Re: [PATCH] RISC-V: Fix vec_init for simple sequences [PR114028].

2024-02-23 Thread Robin Dapp
> +/* { dg-final { scan-assembler-times "vmv\.v\.i\tv\[0-9\],0" 0 } } */ > > I think you should use "scan-assembler-not" Thanks, going to commit with that change. Regards Robin

Re: [PATCH] RISC-V: Fix vec_init for simple sequences [PR114028].

2024-02-22 Thread juzhe.zh...@rivai.ai
vai.ai CC: rdapp.gcc; jeffreyalaw Subject: [PATCH] RISC-V: Fix vec_init for simple sequences [PR114028]. Hi, for a vec_init (_a, _a, _a, _a) with _a of mode DImode we try to construct a "superword" of two "_a"s. This only works for modes < Pmode when we can "shift and or

Re: [PATCH] RISC-V: Fix vec_init for simple sequences [PR114028].

2024-02-22 Thread juzhe.zh...@rivai.ai
lgtm. juzhe.zh...@rivai.ai From: Robin Dapp Date: 2024-02-23 04:02 To: gcc-patches; palmer; Kito Cheng; juzhe.zh...@rivai.ai CC: rdapp.gcc; jeffreyalaw Subject: [PATCH] RISC-V: Fix vec_init for simple sequences [PR114028]. Hi, for a vec_init (_a, _a, _a, _a) with _a of mode DImode we try

[PATCH] RISC-V: Fix vec_init for simple sequences [PR114028].

2024-02-22 Thread Robin Dapp
Hi, for a vec_init (_a, _a, _a, _a) with _a of mode DImode we try to construct a "superword" of two "_a"s. This only works for modes < Pmode when we can "shift and or" two halves into one Pmode register. This patch disallows the optimization for inner_mode == Pmode and emits a simple broadcast