Re: [PATCH] RISC-V: Optimize slli(.uw)? + addw + zext.w into sh[123]add + zext.w

On Fri, 18 Nov 2022 at 20:52, Jeff Law wrote: > Something to consider. We're gaining a lot of > > (subreg:SI (reg:DI) 0) kinds of operands. > > > Would it make sense to make an operand predicate that accepted > > (reg:SI) or (subreg:SI (reg:DI) 0)? > > > It will reduce my compaints about

Re: [PATCH] RISC-V: Optimize slli(.uw)? + addw + zext.w into sh[123]add + zext.w

Applied to master. Thanks. --Philipp. On Fri, 18 Nov 2022 at 20:52, Jeff Law wrote: > > On 11/8/22 12:57, Philipp Tomsich wrote: > > gcc/ChangeLog: > > > > * config/riscv/bitmanip.md: Handle corner-cases for combine > > when chaining slli(.uw)? + addw > > > >

Re: [PATCH] RISC-V: Optimize slli(.uw)? + addw + zext.w into sh[123]add + zext.w

On 11/8/22 12:57, Philipp Tomsich wrote: gcc/ChangeLog: * config/riscv/bitmanip.md: Handle corner-cases for combine when chaining slli(.uw)? + addw gcc/testsuite/ChangeLog: * gcc.target/riscv/zba-shNadd-04.c: New test. OK. Something to consider.  We're gaining a

[PATCH] RISC-V: Optimize slli(.uw)? + addw + zext.w into sh[123]add + zext.w

gcc/ChangeLog: * config/riscv/bitmanip.md: Handle corner-cases for combine when chaining slli(.uw)? + addw gcc/testsuite/ChangeLog: * gcc.target/riscv/zba-shNadd-04.c: New test. --- gcc/config/riscv/bitmanip.md | 49 +++