On 10/31/22 05:38, Tamar Christina via Gcc-patches wrote:
Hi All,
This is a respin with all feedback addressed.
Bootstrapped Regtested on aarch64-none-linux-gnu and no issues.
Ok for master?
Thanks,
Tamar
gcc/ChangeLog:
* match.pd: Add fneg/fadd rule.
gcc/testsuite/ChangeLog:
Hi All,
This is a respin with all feedback addressed.
Bootstrapped Regtested on aarch64-none-linux-gnu and no issues.
Ok for master?
Thanks,
Tamar
gcc/ChangeLog:
* match.pd: Add fneg/fadd rule.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/simd/addsub_1.c: New test.
ener
> > Cc: Richard Sandiford ; nd ;
> > Tamar Christina via Gcc-patches ;
> > juzhe.zh...@rivai.ai
> > Subject: RE: [PATCH]middle-end Add optimized float addsub without
> > needing VEC_PERM_EXPR.
> >
> > > -Original Message-
> > > From
;
> juzhe.zh...@rivai.ai
> Subject: RE: [PATCH]middle-end Add optimized float addsub without
> needing VEC_PERM_EXPR.
>
> > -Original Message-
> > From: Richard Biener
> > Sent: Friday, September 23, 2022 8:54 AM
> > To: Tamar Christina
> >
> -Original Message-
> From: Richard Biener
> Sent: Friday, September 23, 2022 8:54 AM
> To: Tamar Christina
> Cc: Richard Sandiford ; Tamar Christina via
> Gcc-patches ; nd ;
> juzhe.zh...@rivai.ai
> Subject: RE: [PATCH]middle-end Add optimized float
So far I didn't see the case that V2DF <-> V4SF in RISC-V.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2022-09-23 20:54
To: Tamar Christina
CC: Richard Sandiford; Tamar Christina via Gcc-patches; nd; juzhe.zhong
Subject: RE: [PATCH]middle-end Add optimized float addsub without n
On Fri, 23 Sep 2022, Tamar Christina wrote:
> Hi,
>
> Attached is the respun version of the patch,
>
> > >>
> > >> Wouldn't a target need to re-check if lanes are NaN or denormal if
> > >> after a SFmode lane operation a DFmode lane operation follows? IIRC
> > >> that is what usually makes
Hi,
Attached is the respun version of the patch,
> >>
> >> Wouldn't a target need to re-check if lanes are NaN or denormal if
> >> after a SFmode lane operation a DFmode lane operation follows? IIRC
> >> that is what usually makes punning "integer" vectors as FP vectors costly.
I don't believe
On 6/20/2022 5:56 AM, Richard Biener via Gcc-patches wrote:
Note one option would be to emit a multiply with { 1, -1, 1, -1 } on
GIMPLE where then targets could opt-in to handle this via a DFmode
negate via a combine pattern? Not sure if this can be even done
starting from the vec-perm RTL
On 6/17/2022 2:33 PM, Andrew Pinski via Gcc-patches wrote:
On Thu, Jun 16, 2022 at 3:59 AM Tamar Christina via Gcc-patches
wrote:
Hi All,
For IEEE 754 floating point formats we can replace a sequence of alternative
+/- with fneg of a wider type followed by an fadd. This eliminated the
Tamar Christina via Gcc-patches writes:
>> -Original Message-
>> From: Richard Biener
>> Sent: Monday, June 20, 2022 12:56 PM
>> To: Tamar Christina
>> Cc: Andrew Pinski via Gcc-patches ; nd
>>
>> Subject: RE: [PATCH]middle-end Add
> -Original Message-
> From: Richard Biener
> Sent: Monday, June 20, 2022 12:56 PM
> To: Tamar Christina
> Cc: Andrew Pinski via Gcc-patches ; nd
>
> Subject: RE: [PATCH]middle-end Add optimized float addsub without
> needing VEC_PERM_EXPR.
>
> On Mon
On Mon, 20 Jun 2022, Tamar Christina wrote:
> > -Original Message-
> > From: Richard Biener
> > Sent: Saturday, June 18, 2022 11:49 AM
> > To: Andrew Pinski via Gcc-patches
> > Cc: Tamar Christina ; nd
> > Subject: Re: [PATCH]middle-end Add optimi
> -Original Message-
> From: Richard Biener
> Sent: Saturday, June 18, 2022 11:49 AM
> To: Andrew Pinski via Gcc-patches
> Cc: Tamar Christina ; nd
> Subject: Re: [PATCH]middle-end Add optimized float addsub without
> needing VEC_PERM_EXPR.
>
>
>
>
> Am 17.06.2022 um 22:34 schrieb Andrew Pinski via Gcc-patches
> :
>
> On Thu, Jun 16, 2022 at 3:59 AM Tamar Christina via Gcc-patches
> wrote:
>>
>> Hi All,
>>
>> For IEEE 754 floating point formats we can replace a sequence of alternative
>> +/- with fneg of a wider type followed by an
On Thu, Jun 16, 2022 at 3:59 AM Tamar Christina via Gcc-patches
wrote:
>
> Hi All,
>
> For IEEE 754 floating point formats we can replace a sequence of alternative
> +/- with fneg of a wider type followed by an fadd. This eliminated the need
> for
> using a permutation. This patch adds a
Hi All,
For IEEE 754 floating point formats we can replace a sequence of alternative
+/- with fneg of a wider type followed by an fadd. This eliminated the need for
using a permutation. This patch adds a math.pd rule to recognize and do this
rewriting.
For
void f (float *restrict a, float
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