This series is a prototype for adding all typed instructions to a dfa scheduling pipeline.
I've been working on adding insn reservations for all typed instructions to ensure all instructions are part of a dfa pipeline. I don't have a good understanding of vector instruction latency, so I have been struggling with what I should do for those. As of right now, I have copied the insn reservations from generic-ooo.md for vector instructions into the generic.md and sifive-7.md files. This prevents ICEs from enabling the assert but introduces numerous scan dump failures (when tested in linux rv64gcv and rv64gc_zba_zbb_zbc_zbs). Currently, only patch 1/3 RISC-V: Add non-vector types to pipelines does not introduce regressions (when tested against linux rv32/64 gc/gcv on rocket). I hope that the locations I added the insn types make sense. Please let me know if they should change. The final patch enables the assert for insn_has_dfa_reservation. I tested the full patch series on both rocket and sifive-7-series. The series does introduce additional scan dump failures compared to their respective baselines, however, I'm not sure how many failures were due to the patch vs incorrect modeling assumptions. I created PR113035 which has the full testsuite failures I saw (without the patches applied). Edwin Lu (3): RISC-V: Add non-vector types to pipelines RISC-V: Add vector related reservations RISC-V: Enable assert for insn_has_dfa_reservation gcc/config/riscv/generic-ooo.md | 31 ++++---- gcc/config/riscv/generic.md | 131 +++++++++++++++++++++++++++++++- gcc/config/riscv/riscv.cc | 2 - gcc/config/riscv/sifive-7.md | 130 ++++++++++++++++++++++++++++++- 4 files changed, 271 insertions(+), 23 deletions(-) -- 2.34.1
