On Fri, Mar 1, 2024 at 4:07 AM Robin Dapp wrote:
>
> Hi Han,
>
> in addition to what Juzhe mentioned (and that late-combine is going
> to handle such cases) it should be noted that register pressure
> should not be the only consideration here. Many uarchs have a higher
> latency for
Hi Han,
in addition to what Juzhe mentioned (and that late-combine is going
to handle such cases) it should be noted that register pressure
should not be the only consideration here. Many uarchs have a higher
latency for register-file-crossing moves. At least without spilling
the vv variant is
Hi, han. My comment for this patch is same as
[PATCH 3/5] RISC-V: Support vmfxx.vf for autovec comparison of vec and imm
--Original--
From: "demin.han"
Similar to previous float change, vmsxx.vx is needed.
1. Only those which can't match vi should use vx.
2. DImode is processed by sew64_scalar_helper.
Tested on RV32 and RV64.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (get_cmp_insn_code): Select scalar pattern
(expand_vec_cmp):
