Thanks for taking care of this issue.
Ok to backport GCC-13.
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-08-28 10:33
To: xuli1; gcc-patches
CC: kito.cheng; palmer; juzhe.zhong
Subject: Re: [PATCH V2] RISC-V: Insert vsetivli zero, 0 for vmv.x.s/vfmv.f.s
instructions satisfying REG_P(operand[1
This patch should be backported to releases/gcc-13 to addressÂ
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111076
--
Li Xu
>This issue happens is because the operand1 of scalar move can be
>REG_P (operand[1]) in the O0 case, which causes the VSETVL PASS to
>not insert the vsetvl
to.cheng; palmer; juzhe.zhong; Li Xu
> Subject: [PATCH V2] RISC-V: Insert vsetivli zero, 0 for vmv.x.s/vfmv.f.s
> instructions satisfying REG_P(operand[1]) in -O0.
> This issue happens is because the operand1 of scalar move can be
> REG_P (operand[1]) in the O0 case, which causes the VS
LGTM. Let's wait for kito's feedback.
Thanks :)
juzhe.zh...@rivai.ai
From: Li Xu
Date: 2023-05-10 12:02
To: gcc-patches
CC: kito.cheng; palmer; juzhe.zhong; Li Xu
Subject: [PATCH V2] RISC-V: Insert vsetivli zero, 0 for vmv.x.s/vfmv.f.s
instructions satisfying REG_P(operand[1]) in -O0
This issue happens is because the operand1 of scalar move can be
REG_P (operand[1]) in the O0 case, which causes the VSETVL PASS to
not insert the vsetvl instruction correctly, and the compiler crashes.
Consider this following case:
int16_t foo1 (void *base, size_t vl)
{
int16_t maxVal =
