Re: [PATCH V2] RISC-V: Support one more overlap for wv instructions

OK. Regards Robin

[PATCH V2] RISC-V: Support one more overlap for wv instructions

For 'wv' instructions, e.g. vwadd.wv vd,vs2,vs1. vs2 has same EEW as vd. vs1 has smaller than vd. So, vs2 can overlap with vd, but vs1 can only overlap highest-number of vd when LMUL of vs1 is greater than 1. We already have supported overlap for vs1 LMUL >= 1. But I forget vs1 LMUL < 1, vs2