On 9/27/23 19:31, Jeff Law wrote:
On 9/27/23 04:14, juzhe.zh...@rivai.ai wrote:
Since after removing mem-to-mem pattern.
program main
integer, dimension(:,:), allocatable :: a, b
integer, dimension(:), allocatable :: sh
allocate (a(2,2))
allocate (b(2,2))
allocate (sh(3))
a
On 9/27/23 04:14, juzhe.zh...@rivai.ai wrote:
Since after removing mem-to-mem pattern.
program main
integer, dimension(:,:), allocatable :: a, b
integer, dimension(:), allocatable :: sh
allocate (a(2,2))
allocate (b(2,2))
allocate (sh(3))
a = 1
b = cshift(a,sh)
end
On 9/27/23 03:38, juzhe.zh...@rivai.ai wrote:
>> Why add `can_create_pseudo_p ()` here? this will split after reload,
but we forbid that pattern between reload and split2?
I have no ideal. Some fortran tests just need recognization of
mem-to-mem pattern before RA
I don't know the
pattern.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-09-27 18:07
To: juzhe.zh...@rivai.ai
CC: kito.cheng; gcc-patches; jeffreyalaw; Robin Dapp
Subject: Re: Re: [PATCH V3] RISC-V: Remove mem-to-mem VLS move pattern[PR111566]
I can understand why remove mem to mem pattern, but why the normal mov
17:33
> To: Juzhe-Zhong
> CC: gcc-patches; kito.cheng; jeffreyalaw; rdapp.gcc
> Subject: Re: [PATCH V3] RISC-V: Remove mem-to-mem VLS move pattern[PR111566]
> > (define_insn_and_split "*mov"
> >[(set (match_operand:VLS_AVL_IMM 0 "reg_or_mem_operan
o Cheng
Date: 2023-09-27 17:33
To: Juzhe-Zhong
CC: gcc-patches; kito.cheng; jeffreyalaw; rdapp.gcc
Subject: Re: [PATCH V3] RISC-V: Remove mem-to-mem VLS move pattern[PR111566]
> (define_insn_and_split "*mov"
>[(set (match_operand:VLS_AVL_IMM 0 &quo
> (define_insn_and_split "*mov"
>[(set (match_operand:VLS_AVL_IMM 0 "reg_or_mem_operand" "=vr, m, vr")
> (match_operand:VLS_AVL_IMM 1 "reg_or_mem_operand" " m,vr, vr"))]
>"TARGET_VECTOR
> - && (register_operand (operands[0], mode)
> + && (can_create_pseudo_p ()
Why add
PR target/111566
gcc/ChangeLog:
* config/riscv/vector.md (*mov_mem_to_mem): Remove.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls/mov-1.c: Adapt test.
* gcc.target/riscv/rvv/autovec/vls/mov-10.c: Ditto.
*
