Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Thursday, April 25, 2024 5:27 PM
To: Li, Pan2 ; gcc-patches
Cc: kito.cheng ; Robin Dapp ; Li,
Pan2 ; Kito.cheng
Subject: Re: [PATCH v1] RISC-V: Add test cases for insn does not satisfy its
constraints [PR114714]
LGTM. THANKS
LGTM. THANKS
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-04-25 17:25
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; Pan Li; Kito Cheng
Subject: [PATCH v1] RISC-V: Add test cases for insn does not satisfy its
constraints [PR114714]
From: Pan Li
We have one ICE when RVV register
From: Pan Li
We have one ICE when RVV register overlap is enabled. We reverted this
feature as it is in stage 4 and there is no much time to figure a better
solution for this. Thus, for now add the related test cases which will
trigger ICE when register overlap enabled.
This will gate the RVV
