On Wed, 17 Nov 2021 at 20:40, Palmer Dabbelt wrote:
> [This is my first time trying my Rivos address on the lists, so sorry if
> something goes off the rails.]
>
> On Wed, 17 Nov 2021 06:05:04 PST (-0800), gcc-patches@gcc.gnu.org wrote:
> > Hi Philipp:
> >
> > Thanks for the patch, I like this
[This is my first time trying my Rivos address on the lists, so sorry if
something goes off the rails.]
On Wed, 17 Nov 2021 06:05:04 PST (-0800), gcc-patches@gcc.gnu.org wrote:
Hi Philipp:
Thanks for the patch, I like this approach, that can easily configure
different capabilities for each
Hi Philipp:
Thanks for the patch, I like this approach, that can easily configure
different capabilities for each core :)
So there are only a few minor comments for this patch.
On Mon, Nov 15, 2021 at 5:49 AM Philipp Tomsich
wrote:
>
> From: Philipp Tomsich
>
> The Ventana VT1 core supports
From: Philipp Tomsich
The Ventana VT1 core supports quad-issue and instruction fusion.
This implemented TARGET_SCHED_MACRO_FUSION_P to keep fusible sequences
together and adds idiom matcheing for the supported fusion cases.
gcc/ChangeLog:
* config/riscv/riscv.c (enum
