When if-conversion in noce_try_store_flag_mask starts the sequence off
with an order-operator, our patterns for vt.maskc<n> will receive the
result of the order-operator as a register argument; consequently,
they can't know that the result will be either 1 or 0.
To convey this information (and make vt.maskc<n> applicable), we wrap
the result of the order-operator in a eq/ne against (const_int 0).
This commit adds the split pattern to handle these cases.
During if-conversion, if noce_try_store_flag_mask succeeds, we may see
if (cur < next) {
next = 0;
}
transformed into
27: r82:SI=ltu(r76:DI,r75:DI)
REG_DEAD r76:DI
28: r81:SI=r82:SI^0x1
REG_DEAD r82:SI
29: r80:DI=zero_extend(r81:SI)
REG_DEAD r81:SI
This currently escapes the combiner, as RISC-V does not have a pattern
to apply the 'slt' instruction to 'geu' verbs. By adding a pattern in
this commit, we match such cases.
gcc/ChangeLog:
* config/riscv/xventanacondops.md: Add split to wrap an an
order-operator suitably for generating vt.maskc<n>.
* config/riscv/predicates.md (anyge_operator): Define.
(anygt_operator): Define.
(anyle_operator): Define.
(anylt_operator): Define.
* config/riscv/riscv.md: Helpers for ge(u) & le(u).
gcc/testsuite/ChangeLog:
* gcc.target/riscv/xventanacondops-le-01.c: New test.
* gcc.target/riscv/xventanacondops-lt-03.c: New test.
Signed-off-by: Philipp Tomsich <philipp.toms...@vrull.eu>
---
Changes in v2:
- Fixed a pattern that was truncated during a rebase (last line
missing).
- Ran whitespace-cleanup on xventanacondops-le-01.c
- Ran whitespace-cleanup on xventanacondops-lt-03.c
gcc/config/riscv/predicates.md | 12 +++++
gcc/config/riscv/riscv.md | 26 +++++++++++
gcc/config/riscv/xventanacondops.md | 46 +++++++++++++++++++
.../gcc.target/riscv/xventanacondops-le-01.c | 16 +++++++
.../gcc.target/riscv/xventanacondops-lt-03.c | 16 +++++++
5 files changed, 116 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-lt-03.c
diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index b368c11c930..490bff688a7 100644
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -204,6 +204,18 @@
(define_predicate "equality_operator"
(match_code "eq,ne"))
+(define_predicate "anyge_operator"
+ (match_code "ge,geu"))
+
+(define_predicate "anygt_operator"
+ (match_code "gt,gtu"))
+
+(define_predicate "anyle_operator"
+ (match_code "le,leu"))
+
+(define_predicate "anylt_operator"
+ (match_code "lt,ltu"))
+
(define_predicate "order_operator"
(match_code "eq,ne,lt,ltu,le,leu,ge,geu,gt,gtu"))
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 4331842b7b2..d1f3270a3c8 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2636,6 +2636,19 @@
[(set_attr "type" "slt")
(set_attr "mode" "<X:MODE>")])
+(define_split
+ [(set (match_operand:GPR 0 "register_operand")
+ (match_operator:GPR 1 "anyle_operator"
+ [(match_operand:X 2 "register_operand")
+ (match_operand:X 3 "register_operand")]))]
+ "TARGET_XVENTANACONDOPS"
+ [(set (match_dup 0) (match_dup 4))
+ (set (match_dup 0) (eq:GPR (match_dup 0) (const_int 0)))]
+ {
+ operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == LE ? LT : LTU,
+ <GPR:MODE>mode, operands[3], operands[2]);
+ })
+
(define_insn "*slt<u>_<X:mode><GPR:mode>"
[(set (match_operand:GPR 0 "register_operand" "= r")
(any_lt:GPR (match_operand:X 1 "register_operand" " r")
@@ -2657,6 +2670,19 @@
[(set_attr "type" "slt")
(set_attr "mode" "<X:MODE>")])
+(define_split
+ [(set (match_operand:GPR 0 "register_operand")
+ (match_operator:GPR 1 "anyge_operator"
+ [(match_operand:X 2 "register_operand")
+ (match_operand:X 3 "register_operand")]))]
+ "TARGET_XVENTANACONDOPS"
+ [(set (match_dup 0) (match_dup 4))
+ (set (match_dup 0) (eq:GPR (match_dup 0) (const_int 0)))]
+{
+ operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == GE ? LT : LTU,
+ <GPR:MODE>mode, operands[2], operands[3]);
+})
+
;;
;; ....................
;;
diff --git a/gcc/config/riscv/xventanacondops.md
b/gcc/config/riscv/xventanacondops.md
index 641cef0e44e..f23058b95b2 100644
--- a/gcc/config/riscv/xventanacondops.md
+++ b/gcc/config/riscv/xventanacondops.md
@@ -28,3 +28,49 @@
(match_operand:DI 2 "register_operand" "r")))]
"TARGET_XVENTANACONDOPS"
"vt.maskc<n>\t%0,%2,%1")
+
+;; Make order operators digestible to the vt.maskc<n> logic by
+;; wrapping their result in a comparison against (const_int 0).
+
+;; "a >= b" is "!(a < b)"
+(define_split
+ [(set (match_operand:X 0 "register_operand")
+ (and:X (neg:X (match_operator:X 1 "anyge_operator"
+ [(match_operand:X 2 "register_operand")
+ (match_operand:X 3 "register_operand")]))
+ (match_operand:X 4 "register_operand")))
+ (clobber (match_operand:X 5 "register_operand"))]
+ "TARGET_XVENTANACONDOPS"
+ [(set (match_dup 5) (match_dup 6))
+ (set (match_dup 0) (and:X (neg:X (eq:X (match_dup 5) (const_int 0)))
+ (match_dup 4)))]
+{
+ operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == GE ? LT : LTU,
+ <X:MODE>mode, operands[2], operands[3]);
+})
+
+;; "a > b"
+(define_split
+ [(set (match_operand:X 0 "register_operand")
+ (and:X (neg:X (match_operator:X 1 "anygt_operator"
+ [(match_operand:X 2 "register_operand")
+ (match_operand:X 3 "register_operand")]))
+ (match_operand:X 4 "register_operand")))
+ (clobber (match_operand:X 5 "register_operand"))]
+ "TARGET_XVENTANACONDOPS"
+ [(set (match_dup 5) (match_dup 1))
+ (set (match_dup 0) (and:X (neg:X (ne:X (match_dup 5) (const_int 0)))
+ (match_dup 4)))])
+
+;; "a <= b" is "!(a > b)"
+(define_split
+ [(set (match_operand:X 0 "register_operand")
+ (and:X (neg:X (match_operator:X 1 "anyle_operator"
+ [(match_operand:X 2 "register_operand")
+ (match_operand:X 3 "arith_operand")]))
+ (match_operand:X 4 "register_operand")))
+ (clobber (match_operand:X 5 "register_operand"))]
+ "TARGET_XVENTANACONDOPS"
+ [(set (match_dup 5) (match_dup 1))
+ (set (match_dup 0) (and:X (neg:X (ne:X (match_dup 5) (const_int 0)))
+ (match_dup 4)))])
diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c
b/gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c
new file mode 100644
index 00000000000..f6f80958e9d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zba_zbb_zbs_xventanacondops -mabi=lp64
-mbranch-cost=4" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" "-Os" "-Oz" } } */
+
+long long sink (long long);
+
+long long lt3 (long long a, long long b)
+{
+ if (a <= b)
+ b = 0;
+
+ return sink(b);
+}
+
+/* { dg-final { scan-assembler-times "sgt\t" 1 } } */
+/* { dg-final { scan-assembler-times "vt.maskc\t" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-lt-03.c
b/gcc/testsuite/gcc.target/riscv/xventanacondops-lt-03.c
new file mode 100644
index 00000000000..f671f357f91
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-lt-03.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zba_zbb_zbs_xventanacondops -mabi=lp64
-mbranch-cost=4" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" "-Os" "-Oz" } } */
+
+long long sink (long long);
+
+long long lt3 (long long a, long long b)
+{
+ if (a < b)
+ b = 0;
+
+ return sink(b);
+}
+
+/* { dg-final { scan-assembler-times "slt\t" 1 } } */
+/* { dg-final { scan-assembler-times "vt.maskcn\t" 1 } } */
--
2.34.1
