Fixes newlib/libgcc build problems, many test cases. No regressions.
Applied.
* config/m32c/cond.md (movqicc_<code>_<mode>): Remove mode of
conditional.
(movhicc_<code>_<mode>): Likewise.
* config/m32c/m32c.c (encode_pattern_1): Specialise PSImode
subregs.
(m32c_eh_return_data_regno): Change to using memregs to avoid
tying up all the compute regs.
(m32c_legitimate_address_p) Subregs are not valid addresses.
Index: config/m32c/cond.md
===================================================================
--- config/m32c/cond.md (revision 217199)
+++ config/m32c/cond.md (working copy)
@@ -201,44 +201,44 @@
""
[(set_attr "flags" "x")]
)
(define_insn_and_split "movqicc_<code>_<mode>"
[(set (match_operand:QI 0 "register_operand" "=R0w")
- (if_then_else:QI (eqne_cond:QI (match_operand:QHPSI 1 "mra_operand"
"RraSd")
- (match_operand:QHPSI 2 "mrai_operand"
"RraSdi"))
+ (if_then_else:QI (eqne_cond (match_operand:QHPSI 1 "mra_operand"
"RraSd")
+ (match_operand:QHPSI 2 "mrai_operand"
"RraSdi"))
(match_operand:QI 3 "const_int_operand" "")
(match_operand:QI 4 "const_int_operand" "")))]
""
"#"
"reload_completed"
[(set (reg:CC FLG_REGNO)
(compare (match_dup 1)
(match_dup 2)))
(set (match_dup 0)
- (if_then_else:QI (eqne_cond:QI (reg:CC FLG_REGNO) (const_int 0))
+ (if_then_else:QI (eqne_cond (reg:CC FLG_REGNO) (const_int 0))
(match_dup 3)
(match_dup 4)))]
""
[(set_attr "flags" "x")]
)
(define_insn_and_split "movhicc_<code>_<mode>"
[(set (match_operand:HI 0 "register_operand" "=R0w")
- (if_then_else:HI (eqne_cond:HI (match_operand:QHPSI 1 "mra_operand"
"RraSd")
- (match_operand:QHPSI 2 "mrai_operand"
"RraSdi"))
- (match_operand:QI 3 "const_int_operand" "")
- (match_operand:QI 4 "const_int_operand" "")))]
+ (if_then_else:HI (eqne_cond (match_operand:QHPSI 1 "mra_operand"
"RraSd")
+ (match_operand:QHPSI 2 "mrai_operand"
"RraSdi"))
+ (match_operand:HI 3 "const_int_operand" "")
+ (match_operand:HI 4 "const_int_operand" "")))]
"TARGET_A24"
"#"
"reload_completed"
[(set (reg:CC FLG_REGNO)
(compare (match_dup 1)
(match_dup 2)))
(set (match_dup 0)
- (if_then_else:HI (eqne_cond:HI (reg:CC FLG_REGNO) (const_int 0))
+ (if_then_else:HI (eqne_cond (reg:CC FLG_REGNO) (const_int 0))
(match_dup 3)
(match_dup 4)))]
""
[(set_attr "flags" "x")]
)
Index: config/m32c/m32c.c
===================================================================
--- config/m32c/m32c.c (revision 217199)
+++ config/m32c/m32c.c (working copy)
@@ -192,12 +192,15 @@ encode_pattern_1 (rtx x)
*patternp++ = 'r';
break;
case SUBREG:
if (GET_MODE_SIZE (GET_MODE (x)) !=
GET_MODE_SIZE (GET_MODE (XEXP (x, 0))))
*patternp++ = 'S';
+ if (GET_MODE (x) == PSImode
+ && GET_CODE (XEXP (x, 0)) == REG)
+ *patternp++ = 'S';
encode_pattern_1 (XEXP (x, 0));
break;
case MEM:
*patternp++ = 'm';
case CONST:
encode_pattern_1 (XEXP (x, 0));
@@ -1005,18 +1008,15 @@ m32c_incoming_return_addr_rtx (void)
int
m32c_eh_return_data_regno (int n)
{
switch (n)
{
case 0:
- return A0_REGNO;
+ return MEM0_REGNO;
case 1:
- if (TARGET_A16)
- return R3_REGNO;
- else
- return R1_REGNO;
+ return MEM0_REGNO+4;
default:
return INVALID_REGNUM;
}
}
/* Implements EH_RETURN_STACKADJ_RTX. Saved and used later in
@@ -1787,12 +1787,14 @@ m32c_legitimate_address_p (machine_mode
/* $sb needs a secondary reload, but since it's involved in
memory address reloads too, we don't deal with it very
well. */
/* case SB_REGNO: */
return 1;
default:
+ if (GET_CODE (reg) == SUBREG)
+ return 0;
if (IS_PSEUDO (reg, strict))
return 1;
return 0;
}
}
return 0;
