y (1,1) size.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-03-02 17:39
To: juzhe.zhong\@rivai.ai
CC: rguenther; pan2.li; gcc-patches; incarnation.p.lee; Kito.cheng
Subject: Re: [PATCH] RISC-V: Bugfix for rvv bool mode precision adjustment
Thanks for the explanation about the sizes.
.
>
> I'm not sure how it works for variable-length types but isn't
> sizeof (vbool8_t) part of the ABI and thus its TYPE_SIZE / GET_MODE_SIZE
> are relevant there? It might of course be that you can never have
> these types as part of aggregates, arrays or objects of them addre
types but isn't
sizeof (vbool8_t) part of the ABI and thus its TYPE_SIZE / GET_MODE_SIZE
are relevant there? It might of course be that you can never have
these types as part of aggregates, arrays or objects of them address-taken
in which case the issue is moot?
Richard.
>
> juzhe.
(vbool8_t) part of the ABI and thus its TYPE_SIZE / GET_MODE_SIZE
are relevant there? It might of course be that you can never have
these types as part of aggregates, arrays or objects of them address-taken
in which case the issue is moot?
Richard.
>
> juzhe.zh...@rivai.ai
>
> From: Rich
@rivai.ai<mailto:juzhe.zh...@rivai.ai>
> mailto:juzhe.zh...@rivai.ai>>
> Sent: Wednesday, March 1, 2023 10:19 PM
> To: rguenther mailto:rguent...@suse.de>>
> Cc: richard.sandiford
> mailto:richard.sandif...@arm.com>>; gcc-patches
> mailto:gcc-patches@gcc.
isor (like
> 1/8 or 2/8) cases.
>
> Could you please share your professional suggestions about this? Thank you
> all again and have a nice day!
>
> Pan
>
> From: juzhe.zh...@rivai.ai
> Sent: Wednesday, March 1, 2023 10:19 PM
> To: rguenther
> Cc: richard.sandiford ; gc
ld you please share your professional suggestions about this? Thank you
> all again and have a nice day!
>
> Pan
>
> From: juzhe.zh...@rivai.ai
> Sent: Wednesday, March 1, 2023 10:19 PM
> To: rguenther
> Cc: richard.sandiford ; gcc-patches
> ; Pan Li ; Li, Pan2
> ; kito
generate"
Pan
From: Li, Pan2
Sent: Wednesday, March 1, 2023 23:42
To: juzhe.zh...@rivai.ai ; rguenther
Cc: richard.sandiford ; gcc-patches
; Pan Li ; kito.cheng
Subject: RE: Re: [PATCH] RISC-V: Bugfix for rvv bool mode precision adjustment
Thanks all for so much valuable a
an2
; kito.cheng
Subject: Re: Re: [PATCH] RISC-V: Bugfix for rvv bool mode precision adjustment
>> So given the above I think that modeling the size as being the same
>> but with accurate precision would work. It's then only the size of the
>> padding in bytes we cannot represent with
cision even though
they have same bytesize.
First we emit vsetvl e8mf8 +vsm for VNx1BI
Then we emit vsetvl e8mf8 + vlm for VNx2BI
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-03-01 22:03
To: juzhe.zhong
CC: richard.sandiford; gcc-patches; Pan Li; pan2.li; kito.cheng
Subject: Re: Re
On Wed, 1 Mar 2023, Richard Biener wrote:
> On Wed, 1 Mar 2023, juzhe.zh...@rivai.ai wrote:
>
> > Let's me first introduce RVV load/store basics and stack allocation.
> > For scalable vector memory allocation, we allocate memory according to
> > machine vector-length.
> > To get this CPU
ata memory access load store behavior.
So given the above I think that modeling the size as being the same
but with accurate precision would work. It's then only the size of the
padding in bytes we cannot represent with poly-int which should be fine.
Correct?
Richard.
> Thanks.
>
>
>
e aware of this . Thanks.
juzhe.zh...@rivai.ai
From: juzhe.zh...@rivai.ai
Date: 2023-03-01 21:50
To: richard.sandiford; gcc-patches
CC: rguenther; Pan Li; pan2.li; kito.cheng
Subject: Re: Re: [PATCH] RISC-V: Bugfix for rvv bool mode precision adjustment
Let's me first introduce RVV load/store basi
-01 21:19
To: Pan Li via Gcc-patches
CC: Richard Biener; Pan Li; juzhe.zhong\@rivai.ai; pan2.li; Kito.cheng
Subject: Re: [PATCH] RISC-V: Bugfix for rvv bool mode precision adjustment
Pan Li via Gcc-patches writes:
> I am not very familiar with the memory pattern, maybe juzhe can provid
On Wed, 1 Mar 2023, Richard Sandiford wrote:
> Pan Li via Gcc-patches writes:
> > I am not very familiar with the memory pattern, maybe juzhe can provide
> > more information or correct me if anything is misleading.
> >
> > The different precision try to resolve the below bugs, the second
Pan Li via Gcc-patches writes:
> I am not very familiar with the memory pattern, maybe juzhe can provide more
> information or correct me if anything is misleading.
>
> The different precision try to resolve the below bugs, the second vlm(with
> different size of load bytes compared to first
,0(a1)
>
> Pan
>
> From: Richard Biener
> Sent: Wednesday, March 1, 2023 20:33
> To: Richard Sandiford
> Cc: 盼 李 via Gcc-patches ; 盼 李
> ; juzhe.zh...@rivai.ai ;
> pan2.li ; Kito.cheng
> Subject: Re: [PATCH] RISC-V: Bugfix for rvv bo
Sent: Wednesday, March 1, 2023 19:11
> > To: 盼 李 via Gcc-patches
> > Cc: juzhe.zh...@rivai.ai ; pan2.li
> > ; 盼 李 ; Kito.cheng
> > ; rguenther
> > Subject: Re: [PATCH] RISC-V: Bugfix for rvv bool mode precision adjustment
> >
> > 盼 李 via Gcc-patches writes:
he impact of data [4, 4] will impact the genmode part, we cannot write
> >> like below as the gcc_unreachable will be hitten.
> >>
> >> if (!can_div_away_from_zero_p (mode_precision[E_%smode], BITS_PER_UNIT,
> >> _size[E_%smode]))
> >> gcc_unreachable
tches
Cc: incarnation.p.lee ; pan2.li
; Kito.cheng ; rguenther
Subject: Re: Re: [PATCH] RISC-V: Bugfix for rvv bool mode precision adjustment
Actually, we just want to differentiate VNx1BI VNx2BI VNx4BI VNx8BI, and they
are considered the same in GCC which produce BUG in RVV currently.
This patch is j
?
Thanks.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-03-01 20:03
To: 盼 李 via Gcc-patches
CC: 盼 李; juzhe.zhong\@rivai.ai; pan2.li; Kito.cheng; rguenther
Subject: Re: [PATCH] RISC-V: Bugfix for rvv bool mode precision adjustment
盼 李 via Gcc-patches writes:
> Just have a t
>
> Pan
>
> From: Richard Sandiford
> Sent: Wednesday, March 1, 2023 19:11
> To: 盼 李 via Gcc-patches
> Cc: juzhe.zh...@rivai.ai ; pan2.li ;
> 盼 李 ; Kito.cheng ;
> rguenther
> Subject: Re: [PATCH] RISC-V: Bugfix for rvv bool mode
__
> juzhe.zh...@rivai.ai
>
> From: Richard Sandiford<mailto:richard.sandif...@arm.com>
> Date: 2023-03-01 18:11
> To: Li\, Pan2<mailto:pan2...@intel.com>
> CC: 盼 李<mailto:incarnation.p....@outlook.com>; incarnation.p.lee--- via
> Gcc-patch
: Richard Sandiford
Sent: Wednesday, March 1, 2023 19:11
To: 盼 李 via Gcc-patches
Cc: juzhe.zh...@rivai.ai ; pan2.li ; 盼
李 ; Kito.cheng ;
rguenther
Subject: Re: [PATCH] RISC-V: Bugfix for rvv bool mode precision adjustment
盼 李 via Gcc-patches writes:
> Thank you all for your quick response.
> gcc_unreachable (); // Hit on [4, 4] of the self-test.
>
> Pan
>
> From: juzhe.zh...@rivai.ai
> Sent: Wednesday, March 1, 2023 18:46
> To: richard.sandiford ; pan2.li
> Cc: incarnation.p.lee ; gcc-patches
> ; Kito.cheng ; rguenther
; pan2.li
Cc: incarnation.p.lee ; gcc-patches
; Kito.cheng ; rguenther
Subject: Re: Re: [PATCH] RISC-V: Bugfix for rvv bool mode precision adjustment
>> Is it right that, for RVV, a load or store of [4,4] will access [8,8]
>>bits, even when that means accessing fully-unused bytes? E.g.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2023-03-01 18:11
To: Li\, Pan2
CC: 盼 李; incarnation.p.lee--- via Gcc-patches; juzhe.zhong\@rivai.ai;
kito.cheng\@sifive.com; rguenther\@suse.de
Subject: Re: [PATCH] RISC-V: Bugfix for rvv bool mode precision adjustment
"Li, Pan2"
ful data when X==3?
Richard
> Pan
>
> From: 盼 李
> Sent: Tuesday, February 28, 2023 5:59 PM
> To: Richard Sandiford ; Li, Pan2
>
> Cc: incarnation.p.lee--- via Gcc-patches ;
> juzhe.zh...@rivai.ai; kito.ch...@sifive.com; rguent...@suse.de
> Su
ailto:kito.ch...@sifive.com>
mailto:kito.ch...@sifive.com>>;
rguent...@suse.de<mailto:rguent...@suse.de>
mailto:rguent...@suse.de>>
Subject: Re: [PATCH] RISC-V: Bugfix for rvv bool mode precision adjustment
"Li, Pan2" mailto:pan2...@intel.com>> writes:
> Hi Ri
...@sifive.com ; rguent...@suse.de
Subject: Re: [PATCH] RISC-V: Bugfix for rvv bool mode precision adjustment
"Li, Pan2" writes:
> Hi Richard Sandiford,
>
> After some investigation, I am not sure if it is possible to make it general
> without any changes to exact_div. We c
please help to share your opinion about this from the expert’s
> perspective ? Thank you!
>
> Pan
>
> From: 盼 李
> Sent: Monday, February 27, 2023 11:13 PM
> To: Richard Sandiford ; incarnation.p.lee--- via
> Gcc-patches
> Cc: juzhe.zh...@rivai.ai; kito.ch...@sifive.com; rguen
please help to share your opinion about this from the expert’s
perspective ? Thank you!
Pan
From: 盼 李
Sent: Monday, February 27, 2023 11:13 PM
To: Richard Sandiford ; incarnation.p.lee--- via
Gcc-patches
Cc: juzhe.zh...@rivai.ai; kito.ch...@sifive.com; rguent...@suse.de; Li, Pan2
Subject: Re:
ent...@suse.de ;
pan2...@intel.com
Subject: Re: [PATCH] RISC-V: Bugfix for rvv bool mode precision adjustment
Sorry for the slow reply, been away for a couple of weeks.
"incarnation.p.lee--- via Gcc-patches" writes:
> From: Pan Li
>
>Fix the bug of the r
Sorry for the slow reply, been away for a couple of weeks.
"incarnation.p.lee--- via Gcc-patches" writes:
> From: Pan Li
>
> Fix the bug of the rvv bool mode precision with the adjustment.
> The bits size of vbool*_t will be adjusted to
> [1, 2, 4, 8, 16, 32, 64] according to
; jeffreyalaw
Subject: RE: Re: [PATCH] RISC-V: Bugfix for rvv bool mode precision adjustment
Hi Richard Sandiford,
Looks like you are busy and stuck in some important work right now, could you
please help to share something like ETA if possible? Then we may have a better
plan for the RVV intrinsic support
.
Pan
From: juzhe.zh...@rivai.ai
Sent: Friday, February 24, 2023 1:08 PM
To: kito.cheng ; Li, Pan2
Cc: richard.sandiford ; incarnation.p.lee
; gcc-patches ;
Kito.cheng ; rguenther ; jeffreyalaw
Subject: Re: Re: [PATCH] RISC-V: Bugfix for rvv bool mode precision adjustment
Hi,
It's been
...@rivai.ai
From: Kito Cheng
Date: 2023-02-21 16:28
To: Li, Pan2
CC: richard.sandif...@arm.com; juzhe.zhong; incarnation.p@outlook.com;
gcc-patches@gcc.gnu.org; kito.ch...@sifive.com; Richard Biener
Subject: Re: [PATCH] RISC-V: Bugfix for rvv bool mode precision adjustment
Hi Richard Sandiford
Message-
> From: Li, Pan2
> Sent: Friday, February 17, 2023 4:39 PM
> To: richard.sandif...@arm.com; juzhe.zhong
> Cc: incarnation.p@outlook.com; gcc-patches@gcc.gnu.org;
> kito.ch...@sifive.com; Richard Biener
> Subject: RE: [PATCH] RISC-V: Bugfix for rvv bool mod
@outlook.com; gcc-patches@gcc.gnu.org;
kito.ch...@sifive.com; Li, Pan2 ; richard.sandif...@arm.com
Subject: Re: [PATCH] RISC-V: Bugfix for rvv bool mode precision adjustment
On Thu, 16 Feb 2023, juzhe.zhong wrote:
> Thanks for the great work to fix this issue for rvv.Hi，richard. This
> is the
...@sifive.com; Li, Pan2 ; richard.sandif...@arm.com
Subject: Re: [PATCH] RISC-V: Bugfix for rvv bool mode precision adjustment
On Thu, 16 Feb 2023, juzhe.zhong wrote:
> Thanks for the great work to fix this issue for rvv.Hi，richard. This
> is the patch to differentiate mask mode of same by
On Thu, 16 Feb 2023, juzhe.zhong wrote:
> Thanks for the great work to fix this issue for rvv.Hi，richard. This is the
> patch to differentiate mask mode of same bytesize. Adjust the precision
> correctly according to rvv isa. Would you mind helping us with this patch ？
> Since it‘s very important
@outlook.com
Cc: gcc-patches@gcc.gnu.org; kito.ch...@sifive.com; rguent...@suse.de; Li, Pan2
Subject: Re: [PATCH] RISC-V: Bugfix for rvv bool mode precision adjustment
Thanks for the great work to fix this issue for rvv.
Hi，richard. This is the patch to differentiate mask mode of same bytesize.
Adjust
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