Re: [PATCH]AArch64: remove reliance on register allocator for simd/gpreg costing. [PR114741]

2024-04-18 Thread Richard Earnshaw (lists)
On 18/04/2024 11:11, Tamar Christina wrote: > Hi All, > > In PR114741 we see that we have a regression in codegen when SVE is enable > where > the simple testcase: > > void foo(unsigned v, unsigned *p) > { > *p = v & 1; > } > > generates > > foo: > fmovs31, w0 > and

[PATCH]AArch64: remove reliance on register allocator for simd/gpreg costing. [PR114741]

2024-04-18 Thread Tamar Christina
Hi All, In PR114741 we see that we have a regression in codegen when SVE is enable where the simple testcase: void foo(unsigned v, unsigned *p) { *p = v & 1; } generates foo: fmovs31, w0 and z31.s, z31.s, #1 str s31, [x1] ret instead of: foo: