Re: makefile - define targets, dependencies in a variable

2006-11-03 Thread psmith
Steve Calfee [EMAIL PROTECTED] writes: So the question is can I define rules in a variable, and maybe give an example? If you're using a sufficiently new make you can, with $(eval ...). define myrule $($1_LIB) : $($($1_LIB)_OBJS) @echo $$($1_LIB)_OBJS $(value $(AR) $(ARFLAGS)

makefile - define targets, dependencies in a variable

2006-11-02 Thread Steve Calfee
Hi, maybe Paul or someone can help on this. I have a pretty large build of multiple source files being built into libraries. In order to minimize duplicate, identical makefiles, I include them with new names defined to do the same thing ie: #list of packages to be built into libraries whole