; $@
%: %.gz
gzcat < $< > $@
So now I'd need to have some overcomplicated logic to write out the
> resulting rules:
>
> d.json: d.json.envsubst
> ...
>
> d.json.envsubst: d.json.envsubst.gz
> ...
>
Why? I don't see why you would need to do that.
Philip Guenther
o build, then it'll ignore the rule.
Thanks for your answer, Bahman. Not sure what "equivalent" means but with
> the following Makefile:
>
> %.a: %.b
>
> a.a: a.c
> echo $^
>
a.a has an explicit rule with a recipe so the %.a:%.b rule has no effect on
the a.a target.
Philip Guenther
d that info and let a second make discover
the real state of the world for itself then it 'works'.
You should probably also check out Paul's whitepaper on VPATH:
http://make.mad-scientist.net/papers/how-not-to-use-vpath/
because what you're appearing to try to do (use VPATH/vpath to place
targets) is walked through in that paper.
Philip Guenther
m. The
workaround is to add "unset MAKELEVEL; " at the start of the recipe, ala:
all:
unset MAKELEVEL; ${MAKE} -C
/home/nataraj/test/make-ci/zzz/build/postgres
I don't recall the details of why MAKELEVEL causes the postgres build to
trip up, but unsetting it has worked for years at $DAYJOB.
Philip Guenther
On Mon, Jun 15, 2020 at 5:16 PM Budi wrote:
> How can we have make's 'include' command in makefile not to precede
> the first/default target in the actual processes?
> I found it always processed the earliest, how to solve this?
>
Can you describe the problem you're trying to solve, and then
e a magic
meaning, making what they mean when mixed with non-pattern targets
ambiguous.
Is there a clean way to write it without splitting the rule and duplicating
> most of the receipt?
>
Put the commands for the rule in a variable and have two rules, one pattern
and one not, that both use the variable as their entire recipe.
Philip Guenther
nding on what v1 and v2 might contain in the full setup, testing
equality can be easy or difficult.
C) do what everyone has done for 40 years: use shell conditionals, ala @ if
[ "$(v1)" = "$(v2)" ]; then echo...; fi
Philip Guenther
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not significant, except for determining the
"default goal": the target for `make' to consider, if you do not
otherwise specify one. The default goal is the target of the first
rule in the first makefile. If the first rule has multiple targets,
only th
le have to match exactly the same string.
So, how is make going to match this:
vitaserve: vitac.c
$(LINK.c) $^ $(LDLIBS) -o $@
with a %:%.c rule? What would the %s *both* match?
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ing whatever canonification that it requires?
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is is to add
VAR-Y=$(VAR-Y) to the $(MAKE) commands being invoked.
Well, the *real* simplest is to make the variable names conform to the
environment syntax, but that isn't always an option.
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l at all, precisely
> because, it is not a valid shell variable.
It would help if you actually showed the EXACT output from running
your hacked make. As is, it is not clear what exactly you're trying
to describe as happening.
Philip Guenther
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is
send to sed via the pipe, is only one long line - with newlines removed. How
can I fix that?
Uh, why are you using echo and $(shell) there instead of just
~/scripts/make/getshadernames src | sed 's/\(.*\)/\textern
char const * const \1;/g' src/shaders.h
?
Philip Guenther
: $(SRCS:.src=.cached)
cat $^ $@
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concept of
generating as part of compilation and then work out the best way to do
that on your system.
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to be done for 'foo2'.
$
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On Fri, Aug 8, 2014 at 7:43 AM, Vance Turnewitsch vance.turn...@gmail.com
wrote:
I'm using Ubuntu 12.04 64bit with make version 3.81-8.1ubuntu1.1 and was
failing to build bitbake recipes. I narrowed it down to an odd problem with
make not expanding variables. I've attached a sample make file
I hate the gmail control-enter -- send keybind
On Fri, Aug 8, 2014 at 8:55 PM, Philip Guenther guent...@gmail.com wrote:
On Fri, Aug 8, 2014 at 7:43 AM, Vance Turnewitsch vance.turn...@gmail.com
wrote:
I'm using Ubuntu 12.04 64bit with make version 3.81-8.1ubuntu1.1 and was
failing
Take 3! #(*$(#*%$
On Fri, Aug 8, 2014 at 8:55 PM, Philip Guenther guent...@gmail.com wrote:
On Fri, Aug 8, 2014 at 7:43 AM, Vance Turnewitsch vance.turn...@gmail.com
wrote:
I'm using Ubuntu 12.04 64bit with make version 3.81-8.1ubuntu1.1 and was
failing to build bitbake recipes. I
On Tue, Jul 8, 2014 at 5:14 AM, Yann Droneaud ydrone...@opteya.com wrote:
Le vendredi 04 juillet 2014 à 12:36 -0700, Philip Guenther a écrit :
...
This can be confirmed by tell make that the RECIPE variable doesn't
need
to be exported. If you add this line to the Makefile
its value at the time it's defined, so having 2 printed as soon as make
start processing seems correct and logical.
At that point, the variable has now been expanded completely, so when time
comes to stuff it into the environment there's no additional output.
Philip Guenther
with a '#' as the start of a comment, so from
there to the end of the line will be ignored. To pass it through you'll
need to quote it either with single or double-quotes, ala:
f:
@echo '$(rez)'
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this following your instructions with GNU make
4.0 (nor with 3.82) on OpenBSD.
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On Mon, Feb 10, 2014 at 8:40 AM, Lutz Kohlrausch lutz.kohlrau...@gmx.de wrote:
In the Makefiles of a build project here, there is a line with two colons. It
seems to define what I would call a target-specific pattern rule. I've
included a simplified example below (see especially line 9).
...
of gcc, as described on that page at the link, but that's
just an optimization.)
If what I wrote doesn't make sense or doesn't seem to work, then READ THAT PAGE.
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not
rebuild the .c file in case any required header is modified.
In addition to the above rule, we also tried using '-include $(C_DEPS), not
no luck..
Without a complete and reproducible example, I don't see how you can
be helped by others then.
Philip Guenther
$(INCS) $(LIBVUTL)($(OBJS)) $(LIBVLIB)
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always agree.
That rule in your makefile violates the above guidance and the odd results
you're experiencing are *exactly* caused by it. Go read that page, as well
as http://make.paulandlesley.org/vpath.html for thoughts on how to solve
your overall problem.
Philip Guenther
real 0m0.00s user 0m0.00s system
$ time make -q N=100
0m0.05s real 0m0.00s user 0m0.00s system
$ time make -q N=1000
0m0.65s real 0m0.39s user 0m0.25s system
$ time make -q N=1
1m49.17s real 1m42.75s user 0m2.91s system
$
Philip Guenther
can't
portably rely on it.
If it's going to be kept (blech), then LINK.o should have $(CFLAGS)
and $(CPPFLAGS) in its expansion.
(Why $(CPPFLAGS) when it's just linking .o files? Because there are
options affect both preprocessing and linking. -fmudflap being the
easiest to see.)
Philip Guenther
.h file(s) are)
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on with some double calling of the makefile and
check if I can get away with the include directive
Ick, that's strictly worse.
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*that* in an $(eval):
$$(foreach index,$$($(1)_TARGET_NUMBERS),$$(eval $$(call
target_assignments,$(1),BIN$$(index
There's probably a better way to fix this by fixing
target_assignments, but the utter lack of comments make me unsure of
how this is being used elsewhere or its intent.
Philip
)
@echo something2
-
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, which will itself be Just Another Input to generating
the executable or library.
So, keep the rule as %.cpp: %.h, but fix it to write to $@. Then
change any $(srcdir)/foo.cpp references to just foo.cpp
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?
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On Sun, Jun 3, 2012 at 8:46 PM, normvcr norm...@telus.net wrote:
Philip Guenther-2 wrote:
...
I believe the most common cause of this is because some makefile rule
builds a file other than $@. In this case, ../src/foo.cpp didn't
exist before the first run but did afterwards, but make didn't
.o files and a
.direxists file that guarantees the target directory is created before
the above rule is run.
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the correct answer is use a different
tool.
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it'll never be a problem.
...but that's not really a topic for this list. Good luck!
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the directory if it doesn't exist?
DIRS = obj bin
$(DIRS):
test -d $@ || mkdir $@
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of `$^' is a list of
all the prerequisites of the rule, including the names of the
directories in which they were found, and the value of `$@' is the
target. Thus:
foo.o : foo.c
cc -c $(CFLAGS) $^ -o $@
--
There's more there, including an example for a .o target.
Philip Guenther
repeatable on my machine. Also, I've seen somebody
else post this sort of output on pastebin, but have seen nothing else
about it.
How did things work out for that person?
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'
make: *** No targets. Stop.
%: %.cc
# recipe to execute (built-in):
$(LINK.cc) $^ $(LOADLIBES) $(LDLIBS) -o $@
$
I would recommend using LDLIBS.
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like this was a bug that was fixed in 3.82, perhaps as a
side-effect of some other fix. Time to upgrade!
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. In the built-in rules, CPPFLAGS is part of the
commands for both C and C++. The variable that is passed to the C++
compiler but not the C compiler is CXXFLAGS.
So, if you want to pass a -D option to the C and C++ compiler, add it
to CPPFLAGS.
Philip Guenther
, $(call variable,param,param,...) )
The former, the values of parameters. This was illustrated by the
reply to you post back in August.
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for `Makefile'?
Your Makefile, if taken literally, would result in an infinite loop,
as make would have to build the Makefile, then reinvoke itself, then
rebuild the Makefile, then reinvoke itself, etc. So, since your
Makefile is broken, *anything* make does is correct. No?
Philip Guenther
are expanded again
later, and everything after the semicolon as the first command in the
rules.
The solution is to hide the semicolon from the first round of make
expansion, ala:
.SECONDEXPANSION:
semi=;
foobar: $$(shell echo prereq$${semi})
touch $@
Philip Guenther
be.
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of shell expansion.
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dir/foobar - dir1/foobar1
$ cat dir/foobar
surprise, this is dir/dir1
$ cd dir
$ cat foobar
surprise, this is dir/dir1
$ cd ../..
$ cat f/dir/foobar
surprise, this is dir/dir1
$
So, what EFFECTIVE FULL PATH does dir/foobar point to? Is that what
you intended it to point to?
Philip Guenther
lrwxr-xr-x 1 root wheel 1 Jul 1 15:19 /etc/malloc.conf - S
$
That 'S' turns on additional checks and operations that aim to
increase the security of the malloc implementation in the face of
application bugs (e.g., better detection of use-after-free and
double-free occurrences).
Philip Guenther
the comment in that rule, then you need to go
find a plain old book about UNIX that talks about symlinks and read
it. This has nothing to do with make and everything to do with how
symlinks operate in UNIX.
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other criteria for deciding to not do the work of searching the entire
filesystem?
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On Sun, Aug 14, 2011 at 5:10 AM, ali hagigat hagigat...@gmail.com wrote:
8.6 The call Function
The call function expands the param arguments before assigning them to
temporary
variables. This means that variable values containing references to
builtin functions that
have special expansion
with whatever dependencies they had elsewhere in the
tree. make all would always build the entire tree, no matter what
your current directory was.
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option and not from
make. If you want to know what make's executing, just make sure the
command doesn't have a leading '@' in the Makefile.
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the initial tab).
If the meaning of that isn't clear, then I suggest you search the
documentation and read the full context.
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above)
$(warning var2=aba)
EXPAND '$(warning var2=aba)' to '' with side-effect of writing
'var2=aba' to the make output
In any case , none of the two functions of aba or kk are called? Why?
The function 'kk' is called, but you changed it's value.
Philip Guenther
Variable Names section in the documentation.
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is set to 'origin' inside
$(map) but, *concurrently*, inside the three calls to
$(verbose_origin), $1 is set to 'o', 'map', and 'MAKE'.
Does that make the documentation's bit about how each gets its own
local values for $(1), etc clearer?
Philip Guenther
})\
)\
)\
)
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and function
expansion in make, and that it doesn't require $(call)?
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the archive for details.
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variable assignment.
Either stick with the docs on your local system (try info 'gnu
make') or keep up with the current version.
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. Can you please explain what contradiction you see?
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On Sat, Apr 23, 2011 at 12:24 AM, Philip Guenther guent...@gmail.com wrote:
On Fri, Apr 22, 2011 at 11:06 PM, ali hagigat hagigat...@gmail.com wrote:
6.12 Pattern-specific Variable Values
This results in more specific variables taking precedence
over the more generic ones...to
I wonder
.
So the manual is correct: longer (more generic) stems are interpreted
before shorter (more specific) stems...but you'll probably be using
normal assignment so that the latter will override the former.
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. If you're interested in reporting
documentation bugs, why haven't you upgraded?
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the
header a.h and run make again and it says nothing needs to be done.
So, that rule correctly generates an a.P file with the dependency
information for a.o. Are you actually using the 'include' directive
in your Makefile to pull that information in? Something like
-include *.P
perhaps?
Philip
here.
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a Makefile per directory (where a
recursive make setup is used for whatever reason) or via a
${OBJDIR}/%.o: ${SRCDIR}/%.c rule for each OBJDIR:SRCDIR pair.
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to make when you add
.SECONDEXPANSION. Read the manual and then think about what variables
contain and whether a second expansion will affect things...
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you're apparently constrained from providing enough information
for other to debug this, I'll suggest you compare the output of the
before-touch and after-touch runs when you run the (inner) make with
the -d option. Good luck!
Philip Guenther
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were not actually performed. Why are expansions skipped and
what can I do to get them working in this case?
The expansion is skipped because you used $$. Why did you use $$?
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subject for a USENIX paper.
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at chapter 6; go back and read chapter 3.7, How `make'
Reads a Makefile, again.
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for an
invalid option).
-o is intentionally ignored, while -g is an invalid option and
therefore silently ignored.)
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-spot for doing the automatic-manual transition is
an aspect of software engineering.
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without requiring that everything be recompiled if a
generated header file is updated.
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software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law.
$
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lines are
processed. It does *NOT* say _anything_ about changing how makefiles
are otherwise parsed. Ergo: no, the rules for how makefile are parsed
are *NOT* modified by .ONESHELL and you MUST precede each recipe line
with a tab.
Philip Guenther
...)'
Generates a fatal error where the message is TEXT. Note that the
error is generated whenever this function is evaluated. So, if
you put it inside a command script or on the right side of a
recursive variable assignment, it won't be evaluated until later.
---
Philip Guenther
of that paragraph. I.e., Make creates files using the rules
entered in its data base.
Personally, this seems like a case where the doc would be better if it
just said build instead of create when referring to make's
operation.
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directories FUD.
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On Wed, Sep 22, 2010 at 5:37 AM, ali hagigat hagigat...@gmail.com wrote:
Why Philip Guenther wrote: Examples cannot explain?!!!
sigh
I wrote Examples cannot explain, they can only demonstrate a subset
of the logic. Paul's example does not explain the logic, it only
demonstrates one particular
search path for 'di2/preq2'? I'm not seeing
what in the description in info pages leads you to that, so I'm not
sure what wording may deserve adjusting...
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cannot identify the bad step in your path to that incorrect
conclusion.
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} depend on *all* the matching .F90 source
files: changing *any* source file would require recompiling *all* the
target files!
Instead, I think you want just a static pattern rule, such as
${TARGET}: %: %.F90 ${OBJECT}
...
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implies errno was EINVAL, which suggests it wasn't a matter of
a bogus pointer (that would have been EFAULT), but some other bogus
bit. Failure to initialize the variable whose address was passed as
the addrlen argument?)
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On Sat, Aug 21, 2010 at 11:13 PM, ali hagigat hagigat...@gmail.com wrote:
Can anyone write an example of a variable defined in a target-specific context?
To quote the info pages that you've been critiquing:
prog : CFLAGS = -g
Philip Guenther
. This
is a workaround, but I don't want to use it. ?
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and touch foo.o to timestamp of foo.c
...
Hmm, how will that work for a file that has multiple dependencies? If
you always use the timestamp of, say, its first dependency, then how
can you determine whether it's out of date with respect to the second
or later dependencies?
Philip Guenther
$
b.txt is out of date with respect to a.txt, so make rebuilds it, but
it isn't actually changed, so make doesn't have to run the commands
for c.txt.
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On Wed, Aug 4, 2010 at 3:51 PM, Peng Yu pengyu...@gmail.com wrote:
On Wed, Aug 4, 2010 at 5:32 PM, Philip Guenther guent...@gmail.com wrote:
On Wed, Aug 4, 2010 at 3:12 PM, Peng Yu pengyu...@gmail.com wrote:
...
Also, to make this work better, I'd like GNU make has the
capability
includes all the involved files would help.
And finally, your makefile is really not in a 'normal' style. The
normal style uses variables and rules to avoid repeating stuff, and
thereby avoid the possibility of typos or errors.
Philip Guenther
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. It can be found on the web at:
http://miller.emu.id.au/pmiller/books/rmch/
Fixing your build system to not use recursive make solves the big
picture problem.
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