ue and see what you get.
Peter Relson
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ially when the possible values are not knowable to a parser)
to be an "INVALID KEYWORD" (as opposed to if the user had coded PLANN(DSNTEP1)
it might have complained that PLANN was an invalid keyword.
Peter Relson
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careless"). Thank you for submitting feedback to get that corrected.
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text as the basis for a display.
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associated with that RB.
Of at least as much importance: Show the data. Including the 8-byte
translation exception address.
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that routine as REFReshable and
put it in SYS1.LINKLIB.
This behavior, when marking the module as refreshable, applies only when the
REFRPROT option of PROGxx is active.
That applies system-wide. As long as that is OK, and you have control of
setting REFRPROT, have at it.
Peter Relson
z/OS Core
for placing a reentrant program into key 0
non-fetch-protected storage depend on authorization and various system-wide
options, along with the possibility of doing an ATTACHX with the KEY=NINE
parameter (which will place into key 0 storage without relying on
authorization).
Peter Relson
z/OS
yte name.
These days, the L/N/SRL has many better alternatives, such as
LLC (of the 2nd byte of RBOPSW) / NILL (to clear the low 4 bits if for some
reason you need to do so).
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e a dataset is being opened. And as you showed you
have TAPEAUTHDSN=YES.
I have no idea if temporary data sets "count" when OPEN is processing, but it
wouldn't shock me.
Peter Relson
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r's regs (for which the answer is different than the psw/key, but
similarly depends on the type of the SVC.
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refer to as low-core protect).
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r SDWAPRIM =
current primary ASID (such as by using EPAR to extract the current primary ASN).
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, serialization may be required when
accessing something other than your address space's data.
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, it is important to identify to which RB you refer.
Peter Relson
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IEANTRTR, exactly like IEANTRT, has authorization-related "limitations" and
authorization-related opportunities.
If you look closely, the non-authorized IEANTRT shows that the level parameter
has 4 choices. The authorized IEANTRT shows that the level parameter has 7
choices. The same is true
You can cancel an STIMER via TTIMER CANCEL.
Peter Relsonz/OS Core Technology Design
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not need to build/touch IQE/IRB. The parameters on SCHEDIRB (such as EPPTR,
MODE, KEY et al) generally cover all the pieces of data that you would set in
the IRB. They do cover all that you showed in your code example. It is
documented that SCHEDIRB is suggested
trol Block, SCB).
When you are providing a code example and there is any possibility that someone
will want to assemble it (perhaps even to try it), please make sure it
assembles or provide guidance on what to do to get it to assemble.
Peter Relson
z/OS Core Technol
of these are sometimes provided by RTM; SDWAMODN and SDWACSCT are often
set by the recovery routine itself.
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(and options)
that you are using. SDWAFMID is set in only a few circumstances, it seems (such
as DAT error), so you won't find that helpful generally.
Note that none of this discussion mentioned (or had a reason to mention) an
RB/XSB pair.
Peter Relson
z/OS Core Technology Design
(whatever that is) in all cases. And no one is going to try to figure
out the exceptions.
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e that the WKAREA default, to register 1, requires that you have set
up AR1 appropriately (to 0 would be most appropriate)
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older time stamp than the one
already captured).
If these two threads were serialized by an ENQ against each other the above
scenario would not happen because thread two would not have been able to get to
the point of capturing its clock value.
Peter Rels
it
finds it (based on such things as your search criteria - JPALPA or just JPA,
for example), then you have a change to get an XTL64.
Peter Relson
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In contents supervisor speak, an extent list contains header information and
then information about the length and address of each (module) extent (whether
mapped by IHAXTLST or IHAXTL64.
As the name implies, XTL64E_EXTENTADDR contains the address of the extent for
this entry. And, not
AFAIK (which admittedly might not be "far" enough), TFP prior to z16 had no
information relevant to STSI.
There are now TFP hardware records that apply variable capacity for which STSI
surfaces information. Possibly QVS should surface that too and might be
enhanced to do so.
Peter Relsonz/OS
The fact that registers are saved (or at least land) in the "new RB" and the
PSW in the "old RB" was described many posts earlier. That applies in all cases
where a new (not "first") RB is created. Note that just when that saving
happens can be kind of funky for a case such as XCTL(X).
The
It was my understanding probably erroneously that when a RB I guess I am
talking about a PRB gets interrupted and that can happen in one of two
instances
1) An SVC
2) A Program check e.g. S0C1,4
It is true that the understanding is erroneous. There are many more cases where
any RB can be
How about: STSI returns a lot of data that is not returned by SYSEVENT QVS? (or
so I assume)
How about: SYSEVENT QVS returns a lot of data that is not provided by STSI? (or
so I assume)
Now, if you were to ask about specific fields in SYSEVENT QVS, I think for
certain ones the answer is
ve the same trailing characters, but
the first (numeric) characters would differ.
If you are referring to data spaces owned by different ASIDs, you might need to
use an ASIDLST and identify the proper set of ASIDs.
Peter Relson
z/OS Co
is that the security product know
what to do to provide you the "decrypted" info
Charles M helped me realize that I was mis-thinking. It's the utoken that can
be "encrypted", not the ACEE.
Thanks, Charles.
Peter Relson
z/OS Co
as-is. It's not truly encrypted such that you need some
cryptography to decrypt it, but the intent is that the security product know
what to do to provide you the "decrypted" info
Peter Relson
z/OS Core Technology Design
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Are you implying that an ESTAE(X) routine with SDWALOC=31 is guaranteed an
SDWA and there is no reason to check R0 for 12 and alternate code paths?
Jon P did write what I meant. Answer: no, it just makes it a lot more likely
that the storage obtain for the SDWA will succeed.
Peter Relson
z/OS
ve to deal with multiple such STIMER's
associated with a task). A single exploiter can use STIMER TASK within the same
task that has multiple exploiters using STIMERM REAL
Using STIMER REAL to monitor task CPU time is not a good fit.
Peter Relson
z/OS Core Technol
;CPU Time limit" (most would not think of it that way if
they see only "time limit").
And there is no "time interval". The STIMER remains in effect as long as it
takes to use that much CPU time.
Peter Relson
z/OS Core Technology Design
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the
case always for such recovery as ESTAEX and ARR).
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SYNCH(X) and thus begins running in a PRB
created by SYNCH processing.
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or to user recovery.
If you're asking about a space-switch PC, that restricts the choices, but the
approach applies.
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es control to an ESTAE. And that's
why the PRB for your ESTAE is separated from the PRB for your mainline by an
SVRB for the SVC D that got you into RTM.
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with
possibly a message such as HZS0025I that mentions BPX1QDB or BPX1ENV)
HZS0109E IBM HEALTH CHECKER FOR Z/OS ADDRESS SPACE USER IDENTITY DOES NOT HAVE
ACCESS TO z/OS UNIX SYSTEM SERVICES
Peter Relson
z/OS Core Technology Design
sdawgrsv wasn’t in either TCB regs or rb regs
If you had done what I written, you would have looked at all the relevant RBs,
not only at a single RB.You apparently looked at the oldest RB. That sounds
like it was the RB associated with the "mainline". Did you look at the
next-oldest RB?
TCBRBP
Simple experimentation will show what you need to know about what is saved
where.
For example, suppose your mainline links to another routine.You mainline's RB
and the LINK target's RB can be examined.
Or suppose your mainline has an ESTAE and abends.You can examine the mainline's
RB, then the
>Could you share why it matters to you if there is a linkage stack entry
(whether before or after getting to the "true routine", even if my guess is
right about what you think of as the "true routines")?
Performance.
That doesn't provide much insight.
What the callable services stub and the
Joe R wrote
I got to a X'89' is a header the doc say that decrementing that would
bring to a new linkage frame I specifically remember looking - 32 bytes from
there and it was all zeros.
Not having ready access to that document, but knowing who wrote it, I'll bet
that it does not say that. It
Here is the SDWA as you can see the PSW matches how come the registers
don't?
Because the registers are not saved in the same RB that the
scrunched-to-8-bytes PSW is saved in.
Peter Relsonz/OS Core Technology Design
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The technical reason "why" is because it would be very difficult to do, would
have adverse performance effects for the system, and there is not at this point
a business case for providing it. So you're not going to get it just because
you think it sounds nice (and even because it sounds
Binyamin wrote does that means that the CSFDLL functions do not create a
linkage stack entry before calling the true routines/
Could you share why it matters to you if there is a linkage stack entry
(whether before or after getting to the "true routine", even if my guess is
right about what you
You originally asked about the syntax error message.
The syntax of the command used was incorrect, and I think the syntax error
message was pretty reasonable.
F HZSPROC,ADDREPLACE,CHECK=(IBMUSS,USS_HFS_DETECTED),USS=YES
ASA101I SYNTAX ERROR: WAS SEEN, WHERE ONE OF 826
(CHECKROUTINE DATE EXEC
"from a linkage stack entry", that would be good to know.
And for that, the information I mentioned above (plus all the data from the
RBs/XSBs) would be needed for diagnosis.
Peter Relson
z/OS Core Technology Design
---
primary address space when the recovery was established)
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d thus how the recovery routine needed to react). The recovery
routine of the PC target would typically not care about where the PC was issued
from. A diagnostician, of course, might well care about both, but they would
typically be looking at a dump.
Peter Relson
z/OS
ize as supervisor state or PSW key 0-7). SRBs (key 0
supervisor state typically) can run in unauthorized address spaces. The
authorization of the address space is not related to the authorization of an
SRB running within that address spa
help
others too by making sure that the flaw is pointed out to those in charge of
changing it (and pointing out on IBM-Main is generally not as helpful as
getting the publication itself updated).
Peter Relson
z/OS Core Technology Design
n-authorized address space at various points code runs
authorized (such as after an SVC or a non-space-switching PC that is defined to
execute in supervisor state and/or a system key).
Peter Relson
z/OS Core Technology Design
---
R15 has bit 63 on I would assume
Yes, reg 15 would be set up to be suitable for use by BSM 0,15 (AKA
"pointer-defined")
hence having bit 63 on when you want the target to be AMODE 64
(as you would need for an address above 2G).
Peter Relson
z/OS Core Technol
located by reg 15.
The system trace entry for that retry contains the value from reg 15, not the
address of CVTBSM0F.
Aside from the trace entry manipulation, you could accomplish this by yourself
with some other register if you had a need.
Peter Relson
z/OS Core Technology Design
s >= x'7000', that correlates
to "the extent is actually above 2G" and in that same entry the length is "1"
(these being indicators that the real extent definition is in the XTL64 because
it does not fit in the XTLST.
Peter Relson
z/OS Core Technology Design
ou have established SPIE/ESPIE for a program interrupt, that
exit will get control even if there is a newer-established ESTAE-type recovery
routine.
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ump of some type. In the "freeing storage" case,
maybe the recovery isn't so much about freeing the storage but more about
capturing data to help someone figure out what went wrong
Peter Relson
z/OS Core Technology Design
---
e SDWA is in the primary address space of the recovery routine given control
(for an FRR, it's in common storage, so the ALET is not important).
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sn't even need to be backed up to get to the right place to re-execute.
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aybe you
have embedded within a structure; maybe your program has a highly limited
amount of dynamic storage available. Those could be cases where you cannot
"tolerate this".
Peter Relson
z/OS Core Technology Design
---
n.
I.e. do your due diligence and "prove it".
Lack of PLISTVER=MAX on the list form can result in the area for the parameter
list being too small, with the result that the execute form expansion overlays
something following it which perhaps something relies upon.
Peter Rels
program, you can use the LOCTR directive to help to "move" data to a separate
area. You might have an area for your "code" and an area for your "static data"
and an area for your "dynamic data"
equire that all the routines have access to the
field where the current level has been saved (so they can increment/decrement
as appropriate), unless (for example) each routine has a recovery block that
keeps track "for it" and some over-arching code can run these blocks and
determine the
the system LX
does not require use of ETCON (aside from by the creator).
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the PC is issued.
You might find IEAARR an interesting middle-ground choice that can be thought
to lie somewhere between ARR and ESTAE/ESTAEX in performance.
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where you specify an asid indicating what address space you want to provide
this service to
You don't "specify". You provide a way for the connector to issue ETCON.
This is all very well described in the extended addressability guide.
Peter Relson
z/OS Core Technol
address space).
Joe R started this whole discussion with a point about TSO TEST hanging. I
proved that it does not always do so, so Joe needs to consider the possibility
that he's doing something in his test environment that is causing this to
happen.
Peter Rels
an "abend" issued by
a task then the register 1 slot of some RB will have the abend code because
Abend itself is a type 2 SVC. Abend's can be issued by CALLRTM TYPE=ABTERM as
well, for example.
If you'd like opinions on what you're doing (especially since this is for
general cons
SVC 122-9 (setting reg 1 to the
bad value for that case)
If you are truly hanging, then you have again omitted important details.
What is it that you are intending to do with "SDWARBAD"?
Peter Relson
z/OS Core Technology Design
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Don't overlook the health checks that can report on CSA/ECSA and SQA/ESQA usage
and provide alerts at stages (and severities) that you define, such as
CHECK(VSM_CSA_THRESHOLD) and CHECK(VSM_SQA_THRESHOLD).
And for understanding who is using what, there is the VERBEXIT VSMDATA OWNCOMM
report
from STIMERM CANCEL, the exit will not run
subsequently (or has already run), so you can free the exit routine's storage.
This is true on all supported releases (it was not true long ago).
Peter Relson
z/OS Core Technology Design
---
David C wrote
in /usr/include/zos (there is a PDS/E ...
The PDSE is shipped as SYS1.SIEAHDR.H
Peter Relson
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ommunication" can be by posting one of the other ECBs.
If you want only to terminate B (disruptively) then use DETACH.
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Regardless of whether it is hard or easy, why would you
want to bother creating a new class when there is an
existing class (XFACILIT) that completely addresses the problem
(and thus would be easier for a customer)?
Peter Relson
z/OS Core Technology Design
nge the "L" to "LLGT" because LLGT is a 6-byte
instruction.
Peter Relson
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this executable), you
will have to change the program.
Please submit feedback on CSV034I to ask to document the return code 14 reason
code 26110021 combination since that is a case that you can actually do
something yourself about and does not need to be reported to IBM Support.
Peter Relson
z/OS Core
. The updated PET is zeroed only on non-0 RC cases. The
"subsequent attempt" result is what you'd expect from passing in a PET of zeros.
Perhaps you can show exactly what your invocation is and exactly what your data
is and the return information.
Peter Relson
z/OS Core Technol
We intend to add WAIT006 and WAIT074 to the VM66721 APAR description to help
with "search findability".
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nder would normally
choose to do).
That seems useful to me.
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ry which is used by the system to decide how to give the module
control on LINK(X) etc
* it affects the allowable RMODE for the section (RMODE 31 conflicts with
AMODE 24) which in turn affects the RMODE of the loadmod / program object
(factoring in the possibility of RMODE=SPLIT for a progr
not asked the question "On my system, what, by default, gets dumped for
an SVC Dump?"
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TA options in effect for the dump that you are
looking at.
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(and later re-do) the allocations it has put in place to
protect you from deleting the data sets in the LNKLST. Once those allocations
are undone, you can deal with an uncataloged data set of the same name as a
data set in the LNKLST.
Peter Relson
z/OS Core Technology Design
examples), please make them via the appropriate feedback mechanisms, not via a
post on IBM-MAIN.
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t yet defined" for cases where you (in effect)
"undefine" a symbol (which I think you can do). It might be that the
no-substitution-done case is "not defined now", covering both "not yet define
the XSSP (defined by BLSRXSSP) has such information as the address of the
target buffer.
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>does the SCHEDIRB wait for IRB completion?
No.
Any coordination between the scheduler of the IRB and the IRB routine itself is
up to the scheduler and IRB routine to provide.
Peter Relson
z/OS Core Technology Des
word).
Manipulation of a variable-length string is going to be very different than
manipulation of a zero-delimited string.
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>There is another solution
What are you thinking the "problem" is for which you mention a "solution"? The
first post I saw was asking about PDF's, not about access to PL/X. Was there a
post that did not show up in the daily digest? The "access-to-PL/X ship" sai
Regarding PL/X documentation, wouldn't sharing such information outside of IBM,
in the absence of having some sort of license agreement, be "bad form" (or
worse)?
Peter Relson
z/OS Core Technology Design
--
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> even Peter Relson wasn't sure if this correct
As this related to a purported need to link with AC=1, I was perfectly sure
that that was not correct. And I remain so.
Joe R: you've mentioned multiple times that you abended after the load.
But did you ever share what abend code and abend rea
be right.
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I don't see an obvious virtual DUALD pointer.
For task, STCBALOV.
For running SRB, LCCAALOV.
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For address spaces known to always be non-swappable, how about ALESERV
ADD and just load the returned ALET into an AR, then SACF 512?
That is a supported method. The "knowing" can be the sticking point.
Peter Relson
z/OS Core Technol
referring to finding what entries there are on the SRB's dispatchable
unit access list?
Peter Relson
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hy cross-memory
servers are required to be in non-swappable address spaces.
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and so that you can retry from a
problem, in order to avoid adversely affecting the task.
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ere the
storage you obtained is in common storage.
In neither of the latter choices would the system ever free the storage
automatically.
Peter Relson
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