Hi, On Sep 17, 12:20 am, Jemshid KK <jemshi...@gmail.com> wrote: > On 23 August 2011 20:44, Syam Krishnan <sya...@gmail.com> wrote: > Can you provide references to support this statement. > > Thank you > Jemshid
Wow! Looks like the wikipedia bug is catching up! No statements without references! Here is the link of reference: http://www.computerworld.com/s/article/87095/Serial_vs._Parallel_Storage [Computerworld: QuickStudy: Serial vs. Parallel Storage] Warning: Annoying ad loads first. You may want to skip it. Basically, the problem is this - Different bits in a single word in a parallel bus reach its destination at different times. This is due to difference in lengths of parallel bit lines, component imperfections etc. So far, this difference was negligible since each word lasted long enough that all bits got enough time to reach the receiver before they were latched. But lately, the speeds have gone up so much, that this differential delay is comparable to the signalling speeds. In other words, some bits of a parallel word may still be only on its way, when the clock signal reaches the destination to latch the word. This causes data word corruption. Thus in a way, the speeds of a parallel bus hit a wall - after which the data is corrupted. Asynchronous serial transfer doesn't have this problem and can be sped up indefinitely (until you hit some other wall!). I hope that was simple enough! Regards, Gokul Das -- "Freedom is the only law". "Freedom Unplugged" http://www.ilug-tvm.org You received this message because you are subscribed to the Google Groups "ilug-tvm" group. To control your subscription visit http://groups.google.co.in/group/ilug-tvm/subscribe To post to this group, send email to ilug-tvm@googlegroups.com To unsubscribe from this group, send email to ilug-tvm-unsubscr...@googlegroups.com For details visit the google group page: http://groups.google.com/group/ilug-tvm?hl=en
