On 5/28/2015 10:14 PM, Chris Wilson wrote:
On Thu, May 28, 2015 at 06:09:34PM +0100, Michel Thierry wrote:
And prevent overflow warning during compilation. We already set this limit
for the GGTT.
This is a temporary patch until a full replacement of size_t variables
(inadequate in 32-bit
On Thu, May 28, 2015 at 07:19:51PM +0100, Damien Lespiau wrote:
On Fri, May 22, 2015 at 11:22:34AM +0300, Mika Kahola wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Print a warning if we fall through the .get_display_clock_speed() function
pointer setup. We end up assuming a
On Thu, May 28, 2015 at 10:26:58AM -0700, Rodrigo Vivi wrote:
With unified modeset and flip paths introduced recently when switching
to fbcon PSR was being disabled on fb_set_par path but re-enabled on
fb_pan_display one, causing missed screen updates and un unusable
console.
Regression
Summary
We covered 5 platforms: Skylake, Braswell, Broadwell, Haswell, Baytrail. In
this test circle, 3 new bugs have been found in manual testing and 1 new bug
has been found in nightly testing.
90675https://bugs.freedesktop.org/show_bug.cgi?id=90675 - [SKL ]Dpy_misc_s3d
fails
On Thu, May 28, 2015 at 05:56:25PM +0100, Chris Wilson wrote:
On Thu, May 28, 2015 at 05:52:21PM +0200, Daniel Vetter wrote:
On Thu, May 28, 2015 at 03:39:26PM +0100, Chris Wilson wrote:
On Wed, May 20, 2015 at 05:00:13PM +0300, David Weinehall wrote:
Export a new context parameter that
On Thu, May 28, 2015 at 11:07:11AM -0700, Rodrigo Vivi wrote:
We cannot let IPS enabled with no plane on the pipe:
BSpec: IPS cannot be enabled until after at least one plane has
been enabled for at least one vertical blank. and IPS must be
disabled while there is still at least one plane
On Thu, May 28, 2015 at 10:21:16AM -0700, Rodrigo Vivi wrote:
Without this frontbuffer flip when enabling planes PSR got compromised
and wasn't being enabled waiting forever on the flush that never
arrived.
Another solution would to create a enable_cursor function and split this
frontbuffer
On Fri, 29 May 2015, Shuah Khan shua...@osg.samsung.com wrote:
I am seeing the following in the dmesg on 4.0.4 with rt patch
[5.720319] [ cut here ]
[5.720347] WARNING: CPU: 6 PID: 466 at
drivers/gpu/drm/i915/intel_display.c:9748
On Thu, 28 May 2015, Paulo Zanoni przan...@gmail.com wrote:
2015-05-28 9:43 GMT-03:00 Jani Nikula jani.nik...@intel.com:
Split intel_hpd_irq_handler into platforms specific and platform
agnostic parts. The platform specific parts decode the registers into
information about which hpd pins
On Fri, May 22, 2015 at 11:22:41AM +0300, Mika Kahola wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
We need to tell BDW ULT and ULX apart.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
v2: Rebased to the latest
v3: Rebased to the latest
Reviewed-by: Mika
On Fri, May 22, 2015 at 11:22:42AM +0300, Mika Kahola wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Add support for changing cdclk frequency during runtime on BDW. The
procedure is quite a bit different on BDW from the one on HSW, so
add a separate function for it.
Also with
On Thu, 28 May 2015, Chris Wilson ch...@chris-wilson.co.uk wrote:
On Thu, May 28, 2015 at 06:32:36PM +0300, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Apparently we can have requests even if though the active list is empty,
so do the request
Silence the following -Wmaybe-uninitialized warnings and make the code
more clear.
drivers/gpu/drm/i915/intel_display.c: In function ‘__intel_set_mode’:
drivers/gpu/drm/i915/intel_display.c:11844:14: warning: ‘crtc_state’ may be
used uninitialized in this function [-Wmaybe-uninitialized]
On Fri, May 22, 2015 at 11:22:40AM +0300, Mika Kahola wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Implement support for changing the cdclk frequency during runtime on
HSW. VLV/CHV already have support for this, so we can follow their
example for the most part. Only the actual
-Original Message-
From: Lespiau, Damien
Sent: Friday, May 29, 2015 2:31 PM
To: Kahola, Mika
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v4 10/12] drm/i915: HSW cdclk support
On Fri, May 22, 2015 at 11:22:40AM +0300, Mika Kahola wrote:
From: Ville Syrjälä
On Fri, May 29, 2015 at 04:06:53PM +0530, Gaurav K Singh wrote:
Allocate gem memory for MIPI DBI command buffer. This memory
will be used when sending command via DBI interface.
Why would you allocate this via gem? AFAICS you only feed the bus
address to the hardware. Using the dma-api would
Changes done in preparation of command mode-
1. Set DBI HS LS Switch bit for DBI packets to be tramitted in HS mode.
2. Set DBI FIFO watermark.
3. Timing regs need not be programmmed for command mode.
Signed-off-by: Gaurav K Singh gaurav.k.si...@intel.com
Signed-off-by: Yogesh Mohan Marimuthu
During enable sequence for MIPI encoder in command mode, enable
MIPI display self-refresh mode bit in Pipe Ctrl reg.
Signed-off-by: Gaurav K Singh gaurav.k.si...@intel.com
Signed-off-by: Yogesh Mohan Marimuthu yogesh.mohan.marimu...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
If MIPI is operated in command mode, and after display reset. if
not even one frame is sent after enabling the pipe and then if it
is disabled, pipe is getting stuck. This patch will fix this issue
by sending one frame after enabling the pipe.
Ideally,there should not be a case where there is
vblank interrupt should be disabled before starting the disable
sequence for MIPI command mode. Otherwise when pipe is disabled
TE interurpt will be still handled and one memory write command
will be sent with pipe disabled. This makes the pipe hw to get
stuck and it doesn't recover in the next
The bpp value which is used while calulating the txbyteclkhs values
should be wrt the pixel format value. Currently bpp is coming
from pipe config to calculate txbyteclkhs.
Signed-off-by: Gaurav K Singh gaurav.k.si...@intel.com
Signed-off-by: Deepak M m.dee...@intel.com
Signed-off-by: Yogesh
While enabling MIPI Port in command mode, enable tearing effect
by GPIO pin.
Signed-off-by: Gaurav K Singh gaurav.k.si...@intel.com
Signed-off-by: Yogesh Mohan Marimuthu yogesh.mohan.marimu...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.c |
Reset the display hardware if video mode to command mode transition
has to be done in MIPI display. otherwise command mode will not work.
Signed-off-by: Yogesh Mohan Marimuthu yogesh.mohan.marimu...@intel.com
Signed-off-by: Gaurav K Singh gaurav.k.si...@intel.com
---
For command mode and video mode, panel prepare, wait for FIFO
checks are required. Making these changes generic across command
mode and video mode.
Signed-off-by: Gaurav K Singh gaurav.k.si...@intel.com
Signed-off-by: Yogesh Mohan Marimuthu yogesh.mohan.marimu...@intel.com
Signed-off-by: Shobhit
I am currently rebasing (yet again) onto a newer nightly tree and going
through the large number of merge conflicts. I have the anti-OLR and
fence patches rebased but am still in the middle of the scheduler ones.
I am hoping to post an updated patch set for anti-OLR at least later today.
On
On 5/22/2015 6:04 PM, Mika Kuoppala wrote:
With BDW/SKL and 32bit addressing mode only, the hardware preloads
pdps. However the TLB invalidation only has effect on levels below
the pdps. This means that if pdps change, hw might access with
stale pdp entry.
To combat this problem, preallocate
This patch will calculate the bandwidth timer for MIPI DBI interface.
If the BW timer value is available from VBT, then value from VBT
will be used.
Signed-off-by: Gaurav K Singh gaurav.k.si...@intel.com
Signed-off-by: Yogesh Mohan Marimuthu yogesh.mohan.marimu...@intel.com
---
Hi,
These set of patches are for enabling DSI command mode. Command Mode refers to
an operation in which transactions primarily take the form of sending commands
and data to a peripheral that incorporates a display controller. The display
controller may include local registers and a frame buffer.
Add functions for DCS memory write command. The mem write
command to send fb data to panel is sent using this function.
Signed-off-by: Gaurav K Singh gaurav.k.si...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
Signed-off-by: Yogesh Mohan Marimuthu
For command mode panel, panel's fb enabling and tearing configuration
is done as part of TEAR ON sequence. This patch parses and executes
TEAR ON sequence for MIPI command mode.
Signed-off-by: Gaurav K Singh gaurav.k.si...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
Allocate gem memory for MIPI DBI command buffer. This memory
will be used when sending command via DBI interface.
Signed-off-by: Yogesh Mohan Marimuthu yogesh.mohan.marimu...@intel.com
Signed-off-by: Gaurav K Singh gaurav.k.si...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
While disabling MIPI Port in command mode, disable TE trigger by GPIO pin.
Signed-off-by: Gaurav K Singh gaurav.k.si...@intel.com
Signed-off-by: Yogesh Mohan Marimuthu yogesh.mohan.marimu...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
---
drivers/gpu/drm/i915/intel_dsi.c |
During disable sequence for MIPI encoder in command mode, disable
MIPI display self-refresh mode bit in Pipe Ctrl reg.
Signed-off-by: Gaurav K Singh gaurav.k.si...@intel.com
Signed-off-by: Yogesh Mohan Marimuthu yogesh.mohan.marimu...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
Simplify intel_hpd_irq_handler() by extracting HPD irq storm detection
to a separate function.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/i915_irq.c | 53 +++--
1 file changed, 40 insertions(+), 13 deletions(-)
diff --git
On Fri, May 29, 2015 at 09:58:33AM +0100, Michel Thierry wrote:
On 5/28/2015 10:14 PM, Chris Wilson wrote:
On Thu, May 28, 2015 at 06:09:34PM +0100, Michel Thierry wrote:
And prevent overflow warning during compilation. We already set this limit
for the GGTT.
This is a temporary patch until
On 5/29/2015 12:05 PM, Michel Thierry wrote:
On 5/22/2015 6:04 PM, Mika Kuoppala wrote:
With BDW/SKL and 32bit addressing mode only, the hardware preloads
pdps. However the TLB invalidation only has effect on levels below
the pdps. This means that if pdps change, hw might access with
stale pdp
We already set this limit for the GGTT.
This is a temporary patch until a full replacement of size_t variables
(inadequate in 32-bit kernel) is in place.
Regression from:
commit a4e0bedca678c81eea4cd79a4bd502335639f73a
Author: Michel Thierry michel.thie...@intel.com
Date:
In some cases it might be unnecessary or dangerous to give userspace
the right to write arbitrary values to some register, even though it
might be desirable to give it control of some of its bits. This patch
extends the register whitelist entries to contain a mask/value pair in
addition to the
Only bit 27 of SCRATCH1 and bit 6 of ROW_CHICKEN3 are allowed to be
set because of security-sensitive bits we don't want userspace to mess
with. On HSW hardware the whitelisted bits control whether atomic
read-modify-write operations are performed on L3 or on GTI, and when
set to L3 (which can be
Until now the software command checker assumed that commands could
read or write at most a single register per packet. This is not
necessarily the case, MI_LOAD_REGISTER_IMM expects a variable-length
list of offset/value pairs and writes them in sequence. The previous
code would only check
On Fri, May 29, 2015 at 01:06:47PM +0100, Kahola, Mika wrote:
static void broxton_modeset_global_resources(struct drm_atomic_state
*old_state)
broxton_set_cdclk(dev, req_cdclk);
}
+/* compute the max rate for new configuration */ static int
+ilk_max_pixel_rate(struct
On ma, 2015-05-18 at 18:46 +0300, Imre Deak wrote:
The divider value to convert from CZ clock rate to ms needs a +1
adjustment on VLV just like on CHV. This matches both the spec and
the accuracy test by pm_rc6_residency.
Testcase: igt/pm_rc6_residency
Signed-off-by: Imre Deak
On Fri, May 29, 2015 at 12:30:41PM +0100, Damien Lespiau wrote:
On Fri, May 22, 2015 at 11:22:40AM +0300, Mika Kahola wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Implement support for changing the cdclk frequency during runtime on
HSW. VLV/CHV already have support for this,
2015-05-29 10:14 GMT-03:00 Jani Nikula jani.nik...@intel.com:
Simplify intel_hpd_irq_handler() by extracting HPD irq storm detection
to a separate function.
Much better!
I'd probably add a verb to the function name, and try to do something
to remove the debug messages from the if statement.
From: John Harrison john.c.harri...@intel.com
The plan is to pass requests around as the basic submission tracking structure
rather than rings and contexts. This patch updates the i915_gem_object_sync()
code path.
v2: Much more complex patch to share a single request between the sync and the
From: John Harrison john.c.harri...@intel.com
In execlist mode, the context object pointer is written in to the request
structure (and reference counted) at the point of request creation. In legacy
mode, this only happens inside i915_add_request().
This patch updates the legacy code path to
From: John Harrison john.c.harri...@intel.com
The render state initialisation code does an explicit i915_add_request() call to
commit the init commands. It was passing in the initialisation batch buffer to
add_request() as the batch object parameter. However, the batch object entry in
the request
From: John Harrison john.c.harri...@intel.com
Now that a single per ring loop is being done for all the different
intialisation steps in i915_gem_init_hw(), it is possible to add proper request
management as well. The last remaining issue is that the context enable call
eventually ends up within
From: John Harrison john.c.harri...@intel.com
Rather than just having a local request variable in the execbuff code, the
request pointer is now stored in the execbuff params structure. Also added
explicit cleanup of the request (plus wiping the OLR to match) in the error
case. This means that the
From: John Harrison john.c.harri...@intel.com
The do_execbuf() function takes quite a few parameters. The actual set of
parameters is going to change with the conversion to passing requests around.
Further, it is due to grow massively with the arrival of the GPU scheduler.
This patch simplifies
From: John Harrison john.c.harri...@intel.com
In order to explcitly track all GPU work (and completely remove the outstanding
lazy request), it is necessary to add extra i915_add_request() calls to various
places. Some of these do not need the implicit cache flush done as part of the
standard
From: John Harrison john.c.harri...@intel.com
The plan is to pass requests around as the basic submission tracking structure
rather than rings and contexts. This patch updates the move_to_gpu() code paths.
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
Reviewed-by: Tomas
From: John Harrison john.c.harri...@intel.com
It is a bad idea for i915_add_request() to fail. The work will already have been
send to the ring and will be processed, but there will not be any tracking or
management of that work.
The only way the add request call can fail is if it can't write
From: John Harrison john.c.harri...@intel.com
The i915_gem_init_hw() function calls a bunch of smaller initialisation
functions. Multiple of which have generic sections and per ring sections. This
means multiple passes are done over the rings. Each pass writes data to the ring
which floats around
From: John Harrison john.c.harri...@intel.com
Now that everything above has been converted to use requests, it is possible to
update init_context() to take a request pointer instead of a ring/context pair.
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
Reviewed-by: Tomas
From: John Harrison john.c.harri...@intel.com
Now that all callers of i915_add_request() have a request pointer to hand, it is
possible to update the add request function to take a request pointer rather
than pulling it out of the OLR.
For: VIZ-5115
Signed-off-by: John Harrison
From: John Harrison john.c.harri...@intel.com
The plan is to pass requests around as the basic submission tracking structure
rather than rings and contexts. This patch updates the
execbuffer_move_to_active() code path.
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
From: John Harrison john.c.harri...@intel.com
The start of day context initialisation code in i915_gem_context_enable() loops
over each ring and calls the legacy switch context or the execlist init context
code as appropriate.
This patch moves the ring looping out of that function in to the top
From: John Harrison john.c.harri...@intel.com
Added explicit request creation and submission to the GPU idle code path.
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
Reviewed-by: Tomas Elf tomas@intel.com
---
drivers/gpu/drm/i915/i915_gem.c | 14 +-
1
From: John Harrison john.c.harri...@intel.com
The i915_add_request() function is called to keep track of work that has been
written to the ring buffer. It adds epilogue commands to track progress (seqno
updates and such), moves the request structure onto the right list and other
such house
From: John Harrison john.c.harri...@intel.com
The final step in removing the OLR from i915_gem_init_hw() is to pass the newly
allocated request structure in to each step rather than passing a ring
structure. This patch updates both i915_ppgtt_init_ring() and
i915_gem_context_enable() to take
From: John Harrison john.c.harri...@intel.com
Now that everything above has been converted to use request structures, it is
possible to update the lower level move_to_active() functions to be request
based as well.
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
Reviewed-by:
From: John Harrison john.c.harri...@intel.com
The overlay update code path to do explicit request creation and submission
rather than relying on the OLR to do the right thing.
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
Reviewed-by: Tomas Elf tomas@intel.com
---
From: John Harrison john.c.harri...@intel.com
Shrunk the parameter list of i915_gem_execbuffer_retire_commands() to a single
structure as everything it requires is available in the execbuff_params object.
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
Reviewed-by: Tomas Elf
From: John Harrison john.c.harri...@intel.com
Updated *_ring_invalidate_all_caches(), i915_reset_gen7_sol_offsets() and
i915_emit_box() to take request structures instead of ring or ringbuf/context
pairs.
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
Reviewed-by: Tomas Elf
From: John Harrison john.c.harri...@intel.com
Converted i915_gem_l3_remap() to take a request structure instead of a ring.
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
Reviewed-by: Tomas Elf tomas@intel.com
---
drivers/gpu/drm/i915/i915_drv.h |2 +-
From: John Harrison john.c.harri...@intel.com
Updated intel_emit_post_sync_nonzero_flush(), gen7_render_ring_cs_stall_wa() and
gen8_emit_pipe_control() to take requests instead of rings.
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
Reviewed-by: Tomas Elf
From: John Harrison john.c.harri...@intel.com
Updated the ring-emit_bb_start() implementation to take a request instead of a
ringbuf/context pair.
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
Reviewed-by: Tomas Elf tomas@intel.com
---
drivers/gpu/drm/i915/intel_lrc.c
From: John Harrison john.c.harri...@intel.com
Updated mi_set_context() to take a request structure instead of a ring and
context pair.
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
Reviewed-by: Tomas Elf tomas@intel.com
---
drivers/gpu/drm/i915/i915_gem_context.c |
From: John Harrison john.c.harri...@intel.com
Updated the display page flip code to do explicit request creation and
submission rather than relying on the OLR and just hoping that the request
actually gets submitted at some random point.
The sequence is now to create a request, queue the work to
From: John Harrison john.c.harri...@intel.com
Now that the request is guaranteed to specify the context, it is possible to
update the context switch code to use requests rather than ring and context
pairs. This patch updates i915_switch_context() accordingly.
Also removed the warning that the
From: John Harrison john.c.harri...@intel.com
A bunch of the low level LRC functions were passing around ringbuf and ctx
pairs. In a few cases, they took the r/c pair and a request as well. This is all
quite messy and unnecesary. The context_queue() call is especially bad since the
fake request
From: John Harrison john.c.harri...@intel.com
As there is no OLR to check, the check_olr() function is now a no-op and can be
removed.
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h |1 -
drivers/gpu/drm/i915/i915_gem.c |
From: John Harrison john.c.harri...@intel.com
Updated a couple of trace points to use the now cached request pointer rather
than extracting it from the ring.
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
Reviewed-by: Tomas Elf tomas@intel.com
---
From: John Harrison john.c.harri...@intel.com
Start of explicit request management in the execbuffer code path. This patch
adds a call to allocate a request structure before all the actual hardware work
is done. Thus guaranteeing that all that work is tagged by a known request. At
present,
From: John Harrison john.c.harri...@intel.com
The alloc_request() function does not actually return the newly allocated
request. Instead, it must be pulled from ring-outstanding_lazy_request. This
patch fixes this so that code can create a request and start using it knowing
exactly which request
From: John Harrison john.c.harri...@intel.com
Updated the two render_state_init() functions to take a request pointer instead
of a ring. This removes their reliance on the OLR.
v2: Rebased to newer tree.
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
Reviewed-by: Tomas Elf
From: John Harrison john.c.harri...@intel.com
In execlist mode, context initialisation is deferred until first use of the
given context. This is because execlist mode has per ring context state and thus
many more context storage objects than legacy mode and many are never actually
used.
From: John Harrison john.c.harri...@intel.com
The seqno value cannot always be used when debugging issues via trace
points. This is because it can be reset back to start, especially
during TDR type tests. Also, when the scheduler arrives the seqno is
only valid while a given request is executing
From: John Harrison john.c.harri...@intel.com
The driver tracks GPU work using request structures. Unfortunately, this
tracking is not currently explicit but is done by means of a catch-all request
that floats around in the background hoovering up work until it gets submitted.
This background
From: John Harrison john.c.harri...@intel.com
Updated do_switch() to take a request pointer instead of a ring/context pair.
v2: Removed some overzealous req- dereferencing.
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
Reviewed-by: Tomas Elf tomas@intel.com
---
From: John Harrison john.c.harri...@intel.com
Now that everything above has been converted to use requests, intel_ring_begin()
can be updated to take a request instead of a ring. This also means that it no
longer needs to lazily allocate a request if no-one happens to have done it
earlier.
For:
From: John Harrison john.c.harri...@intel.com
The LRC submission code requires a request for tracking purposes. It does not
actually require that request to 'complete' it simply uses it for keeping hold
of reference counts on contexts and such like.
Previously, the fall back path of polling for
From: John Harrison john.c.harri...@intel.com
Updated the various ring-flush() functions to take a request instead of a ring.
Also updated the tracer to include the request id.
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
Reviewed-by: Tomas Elf tomas@intel.com
---
From: John Harrison john.c.harri...@intel.com
The i915_gem_object_flush_active() call used to do lots. Over time it has done
less and less. Now all it does check the various associated requests to see if
they can be retired. Hence this patch renames the function and updates the
comments around it
From: John Harrison john.c.harri...@intel.com
The outstanding_lazy_request is no longer used anywhere in the driver.
Everything that was looking at it now has a request explicitly passed in from on
high. Everything that was relying upon it behind the scenes is now explicitly
From: John Harrison john.c.harri...@intel.com
Updated the various ring-dispatch_execbuffer() implementations to take a
request instead of a ring.
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
Reviewed-by: Tomas Elf tomas@intel.com
---
From: John Harrison john.c.harri...@intel.com
In _i915_add_request(), the request is associated with a userland client.
Specifically it is linked to the 'file' structure and the current user process
is recorded. One problem here is that the current user process is not
necessarily the same as when
From: John Harrison john.c.harri...@intel.com
Updated the ring-sync_to() implementations to take a request instead of a ring.
Also updated the tracer to include the request id.
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
Reviewed-by: Tomas Elf tomas@intel.com
---
From: John Harrison john.c.harri...@intel.com
Updated the *_ring_workarounds_emit() functions to take requests instead of
ring/context pairs.
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
Reviewed-by: Tomas Elf tomas@intel.com
---
drivers/gpu/drm/i915/intel_lrc.c
From: John Harrison john.c.harri...@intel.com
Updated the *_ring_flush_all_caches() functions to take requests instead of
rings or ringbuf/context pairs.
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
Reviewed-by: Tomas Elf tomas@intel.com
---
From: John Harrison john.c.harri...@intel.com
Updated the ring-emit_request() implementation to take a request instead of a
ringbuf/request pair. Also removed its use of the OLR for obtaining the
request's seqno.
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
Reviewed-by:
From: John Harrison john.c.harri...@intel.com
Updated the switch_mm() code paths to take a request instead of a ring. This
includes the myriad *_mm_switch functions themselves and a bunch of PDP related
helper functions.
v2: Rebased to newer tree.
For: VIZ-5115
Signed-off-by: John Harrison
From: John Harrison john.c.harri...@intel.com
Updated the various ring-emit_flush() implementations to take a request instead
of a ringbuf/context pair.
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
Reviewed-by: Tomas Elf tomas@intel.com
---
From: John Harrison john.c.harri...@intel.com
Now that the *_ring_begin() functions no longer call the request allocation
code, it is finally safe for the request allocation code to call *_ring_begin().
This is important to guarantee that the space reserved for the subsequent
i915_add_request()
From: John Harrison john.c.harri...@intel.com
Updated the various ring-add_request() implementations to take a request
instead of a ring. This removes their reliance on the OLR to obtain the seqno
value that the request should be tagged with.
For: VIZ-5115
Signed-off-by: John Harrison
From: John Harrison john.c.harri...@intel.com
Updated intel_ring_cacheline_align() to take a request instead of a ring.
For: VIZ-5115
Signed-off-by: John Harrison john.c.harri...@intel.com
Reviewed-by: Tomas Elf tomas@intel.com
---
drivers/gpu/drm/i915/intel_display.c|2 +-
From: John Harrison john.c.harri...@intel.com
Updated the various ring-signal() implementations to take a request instead of
a ring. This removes their reliance on the OLR to obtain the seqno value that
should be used for the signal.
For: VIZ-5115
Signed-off-by: John Harrison
From: John Harrison john.c.harri...@intel.com
Now that everything above has been converted to use requests,
intel_logical_ring_begin() can be updated to take a request instead of a
ringbuf/context pair. This also means that it no longer needs to lazily allocate
a request if no-one happens to have
On Fri, May 29, 2015 at 02:28:09PM +0300, Ander Conselvan de Oliveira wrote:
Silence the following -Wmaybe-uninitialized warnings and make the code
more clear.
drivers/gpu/drm/i915/intel_display.c: In function ‘__intel_set_mode’:
drivers/gpu/drm/i915/intel_display.c:11844:14: warning:
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