== Series Details ==
Series: drm/i915/fbc: More multi-FBC refactoring
URL : https://patchwork.freedesktop.org/series/97821/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10987 -> Patchwork_21810
Summary
---
On Thu, Dec 09, 2021 at 09:15:24PM +0530, Ramalingam C wrote:
> From: Stanislav Lisovskiy
>
> Tile4 in bspec format is 4K tile organized into
> 64B subtiles with same basic shape as for legacy TileY
> which will be supported by Display13.
>
> v2: - Moved Tile4 associating struct for
i915 has squashing for DG2 and crawling for ADLP.
Moving the checks to atomic check phase so
at a later phase we know how the cdclk changes.
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 49 +-
drivers/gpu/drm/i915/i915_drv.h| 11
On Thu, Dec 09, 2021 at 09:15:24PM +0530, Ramalingam C wrote:
> From: Stanislav Lisovskiy
>
> Tile4 in bspec format is 4K tile organized into
> 64B subtiles with same basic shape as for legacy TileY
> which will be supported by Display13.
>
> v2: - Moved Tile4 associating struct for
== Series Details ==
Series: drm/i915/fbc: More multi-FBC refactoring
URL : https://patchwork.freedesktop.org/series/97821/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/fbc: More multi-FBC refactoring
URL : https://patchwork.freedesktop.org/series/97821/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
62abcc4d9d95 drm/i915/fbc: Parametrize FBC register offsets
8d70368946f6 drm/i915/fbc: Loop through FBC
== Series Details ==
Series: use DYNAMIC_DEBUG to implement DRM.debug & DRM.trace (rev4)
URL : https://patchwork.freedesktop.org/series/96327/
State : failure
== Summary ==
Patch is empty.
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git
On 10/27/2021 2:24 PM, Ville Syrjälä wrote:
On Wed, Oct 27, 2021 at 12:57:37PM +0530, Nautiyal, Ankit K wrote:
On 10/15/2021 7:09 PM, Ville Syrjala wrote:
From: Ville Syrjälä
We lack sufficient state tracking to figure out whether
we want the DFP to perform the RGB->YCbCr conversion for us
== Series Details ==
Series: drm/i915/dg2: Enabling 64k page size and flat ccs (rev4)
URL : https://patchwork.freedesktop.org/series/95686/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10985 -> Patchwork_21808
Summary
Adding PCI device ids and enabling ADL-N platform.
ADL-N from i915 point of view is subplatform of ADL-P.
BSpec: 68397
Changes since V2:
- Added version log history
Changes since V1:
- replace IS_ALDERLAKE_N with IS_ADLP_N - Jani Nikula
Signed-off-by: Tejas Upadhyay
---
On 10/15/2021 7:09 PM, Ville Syrjala wrote:
From: Ville Syrjälä
We're currently duplicating the DFP min/max TMDS clock checks
in .mode_valid() and .compute_config(). Extract a helper suitable
for both use cases.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_dp.c |
Adding PCI device ids and enabling ADL-N platform.
ADL-N from i915 point of view is subplatform of ADL-P.
BSpec: 68397
Signed-off-by: Tejas Upadhyay
---
arch/x86/kernel/early-quirks.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 1
== Series Details ==
Series: drm/i915/dg2: Enabling 64k page size and flat ccs (rev4)
URL : https://patchwork.freedesktop.org/series/95686/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/dg2: Enabling 64k page size and flat ccs (rev4)
URL : https://patchwork.freedesktop.org/series/95686/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0390e187560b drm/i915/xehpsdv: enforce min GTT alignment
-:255: WARNING:DEEP_INDENTATION:
From: John Harrison
If the GuC has failed to load for any reason and then the user pokes
the debugfs GuC log interface, a BUG and/or null pointer deref can
occur. Don't let that happen.
Signed-off-by: John Harrison
Reviewed-by: Lucas De Marchi
---
From: John Harrison
Lots of testing is done with the DEBUG_GEM config option enabled but
not the DEBUG_GUC option. That means we only get teeny-tiny GuC logs
which are not hugely useful. Enabling full DEBUG_GUC also spews lots
of other detailed output that is not generally desired. However,
From: John Harrison
It is possible for platforms to require GuC but not HuC firmware.
Also, the firmware versions for GuC and HuC advance independently. So
split the macros up to allow the lists to be maintained separately.
Signed-off-by: John Harrison
Reviewed-by: Lucas De Marchi
From: John Harrison
Add support for telling the debugfs interface the size of the GuC log
dump in advance. Without that, the underlying framework keeps calling
the 'show' function with larger and larger buffer allocations until it
fits. That means reading the log from graphics memory many times
From: John Harrison
Fix a potential null pointer dereference, improve debug crash reports,
improve code separation, improve GuC log read speed.
Signed-off-by: John Harrison
John Harrison (4):
drm/i915/uc: Allow platforms to have GuC but not HuC
drm/i915/guc: Speed up GuC log dumps
== Series Details ==
Series: drm/i915/cdclk: improve abstractions
URL : https://patchwork.freedesktop.org/series/97802/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10984 -> Patchwork_21807
Summary
---
**SUCCESS**
== Series Details ==
Series: drm/i915/cdclk: improve abstractions
URL : https://patchwork.freedesktop.org/series/97802/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/cdclk: improve abstractions
URL : https://patchwork.freedesktop.org/series/97802/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
6f998c44f2eb drm/i915/cdclk: move intel_atomic_check_cdclk() to intel_cdclk.c
9a302307adb3 drm/i915/cdclk:
== Series Details ==
Series: drm/i915: Sanity Check for device memory region (rev4)
URL : https://patchwork.freedesktop.org/series/97715/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10984 -> Patchwork_21806
Summary
== Series Details ==
Series: drm/i915: Sanity Check for device memory region (rev4)
URL : https://patchwork.freedesktop.org/series/97715/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915: Sanity Check for device memory region (rev4)
URL : https://patchwork.freedesktop.org/series/97715/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
41a897d625ae drm/i915: Exclude reserved stolen from driver use
6c0227919313 drm/i915:
== Series Details ==
Series: series starting with [1/3] drm/i915: Fix up pixel_rate vs. clock
confusion in wm calculations
URL : https://patchwork.freedesktop.org/series/97808/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10984 -> Patchwork_21804
== Series Details ==
Series: series starting with [v4,1/6] drm: move the buddy allocator from i915
into common drm (rev3)
URL : https://patchwork.freedesktop.org/series/97476/
State : failure
== Summary ==
Applying: drm: move the buddy allocator from i915 into common drm
Using index info to
== Series Details ==
Series: drm/i915/gem: Use local pointer ttm for __i915_ttm_move (rev3)
URL : https://patchwork.freedesktop.org/series/97572/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10984 -> Patchwork_21803
== Series Details ==
Series: drm/i915/dg2: Use I915_BO_ALLOC_CONTIGUOUS flag for DPT
URL : https://patchwork.freedesktop.org/series/97806/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10984 -> Patchwork_21801
Summary
== Series Details ==
Series: drm/i915: include reductions
URL : https://patchwork.freedesktop.org/series/97789/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/generated/compile.h
CC [M]
Hi Matt,
> > GGTT is currently available both through i915->ggtt and gt->ggtt, and we
> > eventually want to get rid of the i915->ggtt one.
> > Use to_gt() for all i915->ggtt accesses to help with the future
> > refactoring.
>
> I think we can also convert the two references in
== Series Details ==
Series: drm/i915: Don't leak the capture list items
URL : https://patchwork.freedesktop.org/series/97804/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10984 -> Patchwork_21800
Summary
---
From: "Yang, Dong"
With unknow race condition, the i915_request will be added
to intel_context list twice, and result in system panic.
If node alreay exist then do not add it again.
Signed-off-by: Yang, Dong
---
drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 3 +++
1 file changed, 3
Use to_gt() helper consistently throughout the codebase.
Pure mechanical s/i915->gt/to_gt(i915). No functional changes.
Signed-off-by: Andi Shyti
---
Hi,
the inline of i915_dev_to_pxp() was accidentally removed in v6.
Thanks Matt.
Andi
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 4 +++-
1
== Series Details ==
Series: drm/i915/gt: prepare reset based on reset domain
URL : https://patchwork.freedesktop.org/series/97786/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10984 -> Patchwork_21799
Summary
---
== Series Details ==
Series: drm/i915/gt: prepare reset based on reset domain
URL : https://patchwork.freedesktop.org/series/97786/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: series starting with [1/2] drm/i915: Introduce new Tile 4 format
URL : https://patchwork.freedesktop.org/series/97778/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10984 -> Patchwork_21798
On Fri, Dec 10, 2021 at 02:21:53AM +0200, Andi Shyti wrote:
> Hi Matt,
>
> > > -static inline struct intel_pxp *i915_dev_to_pxp(struct device *i915_kdev)
> > > +static struct intel_pxp *i915_dev_to_pxp(struct device *i915_kdev)
> >
> > Was dropping the inline here intentional? It doesn't seem
Hi Matt,
> > -static inline struct intel_pxp *i915_dev_to_pxp(struct device *i915_kdev)
> > +static struct intel_pxp *i915_dev_to_pxp(struct device *i915_kdev)
>
> Was dropping the inline here intentional? It doesn't seem like there's
> any reason to drop it, and if it was intentional the
On Thu, Dec 09, 2021 at 03:25:12PM +0200, Andi Shyti wrote:
> In preparation of the multitile support, highlight the root GT by
> calling it gt0 inside the drm i915 private data.
>
> Signed-off-by: Andi Shyti
> Cc: Chris Wilson
> Cc: Joonas Lahtinen
> Cc: Lucas De Marchi
> Cc: Rodrigo Vivi
>
On Thu, Dec 09, 2021 at 03:25:11PM +0200, Andi Shyti wrote:
> From: Michał Winiarski
>
> GGTT is currently available both through i915->ggtt and gt->ggtt, and we
> eventually want to get rid of the i915->ggtt one.
> Use to_gt() for all i915->ggtt accesses to help with the future
> refactoring.
On Thu, Dec 09, 2021 at 03:25:10PM +0200, Andi Shyti wrote:
> From: Michał Winiarski
>
> Use to_gt() helper consistently throughout the codebase.
> Pure mechanical s/i915->gt/to_gt(i915). No functional changes.
>
> Signed-off-by: Michał Winiarski
> Signed-off-by: Andi Shyti
Reviewed-by: Matt
== Series Details ==
Series: series starting with [1/2] drm/i915: Introduce new Tile 4 format
URL : https://patchwork.freedesktop.org/series/97778/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: series starting with [1/2] drm/i915: Introduce new Tile 4 format
URL : https://patchwork.freedesktop.org/series/97778/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
59d54448d9b9 drm/i915: Introduce new Tile 4 format
-:9:
On Thu, Dec 09, 2021 at 03:25:09PM +0200, Andi Shyti wrote:
> Use to_gt() helper consistently throughout the codebase.
> Pure mechanical s/i915->gt/to_gt(i915). No functional changes.
>
> Signed-off-by: Andi Shyti
> ---
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 6 --
> 1 file changed, 4
On 12/8/2021 20:03, Patchwork wrote:
Project List - Patchwork *Patch Details*
*Series:* Assorted fixes/tweaks to GuC support (rev5)
*URL:* https://patchwork.freedesktop.org/series/97514/
*State:*failure
*Details:*
On Thu, Dec 09, 2021 at 03:25:08PM +0200, Andi Shyti wrote:
> Use to_gt() helper consistently throughout the codebase.
> Pure mechanical s/i915->gt/to_gt(i915). No functional changes.
>
> Signed-off-by: Andi Shyti
> Cc: Michał Winiarski
Reviewed-by: Matt Roper
> ---
>
== Series Details ==
Series: Support bigger GuC RSA keys
URL : https://patchwork.freedesktop.org/series/97760/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10984 -> Patchwork_21797
Summary
---
**SUCCESS**
No
On Thu, Dec 09, 2021 at 03:25:07PM +0200, Andi Shyti wrote:
> From: Michał Winiarski
>
> Use to_gt() helper consistently throughout the codebase.
> Pure mechanical s/i915->gt/to_gt(i915). No functional changes.
>
> Signed-off-by: Michał Winiarski
> Signed-off-by: Andi Shyti
Reviewed-by: Matt
On Thu, Dec 09, 2021 at 03:25:06PM +0200, Andi Shyti wrote:
> From: Michał Winiarski
>
> Use to_gt() helper consistently throughout the codebase.
> Pure mechanical s/i915->gt/to_gt(i915). No functional changes.
>
> Signed-off-by: Michał Winiarski
> Signed-off-by: Andi Shyti
Reviewed-by: Matt
On Thu, Dec 09, 2021 at 03:25:05PM +0200, Andi Shyti wrote:
> From: Michał Winiarski
>
> Use to_gt() helper consistently throughout the codebase.
> Pure mechanical s/i915->gt/to_gt(i915). No functional changes.
>
> Signed-off-by: Michał Winiarski
> Signed-off-by: Andi Shyti
Reviewed-by: Matt
== Series Details ==
Series: Support bigger GuC RSA keys
URL : https://patchwork.freedesktop.org/series/97760/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
By default, GT (and GuC) run at RPn. Requesting for RP0
before firmware load can speed up DMA and HuC auth as well.
In addition to writing to 0xA008, we also need to enable
swreq in 0xA024 so that Punit will pay heed to our request.
SLPC will restore the frequency back to RPn after
Panel is 800x1280, but mounted on a laptop form factor, sideways.
Signed-off-by: Anisse Astier
Reviewed-by: Hans de Goede
---
drivers/gpu/drm/drm_panel_orientation_quirks.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/drm_panel_orientation_quirks.c
The ACPI OpRegion Mailbox #5 ASLE extension may contain an EDID to be
used for the embedded display. Add support for using it via by adding
the EDID to the list of available modes on the connector, and use it for
eDP when available.
If a panel's EDID is broken, there may be an override EDID set
This patch series is for making the GPD Win Max display usable with
Linux.
The GPD Win Max is a small laptop, and its eDP panel does not send an
EDID over DPCD; the EDID is instead available in the intel opregion, in
mailbox #5 [1]
The second patch is just to fix the orientation of the panel.
On 12/9/2021 11:57 AM, Matthew Brost wrote:
On Thu, Dec 09, 2021 at 11:26:09AM -0800, Daniele Ceraolo Spurio wrote:
On 12/9/2021 10:51 AM, Matthew Brost wrote:
A full GT can race with the last context put resulting in the context
forgot to mention earlier but you're missing "reset" here
On Thu, Dec 09, 2021 at 11:26:09AM -0800, Daniele Ceraolo Spurio wrote:
>
>
> On 12/9/2021 10:51 AM, Matthew Brost wrote:
> > A full GT can race with the last context put resulting in the context
> > ref count being zero but the destroyed bit not yet being set. Remove
> > GEM_BUG_ON in
On Wed, Dec 08, 2021 at 04:56:10PM -0800, Daniele Ceraolo Spurio wrote:
> Some of the newer HW will use bigger RSA keys to authenticate the GuC
> binary. On those platforms the HW will read the key from memory instead
> of the RSA registers, so we need to copy it in a dedicated vma, like we
> do
Ping. I see that a v4 has been sent out without these comments being addressed.
-Nanley
On Tue, Dec 7, 2021 at 6:51 PM Nanley Chery wrote:
>
> Hi Ramalingam,
>
> On Wed, Oct 27, 2021 at 5:22 PM Ramalingam C wrote:
> >
> > From: Matt Roper
> >
> > DG2 unifies render compression and media
On 12/9/2021 10:51 AM, Matthew Brost wrote:
A full GT can race with the last context put resulting in the context
ref count being zero but the destroyed bit not yet being set. Remove
GEM_BUG_ON in scrub_guc_desc_for_outstanding_g2h that asserts the
destroyed bit must be set in ref count is
On Thu, 09 Dec 2021, Ville Syrjälä wrote:
> On Thu, Dec 09, 2021 at 03:50:56PM +0200, Jani Nikula wrote:
>> Not needed.
>>
>> Signed-off-by: Jani Nikula
>> ---
>> drivers/gpu/drm/i915/gt/intel_reset.c | 1 -
>> 1 file changed, 1 deletion(-)
>>
>> diff --git
On 12/9/2021 10:48 AM, Matthew Brost wrote:
s/ce/cn/ when grabbing guc_state.lock before calling
clr_context_registered.
Fixes: 0f7976506de61 ("drm/i915/guc: Rework and simplify locking")
Signed-off-by: Matthew Brost
Cc:
Reviewed-by: Daniele Ceraolo Spurio
I'm assuming we didn't see
Hi Dave and Daniel,
Here goes drm-intel-fixes-2021-12-09:
A fix to a error pointer dereference in gem_execbuffer and
a fix for GT initialization when GuC/HuC are used on ICL.
Thanks,
Rodrigo.
The following changes since commit 0fcfb00b28c0b7884635dacf38e46d60bf3d4eb1:
Linux 5.16-rc4
On Wed, Dec 08, 2021 at 04:56:08PM -0800, Daniele Ceraolo Spurio wrote:
> The FAILURE state of uc_fw currently implies that the fw is loadable
> (i.e init completed), so we can't use it for init failures and instead
> need a dedicated error code.
>
> Note that this currently does not cause any
On Wed, Dec 08, 2021 at 04:56:09PM -0800, Daniele Ceraolo Spurio wrote:
> From: Michal Wajdeczko
>
> Future GuC/HuC firmwares might be signed with different key sizes.
> Don't assume that it must be always 2048 bits long.
>
> Signed-off-by: Michal Wajdeczko
> Cc: Daniele Ceraolo Spurio
You
A full GT can race with the last context put resulting in the context
ref count being zero but the destroyed bit not yet being set. Remove
GEM_BUG_ON in scrub_guc_desc_for_outstanding_g2h that asserts the
destroyed bit must be set in ref count is zero.
Signed-off-by: Matthew Brost
---
s/ce/cn/ when grabbing guc_state.lock before calling
clr_context_registered.
Fixes: 0f7976506de61 ("drm/i915/guc: Rework and simplify locking")
Signed-off-by: Matthew Brost
Cc:
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff
On Thu, 09 Dec 2021, Ville Syrjälä wrote:
> On Thu, Dec 09, 2021 at 06:51:23PM +0200, Jani Nikula wrote:
>> Hide the details better.
>>
>> Signed-off-by: Jani Nikula
>> ---
>> drivers/gpu/drm/i915/display/intel_cdclk.c | 18 ++
>> drivers/gpu/drm/i915/display/intel_cdclk.h | 13
From: Ville Syrjälä
Convert i915->fbc into an array in preparation for
multiple FBC instances, and loop through all instances
in all places where the caller does not know which
instance(s) (if any) are relevant. This is the case
for eg. frontbuffer tracking and FIFO underrun hadling.
From: Ville Syrjälä
Declare which FBC instances are present via a fbc_mask
in device info. For the moment there is just the one.
TODO: Need to figure out how to expose multiple FBC
instances in debugs. Just different file names, or move
the files under some subdirectory (per-crtc maybe), or
From: Ville Syrjälä
Parametrize ilk+ FBC register offsets based on the FBC instance.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fbc.c | 34 +---
drivers/gpu/drm/i915/display/intel_fbc.h | 6 +
drivers/gpu/drm/i915/i915_reg.h | 34
From: Ville Syrjälä
A bit more prep work towards multiple FBC instances.
One thing that is still up in the air is the debugfs
layout. Haven't relly figured out what the best approach
would be, and whatever is chosen does require igt changes
as well.
Ville Syrjälä (3):
drm/i915/fbc:
On Thu, Dec 09, 2021 at 06:51:21PM +0200, Jani Nikula wrote:
> Clean up the cdclk header dependencies.
>
> Jani Nikula (4):
> drm/i915/cdclk: move intel_atomic_check_cdclk() to intel_cdclk.c
> drm/i915/cdclk: un-inline intel_cdclk_state functions
> drm/i915/cdclk: hide struct
On Thu, Dec 09, 2021 at 06:51:25PM +0200, Jani Nikula wrote:
> intel_cdclk.h only needs i915_drv.h for struct intel_cdclk_config. Move
> the definition to intel_cdclk.h and turn the includes around to avoid
> including i915_drv.h from other headers.
>
> Signed-off-by: Jani Nikula
Reviewed-by:
On Thu, Dec 09, 2021 at 06:51:23PM +0200, Jani Nikula wrote:
> Hide the details better.
>
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 18 ++
> drivers/gpu/drm/i915/display/intel_cdclk.h | 13 -
> 2 files changed, 26
On Thu, Dec 09, 2021 at 06:51:24PM +0200, Jani Nikula wrote:
> The definition is not needed outside of intel_cdclk.c.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 8
> drivers/gpu/drm/i915/display/intel_cdclk.h | 8
On Thu, Dec 09, 2021 at 06:51:22PM +0200, Jani Nikula wrote:
> Rename to intel_cdclk_atomic_check() and make
> intel_cdclk_bw_calc_min_cdclk() static.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 55 +++-
>
On 08/12/2021 08:22, Thomas Hellström wrote:
When updating the error capture code and introducing vma snapshots,
we introduced code to hold the vma in memory while capturing it,
calling i915_active_acquire_if_busy(). Now that function isn't relevant
for perma-pinned vmas and caused important
On Thu, Dec 09, 2021 at 03:50:55PM +0200, Jani Nikula wrote:
> Remove some useless includes as well as ones that can be removed with
> trivial changes.
>
> Jani Nikula (7):
> drm/i915/reset: remove useless intel_display_types.h include
> drm/i915/active: remove useless i915_utils.h include
>
On Thu, Dec 09, 2021 at 03:50:56PM +0200, Jani Nikula wrote:
> Not needed.
>
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/gt/intel_reset.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
> b/drivers/gpu/drm/i915/gt/intel_reset.c
>
On 09/12/2021 14:13, Thomas Hellström wrote:
When we recently converted the capture code to use vma snapshots,
we forgot to free the struct i915_capture_list list items after use.
Fix that by bringing back a kfree.
Fixes: ff20afc4cee7 ("drm/i915: Update error capture code to avoid using the
On Wed, Dec 08, 2021 at 06:39:55PM +0200, Jani Nikula wrote:
On Wed, 08 Dec 2021, Lucas De Marchi wrote:
On Wed, Dec 08, 2021 at 01:05:17PM +0200, Jani Nikula wrote:
Add display/intel_display_trace.[ch] for defining display
tracepoints. The main goal is to reduce cross-includes between gem
Hi Jani,
thanks for looking at it.
> > - intel_gt_init_early(_priv->gt, dev_priv);
> > + __intel_gt_init_early(_priv->gt, dev_priv);
>
> Why double underscores here? It looks like it's supposed to be internal
> to intel_gt, not to be called by anyone else.
I forgot to write two lines in
On Fri, Dec 03, 2021 at 08:26:03PM +0530, ravitejax.goud.ta...@intel.com wrote:
From: Raviteja Goud Talla
Bspec page says "Reset: BUS", Accordingly moving w/a's:
Wa_1407352427,Wa_1406680159 to proper function icl_gt_workarounds_init()
Which will resolve guc enabling error
v2:
- Previous
On 12/9/2021 06:41, Robert Beckett wrote:
On 09/12/2021 00:24, John Harrison wrote:
On 12/8/2021 09:58, Robert Beckett wrote:
On 07/12/2021 23:15, John Harrison wrote:
On 12/7/2021 09:53, Adrian Larumbe wrote:
Beginning with DG2, all successive devices will require GuC FW to be
present and
On Thu, 09 Dec 2021, Andi Shyti wrote:
> From: Michał Winiarski
>
> We now support a per-gt uncore, yet we're not able to infer which GT
> we're operating upon. Let's store a backpointer for now.
>
> Signed-off-by: Michał Winiarski
> Signed-off-by: Matt Roper
> Reviewed-by: Andi Shyti
>
On Wed, Dec 08, 2021 at 06:16:10AM +0100, jim.cro...@gmail.com wrote:
> are you planning to dust this patchset off and resubmit it ?
>
> Ive been playing with it and learning ftrace (decade+ late),
> I found your boot-line example very helpful as 1st steps
> (still havent even tried the
Documents the Flat-CCS feature and kernel handling required along with
modifiers used.
Signed-off-by: Ramalingam C
cc: Simon Ser
cc: Pekka Paalanen
Cc: Jordan Justen
Cc: Kenneth Graunke
Cc: mesa-...@lists.freedesktop.org
Cc: Tony Ye
Cc: Slawomir Milczarek
---
Hide the details better.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 18 ++
drivers/gpu/drm/i915/display/intel_cdclk.h | 13 -
2 files changed, 26 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
From: Abdiel Janulgue
A portion of device memory is reserved for Flat CCS so usable
device memory will be reduced by size of Flat CCS. Size of
Flat CCS is specified in “XEHPSDV_FLAT_CCS_BASE_ADDR”.
So to get effective device memory we need to subtract
total device memory by Flat CCS memory size.
On Mon, 29 Nov 2021 at 13:58, Maarten Lankhorst
wrote:
>
> Add a flag PIN_VALIDATE, to indicate we don't need to pin and only
> protected by the object lock.
>
> This removes the need to unpin, which is done by just releasing the
> lock.
>
> eb_reserve is slightly reworked for readability, but
From: CQ Tang
Platforms of XeHP and beyond support 3D surface (buffer) compression and
various compression formats. This is accomplished by an additional
compression control state (CCS) stored for each surface.
Gen 12 devices(TGL family and DG1) stores compression states in a separate
region of
The definition is not needed outside of intel_cdclk.c.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 8
drivers/gpu/drm/i915/display/intel_cdclk.h | 8
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git
From: Mika Kahola
DG2 clear color render compression uses Tile4 layout. Therefore, we need
to define a new format modifier for uAPI to support clear color rendering.
Signed-off-by: Mika Kahola
cc: Anshuman Gupta
Signed-off-by: Juha-Pekka Heikkilä
Signed-off-by: Ramalingam C
---
From: Chris Wilson
As we setup the memory regions for the device, give each a quick test to
verify that we can read and write to the full iomem range. This ensures
that our physical addressing for the device's memory is correct, and
some reassurance that the memory is functional.
v2: wrapper
From: Matthew Auld
If this is LMEM then we get a 32 entry PT, with each PTE pointing to
some 64K block of memory, otherwise it's just the usual 512 entry PT.
This very much assumes the caller knows what they are doing.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
Cc: Ramalingam C
From: Matthew Auld
The basic idea is that each 2M block(page-table) has a color, depending
on if the page-table is occupied by LMEM objects(64K) or SMEM
objects(4K), where our goal is to prevent mixing 64K and 4K GTT pages in
the page-table, which is not supported by the HW.
Signed-off-by:
On 2021-12-08 at 19:46:09 +0530, Ramalingam C wrote:
> Preparational patches for 64k page support.
Thanks for the review. Merged these patches.
Ram.
>
> Matthew Auld (3):
> drm/i915/xehpsdv: set min page-size to 64K
> drm/i915/gtt/xehpsdv: move scratch page to system memory
> drm/i915:
From: Michał Winiarski
Use to_gt() helper consistently throughout the codebase.
Pure mechanical s/i915->gt/to_gt(i915). No functional changes.
Signed-off-by: Michał Winiarski
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gvt/gvt.c | 2 +-
drivers/gpu/drm/i915/gvt/scheduler.c | 2
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