== Series Details ==
Series: drm/i915: SAGV fixes (rev3)
URL : https://patchwork.freedesktop.org/series/100091/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11244 -> Patchwork_22327
Summary
---
**SUCCESS**
No
== Series Details ==
Series: drm/i915: Fix disabled crtc state clearing, again
URL : https://patchwork.freedesktop.org/series/100316/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11242_full -> Patchwork_22313_full
Summary
From: Ville Syrjälä
Extract the data rate calculation loop out from
intel_bw_atomic_check() to make it a bit less confusing.
v2: Deal with 'bool changed'
Reviewed-by: Stanislav Lisovskiy #v1
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_bw.c | 55
From: Ville Syrjälä
Declutter intel_bw_atomic_check() a bit by pulling
the max QGV mask calculation out.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_bw.c | 35 -
1 file changed, 22 insertions(+), 13 deletions(-)
diff --git
From: Ville Syrjälä
Add some debugs on what exactly we're doing to the QGV point mask
in the icl+ sagv pre/post plane update hooks. Currently we're just
guessing.
v2: s/u32/u16/ for consistency with the mask sizes (Stan)
Reviewed-by: Stanislav Lisovskiy
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
To further reduce the confusion between the pre-icl vs. icl+
SAGV codepaths let's do a full split.
Reviewed-by: Stanislav Lisovskiy
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 120
1 file changed, 77 insertions(+),
From: Ville Syrjälä
If the only thing that is changing is SAGV vs. no SAGV but
the number of active planes and the total data rates end up
unchanged we currently bail out of intel_bw_atomic_check()
early and forget to actually compute the new WGV point
mask and thus won't actually enable/disable
From: Ville Syrjälä
When changing between SAGV vs. no SAGV on tgl+ we have to
update the use_sagv_wm flag for all the crtcs or else
an active pipe not already in the state will end up using
the wrong watermarks. That is especially bad when we end up
with the tighter non-SAGV watermarks with SAGV
From: Ville Syrjälä
While pokingaround the watermarks/etc. I noticed our SAGV code
has a bunch of bugs. Let's try to fix it.
OK, v3 which sould avoid the extra debug spew from the bw code.
That should help make the stress tests pass in ci.
Ville Syrjälä (6):
drm/i915: Correctly populate
== Series Details ==
Series: series starting with [CI,1/3] drm/i915: Fix for PHY_MISC_TC1 offset
URL : https://patchwork.freedesktop.org/series/100373/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11244 -> Patchwork_22326
== Series Details ==
Series: series starting with [CI,1/3] drm/i915: Fix for PHY_MISC_TC1 offset
URL : https://patchwork.freedesktop.org/series/100373/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked
== Series Details ==
Series: series starting with [CI,1/3] drm/i915: Fix for PHY_MISC_TC1 offset
URL : https://patchwork.freedesktop.org/series/100373/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2bc5a2246dec drm/i915: Fix for PHY_MISC_TC1 offset
-:49: CHECK:MACRO_ARG_REUSE:
== Series Details ==
Series: drm/i915/dp: remove accidental static on what should be a local variable
URL : https://patchwork.freedesktop.org/series/100310/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11241_full -> Patchwork_22312_full
== Series Details ==
Series: Prep work for next GuC release (rev2)
URL : https://patchwork.freedesktop.org/series/99805/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11244 -> Patchwork_22325
Summary
---
**SUCCESS**
On Tue, Feb 01, 2022 at 04:11:22PM +0530, Ramalingam C wrote:
Details of the 64k pagesize support added as part of DG2 enabling and its
implicit impact on the uAPI.
v2: improvised the Flat-CCS documentation [Danvet & CQ]
v3: made only for 64k pagesize support
Signed-off-by: Ramalingam C
cc:
== Series Details ==
Series: Prep work for next GuC release (rev2)
URL : https://patchwork.freedesktop.org/series/99805/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: series starting with [CI,1/4] drm/i915/dsi: disassociate VBT video
transfer mode from register values
URL : https://patchwork.freedesktop.org/series/100368/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11244 -> Patchwork_22324
== Series Details ==
Series: drm/mm: Add an iterator to optimally walk over holes suitable for an
allocation (rev2)
URL : https://patchwork.freedesktop.org/series/100136/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11241_full -> Patchwork_22310_full
Robert Beckett writes:
> From: Matthew Auld
>
> On discrete platforms like DG2, we need to support a minimum page size
> of 64K when dealing with device local-memory. This is quite tricky for
> various reasons, so try to document the new implicit uapi for this.
>
> v3: fix typos and less
== Series Details ==
Series: series starting with [CI,1/4] drm/i915/dsi: disassociate VBT video
transfer mode from register values
URL : https://patchwork.freedesktop.org/series/100368/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used,
== Series Details ==
Series: series starting with [CI,1/4] drm/i915/dsi: disassociate VBT video
transfer mode from register values
URL : https://patchwork.freedesktop.org/series/100368/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0eacdf7065b7 drm/i915/dsi: disassociate VBT
== Series Details ==
Series: drm/i915/guc: Fix flag query helper function to not modify state
URL : https://patchwork.freedesktop.org/series/100364/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11244 -> Patchwork_22323
On Thu, Feb 17, 2022 at 08:03:41PM -, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: SAGV fixes (rev2)
> URL : https://patchwork.freedesktop.org/series/100091/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_11239_full -> Patchwork_22302_full
>
== Series Details ==
Series: drm/i915: Plane/wm cleanups (rev3)
URL : https://patchwork.freedesktop.org/series/100020/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11241_full -> Patchwork_22307_full
Summary
---
== Series Details ==
Series: Move #define wbvind_on_all_cpus (rev2)
URL : https://patchwork.freedesktop.org/series/1/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11244 -> Patchwork_22322
Summary
---
Hi Tvrtko,
>
> On 17/02/2022 07:50, Vivek Kasireddy wrote:
> > While looking for next holes suitable for an allocation, although,
> > it is highly unlikely, make sure that the DECLARE_NEXT_HOLE_ADDR
> > macro is using a valid node before it extracts the rb_node from it.
>
> Was the need for
== Series Details ==
Series: Move #define wbvind_on_all_cpus (rev2)
URL : https://patchwork.freedesktop.org/series/1/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Move #define wbvind_on_all_cpus (rev2)
URL : https://patchwork.freedesktop.org/series/1/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0ef1e9cb0b7b drm_cache: Add logic for wbvind_on_all_cpus
-:34: WARNING:INCLUDE_LINUX: Use #include instead
== Series Details ==
Series: drm/i915/guc/slpc: Use wrapper for reading RP_STATE_CAP (rev2)
URL : https://patchwork.freedesktop.org/series/100217/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11244 -> Patchwork_22321
== Series Details ==
Series: drm/i915/dg2: 5th Display output (rev3)
URL : https://patchwork.freedesktop.org/series/100151/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11244 -> Patchwork_22320
Summary
---
== Series Details ==
Series: drm/i915/dg2: 5th Display output (rev3)
URL : https://patchwork.freedesktop.org/series/100151/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915/dg2: 5th Display output (rev3)
URL : https://patchwork.freedesktop.org/series/100151/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
8c0d7cd7a8d7 drm/i915/dg2: Enable 5th port
25ac2dc4165f drm/i915/dg2: Drop 38.4 MHz MPLLB tables
== Series Details ==
Series: drm/i915: Kill the fake lmem support (rev2)
URL : https://patchwork.freedesktop.org/series/100276/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11244 -> Patchwork_22319
Summary
---
== Series Details ==
Series: drm/i915: Kill the fake lmem support (rev2)
URL : https://patchwork.freedesktop.org/series/100276/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
From: Matt Roper
Our early understanding of DG2 was incorrect; since the 5th display
isn't actually a Type-C output, 38.4 MHz input clocks are never used on
this platform and we can drop the corresponding MPLLB tables.
Cc: Anusha Srivatsa
Cc: José Roberto de Souza
Signed-off-by: Matt Roper
From: Matt Roper
DG2 supports a 5th display output which the hardware refers to as "TC1,"
even though it isn't a Type-C output. This behaves similarly to the TC1
on past platforms with just a couple minor differences:
* DG2's TC1 bit in SDEISR is at bit 25 rather than 24 as it is on
From: Jouni Högander
Currently ICL_PHY_MISC macro is returning offset 0x64C10 for PHY_E.
The PORT_TC1 port is not yet enabled properly in the driver, but
intel_phy_snps.c is relying on intel_phy_is_snps() to filter out
unavailable phys. That function was already considering the last phy as
== Series Details ==
Series: Add driver for GSC controller (rev9)
URL : https://patchwork.freedesktop.org/series/98066/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11243 -> Patchwork_22318
Summary
---
**SUCCESS**
== Series Details ==
Series: Add driver for GSC controller (rev9)
URL : https://patchwork.freedesktop.org/series/98066/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Add driver for GSC controller (rev9)
URL : https://patchwork.freedesktop.org/series/98066/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a7e6a826a5df drm/i915/gsc: add gsc as a mei auxiliary device
-:63: WARNING:FILE_PATH_CHANGES: added, moved or
== Series Details ==
Series: drm/i915: Disconnect PHYs left connected by BIOS on disabled ports
URL : https://patchwork.freedesktop.org/series/100336/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11243 -> Patchwork_22317
On Mon, Feb 07, 2022 at 03:07:43PM +0530, Ramalingam C wrote:
When we are swapping out the local memory obj on flat-ccs capable platform,
we need to capture the ccs data too along with main meory and we need to
restore it when we are swapping in the content.
Extracting and restoring the CCS
On Fri, Feb 11, 2022 at 06:57:43AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/dg2: add Wa_14014947963 (rev2)
> URL : https://patchwork.freedesktop.org/series/9/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_11215_full ->
On Thu, Feb 10, 2022 at 09:23:33PM -0800, clinton.a.tay...@intel.com wrote:
> From: Clint Taylor
>
> BSPEC: 46123
> v2: Address review feedback [MattR]
> v3: move register definition to gt_regs [MattR]
> Cc: Matt Roper
> Signed-off-by: Clint Taylor
Reviewed-by: Matt Roper
although see below
Hi Andi,
I love your patch! Yet something to improve:
[auto build test ERROR on drm-tip/drm-tip]
[cannot apply to drm-intel/for-linux-next drm-exynos/exynos-drm-next
drm/drm-next tegra-drm/drm/tegra/for-next airlied/drm-next v5.17-rc4
next-20220217]
[If your patch is applied to the wrong git
From: John Harrison
The LRC descriptor pool is going away. So, stop naming context ids as
descriptor pool indecies.
While at it, add a bunch of missing line feeds to some error messages.
Signed-off-by: John Harrison
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 56 +--
From: John Harrison
The LRC descriptor pool is going away. So, stop using it as a check
for whether submission has been initialised or not.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 2 ++
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 8 +---
From: John Harrison
Some G2H handlers were reading the context id field from the payload
before checking the payload met the minimum length required.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
From: John Harrison
The LRC descriptor pool is going away. So, stop using it as the limit
for how many context ids are available.
While at it, also update a kzalloc(sizeof()*count) to be a
kcalloc(count,size).
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/intel_context.c
From: John Harrison
The CTB registration process changed significantly a while back using
a single KLV based H2G. So drop the original and now obsolete H2G
definitions.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 2 --
1 file changed, 2 deletions(-)
From: John Harrison
The LRC descriptor pool is going away. So, stop using it as a check for
context registration, use the GuC id instead (being the thing that
actually gets registered with the GuC).
Also, rename the set/clear/query helper functions for context id
mappings to better reflect
From: John Harrison
The LRC descriptor pool is going away. Further, the function that was
populating it was also doing a bunch of logic about the context
registration sequence. So, split that code apart into separate state
setup and try to register functions. Note that some of those 'try to
From: John Harrison
The next GuC firmware release includes some significant backwards
breaking API changes. One such is that there is no longer an LRC
descriptor pool. A bunch of prep work for that change can be done in
advance - the descriptor pool was being used for things it shouldn't
really
From: John Harrison
The LRC descriptor was being initialised early on in the context
registration sequence. It could then be determined that the actual
registration needs to be delayed and the descriptor would be wiped
out. This is inefficient, so move the setup to later in the process
after the
== Series Details ==
Series: drm/i915: Disconnect PHYs left connected by BIOS on disabled ports
URL : https://patchwork.freedesktop.org/series/100336/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
921ff943d11a drm/i915: Disconnect PHYs left connected by BIOS on disabled ports
== Series Details ==
Series: Introduce multitile support
URL : https://patchwork.freedesktop.org/series/100331/
State : warning
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready
== Series Details ==
Series: Introduce multitile support
URL : https://patchwork.freedesktop.org/series/100331/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11243 -> Patchwork_22316
Summary
---
**FAILURE**
== Series Details ==
Series: drm/i915/dg2: Print PHY name properly on calibration error (rev3)
URL : https://patchwork.freedesktop.org/series/100191/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11239_full -> Patchwork_22305_full
== Series Details ==
Series: Introduce multitile support
URL : https://patchwork.freedesktop.org/series/100331/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: Introduce multitile support
URL : https://patchwork.freedesktop.org/series/100331/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
84ebedcd8baa drm/i915: Rename INTEL_REGION_LMEM with INTEL_REGION_LMEM_0
3122cf9d817d drm/i915: Prepare for multiple
The ICL DSI registers have fairly isolated usage. Split the register
macros to a separate file.
Cc: Matt Roper
Reviewed-by: Matt Roper
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/icl_dsi.c | 1 +
drivers/gpu/drm/i915/display/icl_dsi_regs.h | 342
The VLV (including CHV, BXT, and GLK) DSI registers have fairly isolated
usage. Split the register macros to separated files.
Cc: Matt Roper
Reviewed-by: Matt Roper
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 3 +-
Having a separate definition will be useful for splitting VLV and ICL
register files.
Cc: Matt Roper
Reviewed-by: Matt Roper
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/icl_dsi.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h| 1 +
2 files changed, 2 insertions(+), 1
The VBT DSI video transfer mode field values have been defined in terms
of the VLV MIPI_VIDEO_MODE_FORMAT register. The ICL DSI code maps that
to ICL DSI_TRANS_FUNC_CONF() register. The values are the same, though
the shift is different.
Make a clean break and disassociate the values from each
== Series Details ==
Series: drm/i915: use ref_tracker library for tracking wakerefs
URL : https://patchwork.freedesktop.org/series/100327/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11242 -> Patchwork_22315
Summary
Hi Jani,
This addresses the review comments, could you please take a look at thsi patch?
Manasi
On Tue, Feb 15, 2022 at 12:26:01PM -0800, Manasi Navare wrote:
> With some VRR panels, user can turn VRR ON/OFF on the fly from the panel
> settings.
> When VRR is turned OFF ,sends a long HPD to
On Thu, Feb 17, 2022 at 10:46:44AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/dg2: Move misplaced 'ctx' & 'gt' wa's to engine wa list
> URL : https://patchwork.freedesktop.org/series/100212/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from
On Tue, Feb 15, 2022 at 03:55:31PM -0800, Matt Roper wrote:
> From: Srinivasan Shanmugam
>
> Registers that belong to the shared render/compute reset domain need to
> be placed on an engine workaround list to ensure that they are properly
> re-applied whenever any RCS or CCS engine is reset,
== Series Details ==
Series: drm/i915: use ref_tracker library for tracking wakerefs
URL : https://patchwork.freedesktop.org/series/100327/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
== Series Details ==
Series: drm/i915: use ref_tracker library for tracking wakerefs
URL : https://patchwork.freedesktop.org/series/100327/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
3401795c5e59 lib/ref_tracker: add unlocked leak print helper
-:6:
From: John Harrison
A flag query helper was actually writing to the flags word rather than
just reading. Fix that. Also update the function's comment as it was
out of date.
NB: No need for a 'Fixes' tag. The test was only ever used inside a
BUG_ON during context registration. Rather than
== Series Details ==
Series: drm/i915/gt: use get_reset_domain() helper
URL : https://patchwork.freedesktop.org/series/100326/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11242 -> Patchwork_22314
Summary
---
On Fri, Feb 18, 2022 at 12:12:21AM +0530, Ramalingam C wrote:
From: Matt Roper
DG2 supports a 5th display output which the hardware refers to as "TC1,"
even though it isn't a Type-C output. This behaves similarly to the TC1
on past platforms with just a couple minor differences:
* DG2's TC1
== Series Details ==
Series: drm/i915: Fix disabled crtc state clearing, again
URL : https://patchwork.freedesktop.org/series/100316/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11242 -> Patchwork_22313
Summary
---
On Mon, Feb 14, 2022 at 07:36:44PM +0200, Jani Nikula wrote:
> Always use forward declarations instead of includes in headers if
> possible.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 2 +-
> 1 file changed, 1 insertion(+), 1
Hi Andi,
I love your patch! Yet something to improve:
[auto build test ERROR on drm-tip/drm-tip]
[cannot apply to drm-intel/for-linux-next drm-exynos/exynos-drm-next
drm/drm-next tegra-drm/drm/tegra/for-next airlied/drm-next v5.17-rc4
next-20220217]
[If your patch is applied to the wrong git
On Wed, Feb 16, 2022 at 09:36:02AM +, Hogander, Jouni wrote:
On Wed, 2022-02-16 at 10:50 +0200, Ville Syrjälä wrote:
On Tue, Feb 15, 2022 at 11:21:54AM +0530, Ramalingam C wrote:
> From: Jouni Högander
>
> Currently ICL_PHY_MISC macro is returning offset 0x64C10 for PHY_E
> port. Correct
== Series Details ==
Series: drm/i915/guc/slpc: Correct the param count for unset param
URL : https://patchwork.freedesktop.org/series/100260/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11239_full -> Patchwork_22303_full
drm_cache.h now handles calls to wbinvd_on_all_cpus.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gem/i915_gem_pm.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
index
Add drm_cache.h to additionals files that calls wbinvd_on_all_cpus and
remove un-needed header files.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 2 +-
drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff
Add logic for wbvind_on_all_cpus for non-x86 platforms.
v2(Michael Cheng): Change logic to if platform is not x86, then
we add pr_warn for calling wbvind_on_all_cpus.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/drm_cache.c | 2 --
include/drm/drm_cache.h | 6 ++
This series moves the logic for wbvind_on_all_cpus to drm_cache. The logic
changes a little here, if platform is not x86 then we throw out a warning
for when wbvind_on_all_cpus is being called.
v2(Michael Cheng): Move and redo logic for wbvind_on_all_cpus. Also
add
The 2022 X.Org Foundation elections are rapidly approaching. We will be
forwarding instructions on the nomination process to membership in the
near future.
Please note that only current members can vote in the upcoming election,
and that the deadline for new memberships or renewals to vote in the
== Series Details ==
Series: drm/i915: SAGV fixes (rev2)
URL : https://patchwork.freedesktop.org/series/100091/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11239_full -> Patchwork_22302_full
Summary
---
== Series Details ==
Series: drm/i915/dp: remove accidental static on what should be a local variable
URL : https://patchwork.freedesktop.org/series/100310/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11241 -> Patchwork_22312
Hi Andi,
I love your patch! Yet something to improve:
[auto build test ERROR on drm-tip/drm-tip]
[cannot apply to drm-intel/for-linux-next drm-exynos/exynos-drm-next
drm/drm-next tegra-drm/drm/tegra/for-next airlied/drm-next v5.17-rc4
next-20220217]
[If your patch is applied to the wrong git
On Tue, Feb 15, 2022 at 11:21:54AM +0530, Ramalingam C wrote:
From: Jouni Högander
Currently ICL_PHY_MISC macro is returning offset 0x64C10 for PHY_E
port. Correct offset is 0x64C14.
Fix this by handling PHY_E port seprately.
order of the patch here is wrong. This patch should come before
On Tue, Feb 15, 2022 at 11:21:53AM +0530, Ramalingam C wrote:
From: Matt Roper
Our early understanding of DG2 was incorrect; since the 5th display
isn't actually a Type-C output, 38.4 MHz input clocks are never used on
this platform and we can drop the corresponding MPLLB tables.
Cc: Anusha
On Sun, Feb 13, 2022 at 11:47:00AM -0800, Teres Alexis, Alan Previn wrote:
Thanks Umesh for reviewing the patch.
Am fixing all the rest but a couple of comments.
Responses to the latter and other questions below:
...alan
> +enum intel_guc_state_capture_event_status {
> +
This will ensure correct values for Gen12+ platforms.
v2: Rebase
Cc: Matt Roper
Reviewed-by: Matt Roper
Signed-off-by: Vinay Belgaumkar
---
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git
== Series Details ==
Series: drm/i915: Fix cursor coordinates on bigjoiner slave (rev2)
URL : https://patchwork.freedesktop.org/series/100154/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK
On Tue, Feb 15, 2022 at 11:01:15AM +0530, Ramalingam C wrote:
i915_perf is not enabled for dg2 yet, hence skip the feature
initialization.
Signed-off-by: Ramalingam C
cc: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_perf.c | 4
1 file changed, 4 insertions(+)
diff --git
== Series Details ==
Series: drm/mm: Add an iterator to optimally walk over holes suitable for an
allocation (rev2)
URL : https://patchwork.freedesktop.org/series/100136/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11241 -> Patchwork_22310
On Wed, Feb 16, 2022 at 10:15:04AM -0800, Vinay Belgaumkar wrote:
SLPC unset param H2G only needs one parameter - the id of the
param.
Fixes: 025cb07bebfa ("drm/i915/guc/slpc: Cache platform frequency limits")
Suggested-by: Umesh Nerlige Ramappa
Signed-off-by: Vinay Belgaumkar
---
== Series Details ==
Series: drm/mm: Add an iterator to optimally walk over holes suitable for an
allocation (rev2)
URL : https://patchwork.freedesktop.org/series/100136/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't
== Series Details ==
Series: drm/mm: Add an iterator to optimally walk over holes suitable for an
allocation (rev2)
URL : https://patchwork.freedesktop.org/series/100136/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
19844014c61e drm/mm: Ensure that the entry is not NULL
== Series Details ==
Series: use dynamic-debug under drm.debug api
URL : https://patchwork.freedesktop.org/series/100289/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11241 -> Patchwork_22308
Summary
---
From: Matt Roper
DG2 supports a 5th display output which the hardware refers to as "TC1,"
even though it isn't a Type-C output. This behaves similarly to the TC1
on past platforms with just a couple minor differences:
* DG2's TC1 bit in SDEISR is at bit 25 rather than 24 as it is on
== Series Details ==
Series: series starting with [1/4] drm/i915/dsi: disassociate VBT video
transfer mode from register values (rev2)
URL : https://patchwork.freedesktop.org/series/100249/
State : failure
== Summary ==
Applying: drm/i915/dsi: disassociate VBT video transfer mode from
On Wed, Feb 16, 2022 at 07:42:50PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Extract the data rate calculation loop out from
> intel_bw_atomic_check() to make it a bit less confusing.
>
> Cc: Stanislav Lisovskiy
> Signed-off-by: Ville Syrjälä
Reviewed-by: Stanislav Lisovskiy
>
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