Re: [PATCH v2 03/21] drm/i915/dp: Move link train fallback to intel_dp_link_training.c

Looks good to me, Reviewed-by: Manasi Navare Manasi On Wed, May 22, 2024 at 11:23 AM Ville Syrjälä wrote: > > On Mon, May 20, 2024 at 09:58:01PM +0300, Imre Deak wrote: > > Move the functions used to reduce the link parameters during link > > training to intel_

Re: [RFC] drm/i915/dp: Log message when limiting SST link rate MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit

Thanks Charlton for the patch. I think in general it is a good idea to log this when the max rate is dropped to HBR3 for SST case. Please find my comments below, On Thu, Feb 29, 2024 at 11:49 PM Charlton Lin wrote: > > Driver currently limits link rate up to HBR3 in SST mode. Log a > message

Re: [PATCH 05/11] drm/i915/dp_mst: Account with the DSC DPT bpp limit on MTL

Hi Imre, While we are adding these checks here for DSC for MST, I see that in intel_dp_mst_mode_valid_ctx() we still check against DISPLAY_VER() > 10 for checking for DSC where as in all other places we rely on runtime has_dsc and check for HAS_DSC(), can we fix that and use HAS_DSC() in this

Re: [PATCH 07/11] drm/dp: Add drm_dp_uhbr_channel_coding_supported()

Reviewed-by: Manasi Navare Manasi On Tue, Mar 26, 2024 at 5:54 AM Nautiyal, Ankit K wrote: > > > On 3/21/2024 1:41 AM, Imre Deak wrote: > > Factor out a function to check for UHBR channel coding support used by a > > follow-up patch in the patchset. > > > > Cc

Re: [PATCH 06/11] drm/i915/dp_mst: Sanitize calculating the DSC DPT bpp limit

Hi Imre, Would this impact/fix DSC functionality on ADL based platforms as well or will this change only impact platforms that support UHBR? Manasi On Tue, Mar 26, 2024 at 5:55 AM Nautiyal, Ankit K wrote: > > > On 3/21/2024 1:41 AM, Imre Deak wrote: > > Instead of checking each compressed bpp

Re: [PATCH 02/11] drm/i915/dp_mst: Fix symbol clock when calculating the DSC DPT bpp limit

On Tue, Mar 26, 2024 at 1:04 PM Manasi Navare wrote: > > On Tue, Mar 26, 2024 at 3:01 AM Nautiyal, Ankit K > wrote: > > > > > > On 3/21/2024 1:41 AM, Imre Deak wrote: > > > The expected link symbol clock unit when calculating the DSC DPT bpp &

Re: [PATCH 02/11] drm/i915/dp_mst: Fix symbol clock when calculating the DSC DPT bpp limit

On Tue, Mar 26, 2024 at 3:01 AM Nautiyal, Ankit K wrote: > > > On 3/21/2024 1:41 AM, Imre Deak wrote: > > The expected link symbol clock unit when calculating the DSC DPT bpp > > limit is kSymbols/sec, aligning with the dotclock's kPixels/sec unit > > based on the crtc clock. As opposed to this

Re: [PATCH 01/11] drm/i915/dp: Fix DSC line buffer depth programming

change makes sense, just want to confirm if this applies to all platforms or any particular? With that clarification: Reviewed-by: Manasi Navare Regards Manasi On Tue, Mar 26, 2024 at 3:01 AM Nautiyal, Ankit K wrote: > > > On 3/21/2024 1:41 AM, Imre Deak wrote: > > Fix the calcula

Re: [PATCH 5/6] drm/i915: Handle joined pipes inside hsw_crtc_enable()

The bigjoiner master handling in modset_enables/disables looks good. Reviewed-by: Manasi Navare Manasi On Mon, Mar 25, 2024 at 12:20 AM Srinivas, Vidya wrote: > > Thank you Stan. Rev 14 works. > Tested-by: Vidya Srinivas > > > -Original Message- > > Fr

Re: [PATCH 1/6] Add a small helper to compute the set of pipes that the current crtc is using.

Looks good to me Reviewed-by: Manasi Navare Manasi On Fri, Mar 8, 2024 at 5:11 AM Stanislav Lisovskiy wrote: > > And we have at least one trivial place in > intel_ddi_update_active_dpll() where we can use it > immediately, so let's do that. > > v2: - Fixed conflicts, pa

Re: [PATCH 6/6] drm/i915: Allow bigjoiner for MST

mismatch WARN for mst_master_transcoder > Credits-to: Manasi Navare > > Signed-off-by: Vidya Srinivas > Reviewed-by: Manasi Navare > --- > drivers/gpu/drm/i915/display/intel_ddi.c| 6 -- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 17 + > 2

Re: [PATCH 3/6] drm/i915: Utilize intel_crtc_joined_pipe_mask() more

On Fri, Mar 8, 2024 at 5:11 AM Stanislav Lisovskiy wrote: > > Unify the master vs. slave handling in > intel_ddi_post_disable_hdmi_or_sst() by looping over all the > pipes in one go. How will we handle looping through all joined pipes for MST case, does this need to be accounted for in the last

Re: [PATCH 2/6] drm/i915: Extract intel_ddi_post_disable_hdmi_or_sst()

Thanks Stan for the cleanup around post disable non MST case, one comment below On Fri, Mar 8, 2024 at 5:11 AM Stanislav Lisovskiy wrote: > > Extract the "not-MST" stuff from intel_ddi_post_disable() so that > the whole thing isn't so cluttered. > > The bigjoiner slave handling was outside of

Re: [PATCH 1/1] drm/i915: Allow bigjoiner for MST

Thanks Vidya for the v3, this LGTM, Reviewed-by: Manasi Navare Manasi On Wed, Mar 6, 2024 at 9:31 PM Vidya Srinivas wrote: > > We need bigjoiner support with MST functionality > for MST monitor resolutions > 5K to work. > Adding support for the same. > > v2: Addressed

Re: [PATCH] drm/i915: Allow for Vsync_start and Vsync_end to change in LRR

Hi Ville, Could you take a peek at this patch, as per our offline discussions, Even if VRR does not look at the Vsync start and Vsync end, we need to write to those registers to keep the state checker happy. Regards Manasi On Mon, Feb 26, 2024 at 3:53 PM Manasi Navare wrote: > > Since LR

Re: [PATCH 1/1] drm/i915: Allow bigjoiner for MST

With v2, this looks good to me, Acked-by: Manasi Navare wrote: > > We need bigjoiner support with MST functionality > for MST monitor resolutions > 5K to work. > Adding support for the same. > > v2: Addressed review comments from Jani. > Revert rejection of MST

Re: [PATCH 2/2] drm/i915: Allow bigjoiner for MST

I think now Patch 1/1 of this series takes care of squashing the revert with enabling bigjoiner for MST, so this patch is redundant. Manasi On Tue, Feb 27, 2024 at 10:37 AM Vidya Srinivas wrote: > > We need bigjoiner support with MST functionality > for MST monitor resolutions > 5K to work. >

Re: [PATCH 3/3] drm/i915: Fix bigjoiner case for DP2.0

Thanks Jani for your review. Thanks @Lisovskiy, Stanislav and @vidya.srini...@intel.com for taking this patch forward. @Jani Nikula , @Ville Syrjälä : MST bigjoiner as a feature needs to be enabled upstream and this patch enables that feature. If you agree that bigjoiner refactoring patches 1

[PATCH] drm/i915: Allow for Vsync_start and Vsync_end to change in LRR

. In case of VRR capable panel, it technically ignores the VSYNC because we set Ignore_MSA bit for sink but reprogram the TRANS_VSYNC to keep the state checker happy in case of LRR. Cc: Ville Syrjälä Cc: Sean Paul Signed-off-by: Manasi Navare --- drivers/gpu/drm/i915/display/intel_display.c | 11

Re: [PATCH 3/3] drm/i915: Fix bigjoiner case for DP2.0

Thanks Stan and Vidya for this patch. ACK for the bigjoiner pipes calc and plane max size validation changes. @Ville Syrjälä : Do you see any gaps now with MST bigjoiner enabling in crtc_enable hooks () ? Or just these changes would suffice? Regards Manasi On Wed, Feb 21, 2024 at 11:20 AM

[PATCH v3] drm/i915/dsc: Fix the macro that calculates DSCC_/DSCA_ PPS reg address

/issues/10172 Fixes: bd077259d0a9 ("drm/i915/vdsc: Add function to read any PPS register") Cc: Suraj Kandpal Cc: Ankit Nautiyal Cc: Animesh Manna Cc: Jani Nikula Cc: Sean Paul Cc: Drew Davenport Signed-off-by: Manasi Navare --- drivers/gpu/drm/i915/display/intel_vdsc_regs.h | 4

Re: [Intel-gfx] [PATCH] drm/i915: Fix bigjoiner case for DP2.0

please elaborate on this and if it is not being correctly reflected as ACTIVE, that would be a kernel bug and needs to be fixed as part of this series. Regards Manasi On Tue, Jan 16, 2024 at 5:20 PM Manasi Navare wrote: > > Hi Stan, Ville, > > After Stan's refactor series for bigj

Re: [PATCH v2] drm/i915/dsc: Fix the macro that calculates DSCC_/DSCA_ PPS reg address

Hi Jani, Yea I think I made that change after checkpatch but didnt do commit --amend, let me address that and send the patch for review. Regards Manasi On Mon, Feb 5, 2024 at 4:03 AM Jani Nikula wrote: > > On Fri, 02 Feb 2024, Manasi Navare wrote: > > Commit bd077259d0a9 ("d

[PATCH v2] drm/i915/dsc: Fix the macro that calculates DSCC_/DSCA_ PPS reg address

d function to read any PPS register") Cc: Suraj Kandpal Cc: Ankit Nautiyal Cc: Animesh Manna Cc: Jani Nikula Cc: Sean Paul Cc: Drew Davenport Signed-off-by: Manasi Navare --- drivers/gpu/drm/i915/display/intel_vdsc_regs.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff

Re: [PATCH] drm/i915/display/vdsc: Fix the macro that calculates DSCC_/DSCA_ PPS reg address

Thanks Jani, that makes sense and thanks for adding them in your suggestion. I have made the necessary changes addressing all your review comments and will send out a V2 for the patch. Regards Manasi On Thu, Feb 1, 2024 at 3:34 PM Jani Nikula wrote: > > On Thu, 01 Feb 2024, Manasi

Re: [PATCH] drm/i915/display/vdsc: Fix the macro that calculates DSCC_/DSCA_ PPS reg address

Thanks a lot Jani for your feedback and review. Please find my comments below inline, On Thu, Feb 1, 2024 at 1:15 AM Jani Nikula wrote: > > > Please use "drm/i915/dsc: " as the subject prefix. Okay I will change this > > On Wed, 31 Jan 2024, Manasi Navare wrote: >

[PATCH] drm/i915/display/vdsc: Fix the macro that calculates DSCC_/DSCA_ PPS reg address

to read any PPS register") Cc: Suraj Kandpal Cc: Ankit Nautiyal Cc: Animesh Manna Cc: Jani Nikula Cc: Sean Paul Cc: Drew Davenport Signed-off-by: Manasi Navare --- drivers/gpu/drm/i915/display/intel_vdsc_regs.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/dr

Re: [Intel-gfx] [PATCH] drm/i915: Fix bigjoiner case for DP2.0

Hi Stan, Ville, After Stan's refactor series for bigjoiner, along with Vidya's patch that assigns master/slave for MST as well, do you anticipate more MST specific bigjoiner modeset sequence changes to properly call crtc enable sequence for MST master slave? Stan, when you send the next revision

Re: [PATCH 1/3] drm/i915: Add bigjoiner force enable option to debugfs

Thanks Stan for the patch. I agree that since by forcing big joiner enable we are simulating a higher mode/pixel clock on a connector, this should be a per connector debugfs except for edp that can be exposed. Manasi On Mon, Jan 15, 2024 at 12:57 AM Lisovskiy, Stanislav wrote: > > On Fri, Jan

Re: [Intel-gfx] [PATCH v2 12/12] drm/i915: Implement transcoder LRR for TGL+

On Wed, Sep 20, 2023 at 12:40 PM Ville Syrjälä wrote: > > On Wed, Sep 20, 2023 at 11:47:05AM -0700, Manasi Navare wrote: > > Hi Ville, > > > > Quick question here on the use case and the trigger for the LRR case > > which is within VRR range. > > Could this

Re: [Intel-gfx] [PATCH 00/12] drm/i915: VRR, LRR, and M/N stuff

yrjälä > > Attempt to make VRR, LRR, and M/N updates coexist nicely, > allowing fastsets whenever feasible. > > Lightly smoke tested on my adl. > > Cc: Manasi Navare > > Ville Syrjälä (12): > drm/i915: Move psr unlock out from the pipe update critical section > dr

Re: [Intel-gfx] [PATCH v2 12/12] drm/i915: Implement transcoder LRR for TGL+

that would make update_lrr = true within VRR and hand adjust the vtotal to that exact value? I am looking at adding this virtual mode to DRM soon, wondering if this would be how the kernel would actual set the timings for it. Regards Manasi On Mon, Sep 18, 2023 at 4:16 PM Manasi Navare wrote

Re: [Intel-gfx] [PATCH v2 12/12] drm/i915: Implement transcoder LRR for TGL+

Thanks Ville for the respin, the changes look good now. Reviewed-by: Manasi Navare Manasi On Fri, Sep 15, 2023 at 3:38 AM Ville Syrjala wrote: > > From: Ville Syrjälä > > Implement low refresh rate (LRR) where we change the vblank > length by hand as requested, but otherwise

Re: [Intel-gfx] [PATCH 12/12] drm/i915: Implement transcoder LRR for TGL+

Adjust update_lrr flag behaviour > Make sure timings stay within VRR range > > TODO: Hook LRR into the automatic DRRS downclocking stuff? > > Cc: Manasi Navare > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/display/intel_atomic.c | 1 + >

Re: [Intel-gfx] [PATCH 09/12] drm/i915: Disable VRR during seamless M/N changes

On Thu, Sep 7, 2023 at 10:54 PM Ville Syrjälä wrote: > > On Thu, Sep 07, 2023 at 11:49:10AM -0700, Manasi Navare wrote: > > Hi Ville, > > > > Since we are always disabling when update_m_n, that means if in gaming > > mode if VRR enable is requested by users

Re: [Intel-gfx] [PATCH 11/12] drm/i915: Assert that VRR is off during vblank evasion if necessary

Reviewed-by: Manasi Navare Manasi On Fri, Sep 1, 2023 at 6:05 AM Ville Syrjala wrote: > > From: Ville Syrjälä > > Whenever we change the actual transcoder timings (clock via > seamless M/N, full modeset, (or soon) vtotal via LRR) we > want the timing generator to be

Re: [Intel-gfx] [PATCH 09/12] drm/i915: Disable VRR during seamless M/N changes

yrjälä > > Make life less confusing by making sure VRR is disabled whenever > we do any drastic changes to the display timings, such as seamless > M/N changes. > > Cc: Manasi Navare > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/display/intel_display.

Re: [Intel-gfx] [PATCH 08/12] drm/i915: Validate that the timings are within the VRR range

Reviewed-by: Manasi Navare Manasi On Fri, Sep 1, 2023 at 6:05 AM Ville Syrjala wrote: > > From: Ville Syrjälä > > Let's assume there are some crazy displays where the high > end of the VRR range ends up being lower than the refresh > rate as determined by the actual tim

Re: [Intel-gfx] [PATCH 07/12] drm/i915: Relocate is_in_vrr_range()

Reviewed-by: Manasi Navare Manasi On Fri, Sep 1, 2023 at 6:05 AM Ville Syrjala wrote: > > From: Ville Syrjälä > > Move is_in_vrr_range() into intel_vrr.c in anticipation of > more users, and rename it accordingly. > > Cc: Manasi Navare > Signed-off-by: Ville Syrjälä

Re: [Intel-gfx] [PATCH 06/12] drm/i915: Optimize out redundant M/N updates

Reviewed-by: Manasi Navare Manasi On Fri, Sep 1, 2023 at 6:05 AM Ville Syrjala wrote: > > From: Ville Syrjälä > > Don't perform a seamless M/N update if the values aren't actually > changing. This avoids doing extra shenanigans during vblank evasion > needlessly. >

Re: [Intel-gfx] [PATCH 05/12] drm/i915: Adjust seamless_m_n flag behaviour

Makes sense to rename the flag to update_m_n Reviewed-by: Manasi Navare Manasi On Fri, Sep 1, 2023 at 6:05 AM Ville Syrjala wrote: > > From: Ville Syrjälä > > Make the seamless_m_n flag more like the update_pipe fastset > flag, ie. the flag will only be set if we need to do t

Re: [Intel-gfx] [PATCH 04/12] drm/i915: Enable VRR later during fastsets

Looks good to me, Reviewed-by: Manasi Navare Manasi On Fri, Sep 1, 2023 at 6:05 AM Ville Syrjala wrote: > > From: Ville Syrjälä > > In order to reconcile seamless M/N updates with VRR we'll > need to defer the fastset VRR enable to happen after the > seamless M/N update (wh

Re: [Intel-gfx] [PATCH 02/12] drm/i915: Change intel_pipe_update_{start, end}() calling convention

Reviewed-by: Manasi Navare Manasi On Fri, Sep 1, 2023 at 6:05 AM Ville Syrjala wrote: > > From: Ville Syrjälä > > We'll need to also look at the old crtc state in > intel_pipe_update_start() so change the calling convention to > just plumb in the full atomic state inste

Re: [Intel-gfx] [PATCH 01/12] drm/i915: Move psr unlock out from the pipe update critical section

Looks good to me, Reviewed-by: Manasi Navare Manasi On Fri, Sep 1, 2023 at 6:04 AM Ville Syrjala wrote: > > From: Ville Syrjälä > > Do the PSR unlock after the vblank evade critcal section is > fully over, not before. > > Cc: Manasi Navare > Signed-off-by: Ville S

Re: [Intel-gfx] [PATCH v4 6/6] drm/i915/dp_link_training: Emit a link-status=Bad uevent with trigger property

roperty_event instead of the earlier generic drm_kms_helper_connector_hotplug_event. This will need some changes in other userspaces that parse this else it will cause failures for other userspace once this lands. With all the above changes, Acked-by: Manasi Navare Regards Manasi > > Signe

Re: [Intel-gfx] [PATCH 4/6] drm/i915: Enable VRR later during fastsets

On Tue, Aug 29, 2023 at 1:26 AM Ville Syrjälä wrote: > > On Mon, Aug 28, 2023 at 11:47:49AM -0700, Manasi Navare wrote: > > On Sun, Aug 27, 2023 at 10:41 PM Ville Syrjala > > wrote: > > > > > > From: Ville Syrjälä > > > > > > In order to re

Re: [Intel-gfx] [PATCH 4/6] drm/i915: Enable VRR later during fastsets

g any non-modeset commit, and also grab > the current state of VRR from the active timings (as we disable > VRR before vblank evasion during fastsets). > > This also fixes vblank evasion for seamless M/N updates as > we now properly account for the fact that the M/N update > happ

Re: [Intel-gfx] [PATCH 3/6] drm/i915: Extract intel_crtc_vblank_evade_scanlines()

This looks good to me, Reviewed-by: Manasi Navare Manasi On Sun, Aug 27, 2023 at 10:41 PM Ville Syrjala wrote: > > From: Ville Syrjälä > > Pull the vblank evasion scanline calculations into their own helper > to declutter intel_pipe_update_start() a bit. > > Cc: Manasi

Re: [Intel-gfx] [PATCH 2/6] drm/i915: Change intel_pipe_update_{start, end}() calling convention

the old crtc state to look at if VRR parameters were changed? Could we elaborate why we would need old crtc state so we better understand this change in the patch? Manasi > > Cc: Manasi Navare > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/display/intel_crtc.c| 18

Re: [Intel-gfx] [PATCH 1/6] drm/i915: Move psr unlock out from the pipe update critical section

> > Do the PSR unlock after the vblank evade critcal section is > fully over, not before. > > Cc: Manasi Navare > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/display/intel_crtc.c | 9 + > 1 file changed, 5 insertions(+), 4 deletions(-) > > di

[Intel-gfx] [PATCH 2/2] drm/i915/display/vrr: Update VRR parameters in fastset

together. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9154 Cc: Drew Davenport Cc: Ville Syrjälä Cc: Sean Paul Cc: Jani Nikula Signed-off-by: Manasi Navare --- drivers/gpu/drm/i915/display/intel_display.c | 20 +++- 1 file changed, 19 insertions(+), 1 deletion(-) diff

[Intel-gfx] [PATCH 1/2] drm/i915/display: Allow VRR parameters mismatch in case of dual refresh rate fastset

Cc: Jani Nikula Signed-off-by: Manasi Navare --- drivers/gpu/drm/i915/display/intel_display.c | 15 ++- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index db3c26e013e3

Re: [Intel-gfx] [PATCH v4] drm/i915/display: Dual refresh rate fastset fixes with VRR fastset

Hi @Jani Nikula , Thanks for your feedback. Please find my comments below: On Thu, Aug 24, 2023 at 4:27 AM Jani Nikula wrote: > > On Fri, 18 Aug 2023, Manasi Navare wrote: > > Dual refresh rate (DRR) fastset seamlessly lets refresh rate > > throttle without needing a full mo

Re: [Intel-gfx] [PATCH v4] drm/i915/display: Dual refresh rate fastset fixes with VRR fastset

wrote: > > On Thu, Aug 24, 2023 at 02:27:49PM +0300, Jani Nikula wrote: > > On Fri, 18 Aug 2023, Manasi Navare wrote: > > > Dual refresh rate (DRR) fastset seamlessly lets refresh rate > > > throttle without needing a full modeset. > > > However with the rec

[Intel-gfx] [PATCH] drm/i915/display/vrr: Compute VRR min/max based on highest clock mode for DRRS panel

VRR parameters. Cc: Ville Syrjälä Cc: Jani Nikula Signed-off-by: Manasi Navare --- drivers/gpu/drm/i915/display/intel_dp.c | 4 ++-- drivers/gpu/drm/i915/display/intel_dp.h | 2 ++ drivers/gpu/drm/i915/display/intel_vrr.c | 7 --- 3 files changed, 8 insertions(+), 5 deletions(-) diff

Re: [Intel-gfx] [PATCH v4] drm/i915/display: Dual refresh rate fastset fixes with VRR fastset

, Aug 18, 2023 at 12:05 PM Manasi Navare wrote: > > Dual refresh rate (DRR) fastset seamlessly lets refresh rate > throttle without needing a full modeset. > However with the recent VRR fastset patches that got merged this > logic was broken. This is broken because now with VR

[Intel-gfx] [PATCH v4] drm/i915/display: Dual refresh rate fastset fixes with VRR fastset

mismatch in crtc clock whenever VRR is enabled Fixes: 1af1d18825d3 ("drm/i915/vrr: Allow VRR to be toggled during fastsets") Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9154 Cc: Drew Davenport Cc: Ville Syrjälä Cc: Sean Paul Cc: Mitul Golani Signed-off-by: Man

Re: [Intel-gfx] [PATCH 1/3] drm/i915/dp_link_training: Add a final failing state to link training fallback

ed as connected. > > Cc: Jani Nikula > Cc: Manasi Navare > Cc: Sean Paul > Signed-off-by: Gil Dekel > --- > drivers/gpu/drm/i915/display/intel_dp.c | 18 -- > 1 file changed, 16 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/displ

Re: [Intel-gfx] [PATCH v3] drm/i915/display: Dual refresh rate fastset fixes with VRR fastset

Hi Jani, Thanks for your feedback. Please see my comments below, On Tue, Aug 15, 2023 at 11:02 AM Jani Nikula wrote: > > On Mon, 14 Aug 2023, Manasi Navare wrote: > > Dual refresh rate (DRR) fastset seamlessly lets refresh rate > > throttle without needing a full modeset. >

[Intel-gfx] [PATCH v3] drm/i915/display: Dual refresh rate fastset fixes with VRR fastset

mismatch in crtc clock whenever VRR is enabled Cc: Drew Davenport Cc: Ville Syrjälä Cc: Sean Paul Cc: Mitul Golani Signed-off-by: Manasi Navare --- drivers/gpu/drm/i915/display/intel_display.c | 14 -- 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm

[Intel-gfx] [PATCH v2] drm/i915/display: Dual refresh rate fastset fixes with VRR fastset

crtc clock and written to HW. This DRR + VRR fastset in conjunction needs more work in the driver and will be fixed in later patches. v2: Check for pipe config mismatch in crtc clock whenever VRR is enabled Cc: Drew Davenport Cc: Ville Syrjälä Cc: Sean Paul Signed-off-by: Manasi Navare

[Intel-gfx] [PATCH] drm/i915/display: Dual refresh rate fastset fixes with VRR fastset

crtc clock and written to HW. This DRR + VRR fastset in conjunction needs more work in the driver and will be fixed in later patches. Cc: Drew Davenport Cc: Ville Syrjälä Cc: Sean Paul Signed-off-by: Manasi Navare --- drivers/gpu/drm/i915/display/intel_display.c | 14 -- 1 file

Re: [Intel-gfx] [PATCH v2] i915/display/hotplug: use drm_kms_helper_connector_hotplug_event()

It looks good to me and will be very helpful for Chrome userspace, but can we get some R-B from Intel folks so we can get this merged? Regards Manasi On Mon, Jul 10, 2023 at 12:27 AM Simon Ser wrote: > > Any news about this patch?

Re: [Intel-gfx] [PATCH] drm/i915/display: Return correct err code for bpc < 0

nkit K wrote: > > > > On 4/18/2023 6:16 PM, Ville Syrjälä wrote: > > > On Mon, Apr 17, 2023 at 03:48:12PM -0700, Manasi Navare wrote: > > >> Hi Ville, > > >> > > >> Could you suggest how to handle the intel_dp_link_compute_config() > >

Re: [Intel-gfx] [PATCH] drm/i915/display: Return correct err code for bpc < 0

of trying DSC, correct? Manasi On Thu, Apr 13, 2023 at 8:23 AM Manasi Navare wrote: > > On Tue, Apr 11, 2023 at 10:22 PM Ville Syrjälä > wrote: > > > > On Tue, Apr 11, 2023 at 05:07:01PM -0700, Manasi Navare wrote: > > > On Tue, Apr 11, 2023 at 10:42 AM Ville Syrjälä > &

Re: [Intel-gfx] [PATCH] drm/i915/display: Return correct err code for bpc < 0

On Tue, Apr 11, 2023 at 10:22 PM Ville Syrjälä wrote: > > On Tue, Apr 11, 2023 at 05:07:01PM -0700, Manasi Navare wrote: > > On Tue, Apr 11, 2023 at 10:42 AM Ville Syrjälä > > wrote: > > > > > > On Tue, Apr 11, 2023 at 05:34:08PM +, Manasi N

Re: [Intel-gfx] [PATCH] drm/i915/display: Return correct err code for bpc < 0

On Tue, Apr 11, 2023 at 10:42 AM Ville Syrjälä wrote: > > On Tue, Apr 11, 2023 at 05:34:08PM +, Manasi Navare wrote: > > In the function intel_dp_max_bpp(), currently if bpc < 0 in case of error, > > we return 0 instead of returning an err code of -EINVAL. > >

[Intel-gfx] [PATCH] drm/i915/display: Return correct err code for bpc < 0

al Cc: Sean Paul Signed-off-by: Manasi Navare --- drivers/gpu/drm/i915/display/intel_dp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index f0bace9d98a1..f6546292e7c6 100644 --- a/drivers/g

Re: [Intel-gfx] [PATCH 2/2] drm/i915/dp: Use current cdclk for DSC Bigjoiner BW check

On Thu, Mar 30, 2023 at 4:11 AM Nautiyal, Ankit K wrote: > > > On 3/29/2023 5:05 PM, Ville Syrjälä wrote: > > On Wed, Mar 29, 2023 at 05:00:55PM +0530, Nautiyal, Ankit K wrote: > >> On 3/29/2023 4:23 PM, Ville Syrjälä wrote: > >>> On Wed, Mar 29, 2023 at 04:06:21PM +0530, Nautiyal, Ankit K wrote:

Re: [Intel-gfx] [PATCH v11 08/11] drm/i915/dp: Avoid DSC with output_format YCBCR420

Since we cannot do DSC with this output format currently, can this check be added as part of the intel_dp_supports_dsc() ? Regards Manasi On Tue, Mar 14, 2023 at 4:07 AM Ankit Nautiyal wrote: > Currently, DSC with YCBCR420 is not supported. > Return -EINVAL when trying with DSC with

[Intel-gfx] [PATCH v2] drm/i915/display: Add a separate crtc_enable hook for SKL+

: Ville Syrjälä Cc: Jani Nikula Signed-off-by: Manasi Navare --- drivers/gpu/drm/i915/display/intel_display.c | 64 1 file changed, 52 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c

[Intel-gfx] [PATCH] drm/i915/display: Add a separate crtc_enable hook for SKL+

-off-by: Manasi Navare --- drivers/gpu/drm/i915/display/intel_display.c | 74 +++- 1 file changed, 73 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 806d50b302ab..e2e228073e2e 100644

[Intel-gfx] [PATCH] drm/i915/display/: Refactor hsw_crtc_enable for bigjoiner cleanup

This patch abstracts pieces of hsw_crtc_enable corresponding to different Bspec enable sequence steps into separate functions. This helps to call them in a specific order for bigjoiner master/slave in a cleaner fashion. Cc: Ville Syrjälä Cc: Animesh Manna Signed-off-by: Manasi Navare

[Intel-gfx] [PATCH v7] drm/i915/display/vrr: Reset VRR capable property on a long hpd

: 390a1f8beb87 ("Revert "drm/i915/display/vrr: Reset VRR capable property on a long hpd") Signed-off-by: Manasi Navare --- drivers/gpu/drm/i915/display/intel_dp.c | 17 +++-- 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c

[Intel-gfx] [PATCH v6 1/2] drm/vrr: Set VRR capable prop only if it is attached to connector

Signed-off-by: Manasi Navare --- drivers/gpu/drm/drm_connector.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c index a50c82bc2b2f..76a8c707c34b 100644 --- a/drivers/gpu/drm/drm_connector.c +++ b/drivers/gpu/drm/drm_connector.c

[Intel-gfx] [PATCH v6 2/2] drm/i915/display/vrr: Reset VRR capable property on a long hpd

Reset VRR capable property on a long hpd") Signed-off-by: Manasi Navare --- drivers/gpu/drm/i915/display/intel_dp.c | 15 +++ 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c ind

[Intel-gfx] [PATCH v5] drm/i915/display/vrr: Reset VRR capable property on a long hpd

) Remove the redundant comment (Jan N) v5: Fixes the regression on older platforms by reseting the VRR only if HAS_VRR Cc: Jani Nikula Cc: Ville Syrjälä Fixes: 390a1f8beb87 ("Revert "drm/i915/display/vrr: Reset VRR capable property on a long hpd") Signed-off-by: Manasi Navare ---

[Intel-gfx] [PATCH v3] drm/i915/display/vrr: Reset VRR capable property on a long hpd

) Remove the redundant comment (Jan N) Cc: Jani Nikula Signed-off-by: Manasi Navare --- drivers/gpu/drm/i915/display/intel_dp.c | 17 + 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c

[Intel-gfx] [PATCH v2] drm/i915/display/vrr: Reset VRR capable property on a long hpd

. Hence the userspace still sees this as VRR Capable panel which is incorrect. Fix this by explicitly resetting the connector property. v2: Reset vrr capable if status == connector_disconnected v3: Use i915 and use bool vrr_capable (Jani Nikula) Cc: Jani Nikula Signed-off-by: Manasi Navare

[Intel-gfx] [PATCH] drm/i915/display/vrr: Reset VRR capable property on a long hpd

. Hence the userspace still sees this as VRR Capable panel which is incorrect. Fix this by explicitly resetting the connector property. Signed-off-by: Manasi Navare --- drivers/gpu/drm/i915/display/intel_dp.c | 11 ++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu

[Intel-gfx] [PATCH] drm/i915/: Extend VRR platform support to Gen 11

VRR is supported on Gen 11 HW , hence extend the support in the driver to enable this for Gen 11. Cc: Ville Syrjälä Signed-off-by: Manasi Navare --- drivers/gpu/drm/i915/i915_drv.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu

[Intel-gfx] [PATCH] drm/i915/display/dsc: Clamp the max DSC input BPP to connector's max bpp

on connector's max bpp. This patch fixes that. Cc: Jani Nikula Cc: Vandita Kulkarni Cc: Ville Syrjälä Signed-off-by: Manasi Navare --- drivers/gpu/drm/i915/display/intel_dp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display

[Intel-gfx] [PATCH v3] drm/atomic: Add the crtc to affected crtc only if uapi.enable = true

lle) Cc: Ville Syrjälä Cc: Simon Ser Cc: Pekka Paalanen Cc: Daniel Stone Cc: Daniel Vetter Cc: dri-de...@lists.freedesktop.org Signed-off-by: Manasi Navare --- drivers/gpu/drm/drm_atomic.c | 12 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/

[Intel-gfx] [PATCH v2] drm/atomic: Add the crtc to affected crtc only if uapi.enable = true

in review comments because the crtc gets stolen only after the atomic_check call. Cc: Ville Syrjälä Cc: Simon Ser Cc: Pekka Paalanen Cc: Daniel Stone Cc: Daniel Vetter Cc: dri-de...@lists.freedesktop.org Signed-off-by: Manasi Navare --- drivers/gpu/drm/drm_atomic.c | 6 -- 1 file changed, 4

[Intel-gfx] [PATCH] drm/i915/display: Fix shared dpll mismatch for bigjoiner slave

://gitlab.freedesktop.org/drm/intel/-/issues/3465 Cc: Ville Syrjälä Cc: Ankit Nautiyal Tested-By: Swati Sharma Signed-off-by: Manasi Navare --- drivers/gpu/drm/i915/display/intel_display.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915

[Intel-gfx] [PATCH] drm/i915/display: Fix shared dpll mismatch for bigjoiner slave

://gitlab.freedesktop.org/drm/intel/-/issues/3465 Cc: Ville Syrjälä Cc: Ankit Nautiyal Signed-off-by: Manasi Navare --- drivers/gpu/drm/i915/display/intel_display.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display

[Intel-gfx] [PATCH v2] drm/i915: Initialize the mbus_offset to fix static analysis issue

Static analysis identified an issue in skl_crtc_allocate_ddb where mbus_offset may be used uninitialized. This patch fixes it. Fixes: 835c176cb1c4 ("drm/i915: Introduce MBUS relative dbuf offsets") Cc: Ville Syrjälä Signed-off-by: Manasi Navare --- drivers/gpu/drm/i915/intel_pm.c

[Intel-gfx] [PATCH] drm/i915: Initialize the mbus_offset to fix Klockwork issue

Static analysis identified an issue in skl_crtc_allocate_ddb where mbus_offset may be used uninitialized. This patch fixes it. Fixes: 835c176cb1c4 ("drm/i915: Introduce MBUS relative dbuf offsets") Cc: Ville Syrjälä Signed-off-by: Manasi Navare --- drivers/gpu/drm/i915/intel_pm.c

[Intel-gfx] [PATCH] drm/atomic: Add the crtc to affected crtc only if uapi.enable = true

: Daniel Vetter Cc: dri-de...@lists.freedesktop.org Signed-off-by: Manasi Navare --- drivers/gpu/drm/drm_atomic.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c index 5b4547e0f775..d7acd6bbd97e 100644 --- a/drivers

[Intel-gfx] [PATCH] Revert "drm/atomic: document and enforce rules around "spurious" EBUSY"

. Cc: Ville Syrjala Cc: Daniel Vetter Signed-off-by: Manasi Navare --- drivers/gpu/drm/drm_atomic.c | 29 - 1 file changed, 29 deletions(-) diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c index b1efa9322be2..48b2262d69f6 100644 --- a/drivers

[Intel-gfx] [PATCH] drm/i915/display/vrr: Skip the VRR HW state readout on DSI transcoder

DSI transcoder does not support VRR and hence skip the HW state readout if its a DSI transcoder. Fixes: c7f0f4372b30 ("drm/i915/display: Add HW state readout for VRR") Cc: Ville Syrjälä Cc: Jani Nikula Cc: Vandita Kulkarni Signed-off-by: Manasi Navare --- drivers/gpu/drm/i9

[Intel-gfx] [CI v6] drm/i915/display/vrr: Create VRR file and add VRR capability check

(Manasi) Cc: Ville Syrjälä Cc: Jani Nikula Signed-off-by: Manasi Navare Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/Makefile| 1 + drivers/gpu/drm/i915/display/intel_vrr.c | 31 drivers/gpu/drm/i915/display/intel_vrr.h | 15 drivers/gpu/drm

[Intel-gfx] [CI v5 03/18] drm/i915: Store framestart_delay in dev_priv

it into dev_priv for now. v2: * Rebase on drm-tip (Manasi) v3: * Framestart_delay as 1 - 4 to align with HW Signed-off-by: Manasi Navare Signed-off-by: Ville Syrjälä Reviewed-by: Manasi Navare --- drivers/gpu/drm/i915/display/intel_display.c | 23 ++-- drivers/gpu/drm/i915

[Intel-gfx] [CI v5 16/18] drm/i915: Add vrr state dump

From: Ville Syrjälä Dump vrr state alongside everything else. Signed-off-by: Ville Syrjälä Reviewed-by: Manasi Navare --- drivers/gpu/drm/i915/display/intel_display.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm

[Intel-gfx] [CI v5 15/18] drm/i915/display: Helpers for VRR vblank min and max start

extra scanline const (Manasi) Signed-off-by: Manasi Navare Signed-off-by: Ville Syrjälä Reviewed-by: Manasi Navare --- drivers/gpu/drm/i915/display/intel_vrr.c | 36 drivers/gpu/drm/i915/display/intel_vrr.h | 2 ++ 2 files changed, 38 insertions(+) diff --git a/drivers

[Intel-gfx] [CI v5 12/18] drm/i915/display/vrr: Disable VRR in modeset disable path

Syrjälä Signed-off-by: Manasi Navare Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++ drivers/gpu/drm/i915/display/intel_vrr.c | 13 + drivers/gpu/drm/i915/display/intel_vrr.h | 1 + 3 files changed, 16 insertions(+) diff --git a/drivers/gpu/drm

[Intel-gfx] [CI v5 10/18] drm/i915/display/vrr: Configure and enable VRR in modeset enable

for TRANS_VRR regs (Ville) Cc: Ville Syrjälä Signed-off-by: Manasi Navare Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_ddi.c | 3 +++ drivers/gpu/drm/i915/display/intel_vrr.c | 22 ++ drivers/gpu/drm/i915/display/intel_vrr.h | 3 +++ 3 files changed, 28

[Intel-gfx] [CI v5 17/18] drm/i915: Fix vblank timestamps with VRR

d then we adjust the reported scanout position accordingly so that the core will see that the vblank is close to ending. v2: * Fix the else if (use_scanline_Counter) (Manasi) Signed-off-by: Ville Syrjälä Reviewed-by: Manasi Navare --- drivers/gpu/drm/i915/display/intel_display.

[Intel-gfx] [CI v5 09/18] drm/i915: Rename VRR_CTL reg fields

From: Ville Syrjälä Give the pipeline full line count bits more descriptive names Signed-off-by: Ville Syrjälä Signed-off-by: Manasi Navare Reviewed-by: Manasi Navare --- drivers/gpu/drm/i915/i915_reg.h | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git

[Intel-gfx] [CI v5 04/18] drm/i915: Extract intel_mode_vblank_start()

From: Ville Syrjälä We want to calculate the vblank_start for vblank evasion differently for vrr. To make that nicer lets first extract the current non-vrr case to a helper. Signed-off-by: Ville Syrjälä Reviewed-by: Manasi Navare --- drivers/gpu/drm/i915/display/intel_sprite.c | 14

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