Thanks for the comment.
I will revise this patch, so the change is only removing POST overriding.
In addition, the patch for removing TRAIL was submitted as
https://patchwork.kernel.org/project/intel-gfx/patch/20211217100903.32599-1-william.ts...@intel.com/.
Can you help to review as well?
For current VBT design, it does define the parameters ths_exit and tclk_post,
which are related to the timing values, TEOT and TCLK-POST respectively.
Unfortunately
they are not configurable from VBT because both parameters are constants passed
by VBT.
To fix the timing problems, shall the
drm-tip
patch link:
https://lore.kernel.org/r/20230901095100.3771188-1-william.tseng%40intel.com
patch subject: [Intel-gfx] [PATCH] drm/i915/dsi: let HW maintain HS-TRAIL and
CLK_POST
config: x86_64-defconfig
(https://download.01.org/0day-ci/archive/20230901/202309012129.sie9g3dy
drm-tip
patch link:
https://lore.kernel.org/r/20230901095100.3771188-1-william.tseng%40intel.com
patch subject: [Intel-gfx] [PATCH] drm/i915/dsi: let HW maintain HS-TRAIL and
CLK_POST
config: i386-randconfig-002-20230901
(https://download.01.org/0day-ci/archive/20230901/202309012009.7ixuigbj
On Fri, Sep 01, 2023 at 05:51:00PM +0800, William Tseng wrote:
> This change is to adjust TEOT timing and TCLK-POST timing so DSI
> signaling can meet CTS specification.
>
> For clock lane, the measured TEOT may be changed from 142.64 ns to
> 107.36 ns, which is less than (105 ns+12*UI) and is
On Fri, 01 Sep 2023, William Tseng wrote:
> This change is to adjust TEOT timing and TCLK-POST timing so DSI
> signaling can meet CTS specification.
>
> For clock lane, the measured TEOT may be changed from 142.64 ns to
> 107.36 ns, which is less than (105 ns+12*UI) and is conformed to
> mipi
This change is to adjust TEOT timing and TCLK-POST timing so DSI
signaling can meet CTS specification.
For clock lane, the measured TEOT may be changed from 142.64 ns to
107.36 ns, which is less than (105 ns+12*UI) and is conformed to
mipi D-PHY v1.2 CTS v1.0.
As to TCLK-POST, it may be changed
