[Intel-gfx] Write GFX_FLSH_CNT after updating GGTT entries

Hi Gurus: I'm curious about the register GFX_FLSH_CNT(0x101008) in i915_gem_gtt.c. Does these register exist in recently generations? After digging into b-spec, it looks only BXT and CHV has this register. Does the desktop platform also have this register which needs to be written after

[Intel-gfx] [RFC PATCH 2/2] drm/i915: make intel_backlight sysfs interface have range 0..100

Historically we have exposed the full backlight PWM duty cycle range from 0 to the PWM modulation frequency as the backlight range to the userspace. Since then, we have had to scale that to respect panel specific minimum duty cycles. Go for fully abstracting the PWM duty cycles and modulation

[Intel-gfx] [RFC PATCH 1/2] drm/i915: preserve min brightness across backlight disable/enable

We try to preserve the backlight brightness across backlight disable/enable, except for minimum brightness. Currently, if the backlight is at minimum, we crank the backlight to max on enable. Preserve the minimum too, and turn the code into a sanity check instead. Cc: Chris Wilson

Re: [Intel-gfx] [PATCH] Add Kabylake PCI IDs

On Wed, Nov 18, 2015 at 10:39:42AM -0800, Wayne Boyer wrote: > Add the Kabylake PCI IDs based on the following patches. > > commit d97044b661d0d56b2a2ae9b2b95ab0b359b417dc > Author: Deepak S > Date: Wed Oct 28 12:19:51 2015 -0700 > > drm/i915/kbl: Add Kabylake PCI ID >

Re: [Intel-gfx] [Announcement] 2015-Q3 release of XenGT - a Mediated Graphics Passthrough Solution from Intel

Hi, > > Another area of extension is how to expose a framebuffer to QEMU for > > seamless integration into a SPICE/VNC channel. For this I believe we > > could use a new region, much like we've done to expose VGA access > > through a vfio device file descriptor. An area within this new > >

[Intel-gfx] [PATCH] Revert "drm/i915: skip modeset if compatible for everyone."

This reverts commit 6764e9f8724f1231b4deac53b9a82286ac0830e7 Author: Maarten Lankhorst Date: Thu Aug 27 15:44:06 2015 +0200 drm/i915: skip modeset if compatible for everyone. Bring back the i915.fastboot module parameter, disabled by default, due to

Re: [Intel-gfx] [PATCH v2 maintainer-tools] dim: Replace git commit --amend from dim_apply with dimrc option

On Wed, 2015-11-18 at 16:52 +0100, Daniel Vetter wrote: > On Mon, Nov 16, 2015 at 12:17:15PM +0200, Ander Conselvan de Oliveira wrote: > > Introduce DIM_POST_APPLY_ACTION to dimrc that allows the user to specify > > a command to be run after a patch is applied. Use eval so enviroment > > variables

[Intel-gfx] [PATCH 1/1] drm/i915/audio: apply SKL codec wake up patch to BXT

From: "Lu, Han" Signed-off-by: Lu, Han diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c index 63d4706..8310bf3 100644 --- a/drivers/gpu/drm/i915/intel_audio.c +++ b/drivers/gpu/drm/i915/intel_audio.c @@ -591,7 +591,8 @@

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Also delay first activation for SKL+

Hi Rodrigo, On 19 November 2015 at 00:39, Rodrigo Vivi wrote: > @@ -441,15 +438,14 @@ void intel_psr_enable(struct intel_dp *intel_dp) > /* > * FIXME: Activation should happen immediately since this function > * is just called after pipe is fully

Re: [Intel-gfx] [PATCH] drm/atomic-helper: Check encoder/crtc constraints

Hi, On 18 November 2015 at 17:46, Daniel Vetter wrote: > This was totally lost when I originally created the atomic helpers. > > We probably should also check possible_clones in the helpers, but > since the legacy ones didn't do that this is for a separate patch. Heh,

Re: [Intel-gfx] [PATCH] Revert "drm/i915: skip modeset if compatible for everyone."

On Thu, 19 Nov 2015, Jani Nikula wrote: > This reverts > > commit 6764e9f8724f1231b4deac53b9a82286ac0830e7 > Author: Maarten Lankhorst > Date: Thu Aug 27 15:44:06 2015 +0200 > > drm/i915: skip modeset if compatible for everyone. > >

Re: [Intel-gfx] [PATCH 1/1] drm/i915/audio: apply SKL codec wake up patch to BXT

On Thu, 19 Nov 2015, han...@intel.com wrote: > From: "Lu, Han" > > Signed-off-by: Lu, Han > > diff --git a/drivers/gpu/drm/i915/intel_audio.c > b/drivers/gpu/drm/i915/intel_audio.c > index 63d4706..8310bf3 100644 > --- a/drivers/gpu/drm/i915/intel_audio.c >

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Serialise updates to GGTT with access through GGTT on Braswell

On Wed, Nov 18, 2015 at 03:08:47PM -0800, Jesse Barnes wrote: > On 11/17/2015 08:37 AM, Daniel Vetter wrote: > > On Fri, Oct 30, 2015 at 04:58:41PM +, Chris Wilson wrote: > >> On Fri, Oct 30, 2015 at 05:14:21PM +0100, Daniel Vetter wrote: > >>> On Fri, Oct 23, 2015 at 06:43:32PM +0100, Chris

[Intel-gfx] [PATCH v2] drm/i915: Mark uneven memory banks on gen4 desktop as unknown swizzling

We have varied reports of swizzling corruption on gen4 desktop, and confirmation that one at least is triggered by uneven memory banks (L-shaped memory). The implication is that the swizzling varies between the paired channels and the remainder of memory on the single channel. As the object then

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Only spin whilst waiting on the current request

Hi, On 18/11/15 09:56, Chris Wilson wrote: Limit busywaiting only to the request currently being processed by the GPU. If the request is not currently being processed by the GPU, there is a very low likelihood of it being completed within the 2 microsecond spin timeout and so we will just be

Re: [Intel-gfx] [PATCH] drm/atomic-helper: Check encoder/crtc constraints

On Wed, Nov 18, 2015 at 06:46:48PM +0100, Daniel Vetter wrote: > This was totally lost when I originally created the atomic helpers. > > We probably should also check possible_clones in the helpers, but > since the legacy ones didn't do that this is for a separate patch. > > Reported-by: Ville

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Only spin whilst waiting on the current request

On Thu, Nov 19, 2015 at 10:05:39AM +, Tvrtko Ursulin wrote: > > Hi, > > On 18/11/15 09:56, Chris Wilson wrote: > >Limit busywaiting only to the request currently being processed by the > >GPU. If the request is not currently being processed by the GPU, there > >is a very low likelihood of it

Re: [Intel-gfx] [PATCH 1/1] drm/i915/audio: apply SKL codec wake up patch to BXT

On Thu, 19 Nov 2015, Jani Nikula wrote: > On Thu, 19 Nov 2015, han...@intel.com wrote: >> From: "Lu, Han" >> >> Signed-off-by: Lu, Han >> >> diff --git a/drivers/gpu/drm/i915/intel_audio.c >> b/drivers/gpu/drm/i915/intel_audio.c >>

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Serialise updates to GGTT with access through GGTT on Braswell

On Thu, Nov 19, 2015 at 10:14:08AM +0100, Daniel Vetter wrote: > On Wed, Nov 18, 2015 at 03:08:47PM -0800, Jesse Barnes wrote: > > On 11/17/2015 08:37 AM, Daniel Vetter wrote: > > > On Fri, Oct 30, 2015 at 04:58:41PM +, Chris Wilson wrote: > > >> On Fri, Oct 30, 2015 at 05:14:21PM +0100,

Re: [Intel-gfx] [PATCH 12/31] drm/i915: Fix PSR initialization.

On Wed, Nov 18, 2015 at 06:39:45PM +, Vivi, Rodrigo wrote: > On Wed, 2015-11-18 at 11:12 +0100, Daniel Vetter wrote: > > On Thu, Nov 05, 2015 at 10:50:04AM -0800, Rodrigo Vivi wrote: > > > PSR is still disabled by default, but even passing > > > i915.enable_psr=1 > > > at this point we

Re: [Intel-gfx] [PATCH i-g-t] Add dmesg capture and dumping to tests and a test for it.

On Thu, Nov 19, 2015 at 10:38 AM, Daniel Vetter wrote: > On Wed, Nov 18, 2015 at 05:32:59PM +, Chris Wilson wrote: >> On Wed, Nov 18, 2015 at 04:44:20PM +0100, Daniel Vetter wrote: >> > On Mon, Nov 16, 2015 at 03:22:23PM +0200, Joonas Lahtinen wrote: >> > > Cc: Thomas Wood

Re: [Intel-gfx] [PATCH] drm/i915: Use dpcd read wake for sink crc calls.

On Wed, Nov 18, 2015 at 06:31:05PM +, Vivi, Rodrigo wrote: > On Tue, 2015-11-17 at 15:08 +0100, Daniel Vetter wrote: > > On Mon, Nov 16, 2015 at 04:05:42PM +, Rodrigo Vivi wrote: > > > Ok, so after trying it we saw that we really cannot trust on aux > > > mutex.At > > > least not on all

Re: [Intel-gfx] [PATCH v3] drm/i915: Ensure associated VMAs are inactive when contexts are destroyed

On Wed, Nov 18, 2015 at 05:18:30PM +, Tvrtko Ursulin wrote: > > On 17/11/15 17:56, Daniel Vetter wrote: > > On Tue, Nov 17, 2015 at 05:24:01PM +, Tvrtko Ursulin wrote: > >> > >> On 17/11/15 17:08, Daniel Vetter wrote: > >>> On Tue, Nov 17, 2015 at 04:54:50PM +, Tvrtko Ursulin wrote: >

Re: [Intel-gfx] [PATCH 10/31] drm/i915: Detatch i915.enable_psr from psr_ready

On Wed, Nov 18, 2015 at 06:35:15PM +, Vivi, Rodrigo wrote: > On Wed, 2015-11-18 at 11:07 +0100, Daniel Vetter wrote: > > On Thu, Nov 05, 2015 at 10:50:02AM -0800, Rodrigo Vivi wrote: > > > PSR will be enabled on every post primary update when it is > > > ready and parameter allows. > > > With

Re: [Intel-gfx] [PATCH i-g-t] Add dmesg capture and dumping to tests and a test for it.

On Wed, Nov 18, 2015 at 05:32:59PM +, Chris Wilson wrote: > On Wed, Nov 18, 2015 at 04:44:20PM +0100, Daniel Vetter wrote: > > On Mon, Nov 16, 2015 at 03:22:23PM +0200, Joonas Lahtinen wrote: > > > Cc: Thomas Wood > > > Cc: Chris Wilson > > >

Re: [Intel-gfx] [PATCH v3] drm/i915: Ensure associated VMAs are inactive when contexts are destroyed

On 19/11/15 09:17, Daniel Vetter wrote: On Wed, Nov 18, 2015 at 05:18:30PM +, Tvrtko Ursulin wrote: On 17/11/15 17:56, Daniel Vetter wrote: On Tue, Nov 17, 2015 at 05:24:01PM +, Tvrtko Ursulin wrote: On 17/11/15 17:08, Daniel Vetter wrote: On Tue, Nov 17, 2015 at 04:54:50PM +,

Re: [Intel-gfx] [PATCH] drm/i915: Allow unready gpu to be reset on gen8

Daniel Vetter writes: > On Mon, Nov 02, 2015 at 11:25:08AM +0200, Mika Kuoppala wrote: >> Gen9 has had demonstrated cases where forcing a not ready gpu >> into reset has caused system hang [1]. >> >> Gen8 has never to this date demonstrated such behaviour. >> >> In our CI

Re: [Intel-gfx] [PATCH 11/9] drm/i915: Opt out of vblank disable timer on >gen2

2014-05-26 11:26 GMT-03:00 : > From: Ville Syrjälä > > Now that the vblank races are plugged, we can opt out of using > the vblank disable timer and just let vblank interrupts get > disabled immediately when the last reference is

Re: [Intel-gfx] [PATCH] drm/i915/skl: enable PC9/10 power states during suspend-to-idle

On to, 2015-11-19 at 19:00 +0100, Patrik Jakobsson wrote: > On Thu, Nov 19, 2015 at 04:06:47PM +0200, Imre Deak wrote: > > On to, 2015-11-19 at 14:34 +0100, Patrik Jakobsson wrote: > > > On Wed, Nov 18, 2015 at 06:44:43PM +0200, Imre Deak wrote: > > > > On ke, 2015-11-18 at 17:33 +0100, Daniel

Re: [Intel-gfx] [PATCH 2/2] drm/i915: take a power domain reference while checking the HDMI live status

On Thu, Nov 19, 2015 at 08:55:01PM +0200, Imre Deak wrote: > There are platforms that don't need the full GMBUS power domain > (PCH, BXT) while others do (VLV/CHV). For optimizing this we > would need to add a new power domain, but it's not clear how much we > would benefit given the short time we

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Remove PSR Perf Counter for SKL+

On Wed, Nov 18, 2015 at 11:45 PM, Jindal, Sonika wrote: > Hi Rodrigo, > > Which platform have you observed this issue on? Skylake and Kabylake > This looks really strange. It is expected actually. On DC5/6 states all read-only registers are reset and cannot be

[Intel-gfx] [PATCH 1/2] drm/i915/pm: Unconstify power_domain_str

Let us print human-parseable values from the power domain code; upcoming display code also wants to use it. Signed-off-by: Daniel Stone --- drivers/gpu/drm/i915/i915_debugfs.c | 67 + drivers/gpu/drm/i915/i915_drv.h | 66

[Intel-gfx] [PATCH 2/2] drm/i915/pm: Print offending domain in refcount failure

If we experience a refcounting failure in a power domain/well (unref'ing at least one too many times), log the name of the offending domain or well. Signed-off-by: Daniel Stone --- drivers/gpu/drm/i915/intel_runtime_pm.c | 8 ++-- 1 file changed, 6 insertions(+), 2

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Also delay first activation for SKL+

On Thu, 2015-11-19 at 08:44 +, Daniel Stone wrote: > Hi Rodrigo, > > On 19 November 2015 at 00:39, Rodrigo Vivi > wrote: > > @@ -441,15 +438,14 @@ void intel_psr_enable(struct intel_dp > > *intel_dp) > > /* > > * FIXME: Activation should happen

Re: [Intel-gfx] [PATCH 2/2] drm/i915: take a power domain reference while checking the HDMI live status

On Thu, 2015-11-19 at 21:08 +0200, Ville Syrjälä wrote: > On Thu, Nov 19, 2015 at 08:55:01PM +0200, Imre Deak wrote: > > There are platforms that don't need the full GMBUS power domain > > (PCH, BXT) while others do (VLV/CHV). For optimizing this we > > would need to add a new power domain, but

Re: [Intel-gfx] [PATCH] drm/i915/skl: enable PC9/10 power states during suspend-to-idle

On Thu, Nov 19, 2015 at 04:06:47PM +0200, Imre Deak wrote: > On to, 2015-11-19 at 14:34 +0100, Patrik Jakobsson wrote: > > On Wed, Nov 18, 2015 at 06:44:43PM +0200, Imre Deak wrote: > > > On ke, 2015-11-18 at 17:33 +0100, Daniel Vetter wrote: > > > > On Wed, Nov 18, 2015 at 05:32:30PM +0200, Imre

Re: [Intel-gfx] [PATCH 1/2] drm/i915/pm: Unconstify power_domain_str

On Thu, Nov 19, 2015 at 05:59:10PM +, Daniel Stone wrote: > Let us print human-parseable values from the power domain code; upcoming > display code also wants to use it. > > Signed-off-by: Daniel Stone > --- > drivers/gpu/drm/i915/i915_debugfs.c | 67 >

Re: [Intel-gfx] [PATCH 1/2] drm/i915/pm: Unconstify power_domain_str

On Thu, Nov 19, 2015 at 06:26:23PM +, Daniel Stone wrote: > Hey, > > On 19 November 2015 at 18:24, Ville Syrjälä > wrote: > > On Thu, Nov 19, 2015 at 05:59:10PM +, Daniel Stone wrote: > >> +static inline const char * > >>

Re: [Intel-gfx] [PATCH] drm/i915/skl: re-enable power well support

On Wed, Nov 18, 2015 at 07:53:50PM +0200, Imre Deak wrote: > Now that the known DMC/DC issues are fixed, let's try again and > re-enable the power well support. > > Signed-off-by: Imre Deak Together with the PC9/10 fix this is: Reviewed-by: Patrik Jakobsson

Re: [Intel-gfx] [PATCH 1/2] drm/i915/pm: Unconstify power_domain_str

Hey, On 19 November 2015 at 18:24, Ville Syrjälä wrote: > On Thu, Nov 19, 2015 at 05:59:10PM +, Daniel Stone wrote: >> +static inline const char * >> +intel_display_power_domain_str(enum intel_display_power_domain domain) > > It's still const. And I assume now

Re: [Intel-gfx] [PATCH 2/2] drm/i915: take a power domain reference while checking the HDMI live status

On Thu, Nov 19, 2015 at 09:13:04PM +0200, Imre Deak wrote: > On Thu, 2015-11-19 at 21:08 +0200, Ville Syrjälä wrote: > > On Thu, Nov 19, 2015 at 08:55:01PM +0200, Imre Deak wrote: > > > There are platforms that don't need the full GMBUS power domain > > > (PCH, BXT) while others do (VLV/CHV). For

Re: [Intel-gfx] [PATCH 11/9] drm/i915: Opt out of vblank disable timer on >gen2

On Thu, Nov 19, 2015 at 10:53:30PM +0200, Ville Syrjälä wrote: > On Thu, Nov 19, 2015 at 06:35:04PM -0200, Paulo Zanoni wrote: > > 2015-11-19 18:06 GMT-02:00 Ville Syrjälä : > > > On Thu, Nov 19, 2015 at 05:44:51PM -0200, Paulo Zanoni wrote: > > >> 2014-05-26 11:26

Re: [Intel-gfx] [PATCH 5/7] drm/i915: sseu: convert subslice count fields to subslice mask

On Wed, Oct 21, 2015 at 06:40:35PM +0300, Imre Deak wrote: > In an upcoming patch we'll need the actual mask of subslices in addition > to their count, so convert the subslice_per_slice field to a mask. > Also we can easily calculate subslice_total from the other fields, so > instead of storing a

Re: [Intel-gfx] [PATCH 7/7] drm/i915/bdw: sseu: fix sseu status parsing

On Wed, Oct 21, 2015 at 06:40:37PM +0300, Imre Deak wrote: > Currently when checking for fused off EUs we may ignore the EU count in > an enabled slice if there is any disabled slice preceding the enabled > one (with a lower slice ID). Perhaps this can't happen in reality, but > there is no reason

[Intel-gfx] [PATCH v1] drm/i915: Fix a false alert of memory leak when free LRC

From: Alex Dai There is a memory leak warning message from i915_gem_context_clean when GuC submission is enabled. The reason is that when LRC is released, its ppgtt could be still referenced. The assumption that all VMAs are unbound during release of LRC is not true. v1: Move

Re: [Intel-gfx] [PATCH 1/7] drm/i915: sseu: move sseu_dev_status to i915_drv.h

On Thu, Nov 19, 2015 at 03:10:14PM -0800, Ben Widawsky wrote: > On Wed, Oct 21, 2015 at 06:40:31PM +0300, Imre Deak wrote: > > The data in this struct is provided both by getting the > > slice/subslice/eu features available on a given platform and the actual > > runtime state of these same

[Intel-gfx] [PATCH] drm/i915/guc: Keep irq enabled during GuC cmd submission

From: Alex Dai When GuC Work Queue is full, driver will wait GuC for avaliable space by calling wait_for_atomic. If irq is disabled, lockup will happen because jiffies won't be updated. Issue is found in igt/gem_close_race. Signed-off-by: Alex Dai ---

[Intel-gfx] [PATCH V3 1/1] drm/i915/audio: apply SKL codec wake up patch to BXT

From: "Lu, Han" For SKL we added a commit 632f3ab95fe2 ("drm/i915/audio: add codec wakeup override enabled/disable callback"), in order to enable codec wakeup override signal, to allow re-enumeration of the controller on SKL after resume from low power state. In SKL, HDMI/DP

Re: [Intel-gfx] [PATCH 4/7] drm/i915: sseu: convert slice count field to mask

On Wed, Oct 21, 2015 at 06:40:34PM +0300, Imre Deak wrote: > In an upcoming patch we'll need the actual mask of slices in addition to > their count, so replace the count field with a mask. > > Signed-off-by: Imre Deak > --- > drivers/gpu/drm/i915/i915_debugfs.c | 14

[Intel-gfx] [PATCH v1] drm/i915: Defer LRC unpin and release

From: Alex Dai Can't immediately free LRC (neither unpin it) even all its referenced requests are completed, because HW still need a short period of time to save data to LRC status page. It is safe to free LRC when HW completes a request from a different LRC. Introduce a new

Re: [Intel-gfx] [PATCH V2 1/1] drm/i915/audio: apply SKL codec wake up patch to BXT

On 11/20/2015 12:01 AM, Jani Nikula wrote: On Thu, 19 Nov 2015, Daniel Vetter wrote: On Thu, Nov 19, 2015 at 10:44:48PM +0800, han...@intel.com wrote: From: "Lu, Han" For SKL we added a commit 632f3ab95fe2 ("drm/i915/audio: add codec wakeup override

Re: [Intel-gfx] [PATCH 11/9] drm/i915: Opt out of vblank disable timer on >gen2

On Thu, Nov 19, 2015 at 05:44:51PM -0200, Paulo Zanoni wrote: > 2014-05-26 11:26 GMT-03:00 : > > From: Ville Syrjälä > > > > Now that the vblank races are plugged, we can opt out of using > > the vblank disable timer and just let

Re: [Intel-gfx] [PATCH 11/9] drm/i915: Opt out of vblank disable timer on >gen2

2015-11-19 18:06 GMT-02:00 Ville Syrjälä : > On Thu, Nov 19, 2015 at 05:44:51PM -0200, Paulo Zanoni wrote: >> 2014-05-26 11:26 GMT-03:00 : >> > From: Ville Syrjälä >> > >> > Now that the vblank races are

Re: [Intel-gfx] [PATCH 1/2] drm/i915: take a power domain ref only when needed during HDMI detect

On Thu, Nov 19, 2015 at 08:55:00PM +0200, Imre Deak wrote: > Suggested by Ville. Do you mind explaining why this is done at the hdmi level and not the gmbus level? -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list

Re: [Intel-gfx] [PATCH 11/9] drm/i915: Opt out of vblank disable timer on >gen2

On Thu, Nov 19, 2015 at 06:35:04PM -0200, Paulo Zanoni wrote: > 2015-11-19 18:06 GMT-02:00 Ville Syrjälä : > > On Thu, Nov 19, 2015 at 05:44:51PM -0200, Paulo Zanoni wrote: > >> 2014-05-26 11:26 GMT-03:00 : > >> > From: Ville Syrjälä

Re: [Intel-gfx] [PATCH 1/2] drm/i915: take a power domain ref only when needed during HDMI detect

On Thu, 2015-11-19 at 20:51 +, Chris Wilson wrote: > On Thu, Nov 19, 2015 at 08:55:00PM +0200, Imre Deak wrote: > > Suggested by Ville. > > Do you mind explaining why this is done at the hdmi level and not the > gmbus level? To reduce the on/off toggling, since we don't have delayed

Re: [Intel-gfx] [PATCH] igt/gem_request_retire: Provoke context destruction with active VMAs

On Thu, Nov 19, 2015 at 05:24:03PM +, Tvrtko Ursulin wrote: > >>+ while (i % 4) > >>+ batch[i++] = MI_NOOP; > > Is this ok? I arrived at it by experimentation, kernel was > complaining that relocations are not 4-byte aligned without it. batch is u32, so all is

Re: [Intel-gfx] [PATCH] drm/i915: Try to fix MST for SKL

On 2015-11-10 21:15, Jesse Barnes wrote: On 08/17/2015 08:46 AM, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä Set up the DDI->PLL mapping on SKL also for MST links. Might help make MST operational on SKL. Cc: Maarten Lankhorst

[Intel-gfx] [PATCH i-g-t 1/2] lib/kbl: move KBL check from IS_SKYLAKE() to IS_GEN9()

Remove the KBL check from IS_SKYLAKE() following the kernel definition. Then, add the KBL check to IS_GEN9(). The idea is to avoid confusion. On the kernel side, the mix of SKY and KBL was nacked so the platforms are split. Cc: Rodrigo Vivi Signed-off-by: Wayne Boyer

[Intel-gfx] [PATCH i-g-t 2/2] lib/kbl: Add Kabylake GT4 PCI IDs

Add the Kabylake GT4 PCI IDs as defined in this kernel patch. commit 8b10c0cf21ec84618d4bf02c73c0543500ece68d Author: Deepak S Date: Wed Oct 28 12:21:12 2015 -0700 drm/i915/kbl: Add Kabylake GT4 PCI ID Cc: Rodrigo Vivi

[Intel-gfx] [PATCH 1/2] drm/i915: take a power domain ref only when needed during HDMI detect

Suggested by Ville. Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/intel_hdmi.c | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index fd86cef..17ced03 100644 ---

[Intel-gfx] [PATCH 2/2] drm/i915: take a power domain reference while checking the HDMI live status

There are platforms that don't need the full GMBUS power domain (PCH, BXT) while others do (VLV/CHV). For optimizing this we would need to add a new power domain, but it's not clear how much we would benefit given the short time we hold the reference. So for now let's keep things simple.

Re: [Intel-gfx] [Announcement] 2015-Q3 release of XenGT - a Mediated Graphics Passthrough Solution from Intel

Hi Kevin, On Thu, 2015-11-19 at 04:06 +, Tian, Kevin wrote: > > From: Alex Williamson [mailto:alex.william...@redhat.com] > > Sent: Thursday, November 19, 2015 2:12 AM > > > > [cc +qemu-devel, +paolo, +gerd] > > > > On Tue, 2015-10-27 at 17:25 +0800, Jike Song wrote: > > > Hi all, > > > > >

Re: [Intel-gfx] [PATCH v3 1/2] drm/i915: Tear down fbdev if initialization fails

Hi again, On Thu, Nov 19, 2015 at 05:02:04PM +0100, Daniel Vetter wrote: > On Wed, Nov 18, 2015 at 01:43:20PM +0100, Lukas Wunner wrote: > > --- a/drivers/gpu/drm/i915/intel_dp_mst.c > > +++ b/drivers/gpu/drm/i915/intel_dp_mst.c > > @@ -408,7 +408,10 @@ static void

Re: [Intel-gfx] [PATCH] drm/sysfs: Send out uevent when connector->force changes

On Thu, Nov 19, 2015 at 05:46:50PM +0100, Daniel Vetter wrote: > To avoid even more code duplication punt this all to the probe worker, > which needs some slight adjustment to also generate a uevent when the > status has changed to due connector->force. > > v2: Instead of running the

Re: [Intel-gfx] [PATCH 11/9] drm/i915: Opt out of vblank disable timer on >gen2

On Thu, Nov 19, 2015 at 10:06:01PM +0200, Ville Syrjälä wrote: > On Thu, Nov 19, 2015 at 05:44:51PM -0200, Paulo Zanoni wrote: > > 2014-05-26 11:26 GMT-03:00 : > > > From: Ville Syrjälä > > > > > > Now that the vblank races are

[Intel-gfx] [PATCH 06/12] drm/i915: alloc/free the FBC CFB during enable/disable

One of the problems with the current code is that it frees the CFB and releases its drm_mm node as soon as we flip FBC's enable bit. This is bad because after we disable FBC the hardware may still use the CFB for the rest of the frame, so in theory we should only release the drm_mm node one frame

Re: [Intel-gfx] [PATCH v3 1/2] drm/i915: Tear down fbdev if initialization fails

On Thu, Nov 19, 2015 at 04:58:44PM +0100, Daniel Vetter wrote: > On Wed, Nov 18, 2015 at 04:29:51PM +0100, Lukas Wunner wrote: > > @@ -727,7 +730,8 @@ void intel_fbdev_fini(struct drm_device *dev) > > > > flush_work(_priv->fbdev_suspend_work); > > > > - async_synchronize_full(); > > +

Re: [Intel-gfx] [PATCH 1/2] drm/i915: take a power domain ref only when needed during HDMI detect

On Thu, Nov 19, 2015 at 11:01:49PM +0200, Imre Deak wrote: > On Thu, 2015-11-19 at 20:51 +, Chris Wilson wrote: > > On Thu, Nov 19, 2015 at 08:55:00PM +0200, Imre Deak wrote: > > > Suggested by Ville. > > > > Do you mind explaining why this is done at the hdmi level and not the > > gmbus

Re: [Intel-gfx] [PATCH 1/7] drm/i915: sseu: move sseu_dev_status to i915_drv.h

On Wed, Oct 21, 2015 at 06:40:31PM +0300, Imre Deak wrote: > The data in this struct is provided both by getting the > slice/subslice/eu features available on a given platform and the actual > runtime state of these same features which depends on the HW's current > power saving state. > > Atm

Re: [Intel-gfx] [PATCH 1/2] drm/i915: take a power domain ref only when needed during HDMI detect

On Thu, 2015-11-19 at 21:38 +, Chris Wilson wrote: > On Thu, Nov 19, 2015 at 11:01:49PM +0200, Imre Deak wrote: > > On Thu, 2015-11-19 at 20:51 +, Chris Wilson wrote: > > > On Thu, Nov 19, 2015 at 08:55:00PM +0200, Imre Deak wrote: > > > > Suggested by Ville. > > > > > > Do you mind

Re: [Intel-gfx] [PATCH 1/2] drm/i915: take a power domain ref only when needed during HDMI detect

On Thu, 2015-11-19 at 23:50 +0200, Imre Deak wrote: > On Thu, 2015-11-19 at 21:38 +, Chris Wilson wrote: > > On Thu, Nov 19, 2015 at 11:01:49PM +0200, Imre Deak wrote: > > > On Thu, 2015-11-19 at 20:51 +, Chris Wilson wrote: > > > > On Thu, Nov 19, 2015 at 08:55:00PM +0200, Imre Deak

Re: [Intel-gfx] [PATCH v3 1/2] drm/i915: Tear down fbdev if initialization fails

Hi Chris, On Thu, Nov 19, 2015 at 09:46:34PM +, Chris Wilson wrote: > On Thu, Nov 19, 2015 at 04:58:44PM +0100, Daniel Vetter wrote: > > On Wed, Nov 18, 2015 at 04:29:51PM +0100, Lukas Wunner wrote: > > > @@ -727,7 +730,8 @@ void intel_fbdev_fini(struct drm_device *dev) > > > > > >

Re: [Intel-gfx] [PATCH 2/7] drm/i915: sseu: use sseu_dev_info in device info

On Wed, Oct 21, 2015 at 06:40:32PM +0300, Imre Deak wrote: > Move all slice/subslice/eu related properties to the sseu_dev_info > struct. > > No functional change. > > Signed-off-by: Imre Deak Reviewed-by: Ben Widawsky > --- >

Re: [Intel-gfx] [PATCH 3/7] drm/i915: sseu: simplify debugfs status/info printing

On Wed, Oct 21, 2015 at 06:40:33PM +0300, Imre Deak wrote: > Signed-off-by: Imre Deak Reviewed-by: Ben Widawsky > --- > drivers/gpu/drm/i915/i915_debugfs.c | 55 > +++-- > 1 file changed, 29 insertions(+), 26

[Intel-gfx] [PATCH] drm/i915: Don't override output type for DDI HDMI

Currently a DDI port may register the DP hotplug handler even though it's used with HDMI, and the DP HPD handler overrides the encoder type forcibly to DP. This caused the inconsistency on a machine connected with a HDMI monitor; upon a hotplug event, the DDI port is suddenly switched to be

Re: [Intel-gfx] [Announcement] 2015-Q3 release of XenGT - a Mediated Graphics Passthrough Solution from Intel

On 19/11/2015 09:40, Gerd Hoffmann wrote: >> > But this code should be >> > minor to be maintained in libvirt. > As far I know libvirt only needs to discover those devices. If they > look like sr/iov devices in sysfs this might work without any changes to > libvirt. I don't think they will

[Intel-gfx] [PATCH 2/4] drm/i915: Fix possible null dereference in two debugfs functions

Found by static code analysis tool. Signed-off-by: Namrta Salonie Signed-off-by: Deepak S --- drivers/gpu/drm/i915/i915_debugfs.c | 19 +++ 1 file changed, 15 insertions(+), 4 deletions(-) diff --git

Re: [Intel-gfx] [PATCH i-g-t v2] lib/igt_core: Add kmsg capture and dumping

On Thu, Nov 19, 2015 at 12:35:23PM +0200, Joonas Lahtinen wrote: > +static void _igt_kmsg_capture_reset(void) > +{ > + if (igt_kmsg_capture_fd != -1) > + close(igt_kmsg_capture_fd); > + > + igt_kmsg_capture_fd = open("/dev/kmsg", > +O_RDONLY |

Re: [Intel-gfx] [PATCH 4/4] drm/i915: Fix potential NULL pointer de-reference in ggtt unbind.

On Thu, Nov 19, 2015 at 04:57:31PM +0530, Namrta Salonie wrote: > Found by static analysis tool. What bug? Please fix any callsite where this is an issue, rather than paper over the bug. -Chris -- Chris Wilson, Intel Open Source Technology Centre

Re: [Intel-gfx] [PATCH 1/2] drm/i915: PSR: Let's rely more on frontbuffer tracking.

On Thu, Nov 19, 2015 at 11:24:22AM +, Zanoni, Paulo R wrote: > Em Qui, 2015-11-19 às 13:16 +0200, Jani Nikula escreveu: > > On Wed, 18 Nov 2015, "Zanoni, Paulo R" > > wrote: > > > Em Qua, 2015-11-18 às 11:21 -0800, Rodrigo Vivi escreveu: > > > > Cc: Paulo Zanoni

[Intel-gfx] [PATCH i-g-t v4] lib/igt_core: Prefer CLOCK_MONOTONIC_RAW

CLOCK_MONOTONIC_RAW is not affected by NTP, so it should be THE clock used for timing execution of tests. When fetching either the starting or ending time of a test, show the time as -1.000s. v4: - Introduce time_valid macro (Chris) - Reduce amount of boilerplate code for calculating elapsed

[Intel-gfx] [PATCH 1/4] drm/i915: Fix for potential NULL pointer dereference at ctx access.

Added a null check for the context pointer, before de-referencing it. Found by static analysis tool. Signed-off-by: Namrta Salonie --- drivers/gpu/drm/i915/i915_gpu_error.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[Intel-gfx] [PATCH 0/4] Fix issues reported by static code analysis tool

The patchset is created to fix the issues static analysis tool has reported Namrta Salonie (4): drm/i915: Fix for potential NULL pointer dereference at ctx access. drm/i915: Fix possible null dereference in two debugfs functions drm/i915 : Fix to remove unnecsessary checks in postclose

[Intel-gfx] [PATCH 4/4] drm/i915: Fix potential NULL pointer de-reference in ggtt unbind.

Found by static analysis tool. Signed-off-by: Namrta Salonie --- drivers/gpu/drm/i915/i915_drv.h |5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 8afda45..705b1e6

[Intel-gfx] [PATCH 3/4] drm/i915 : Fix to remove unnecsessary checks in postclose function.

Found by static analysis tool. Signed-off-by: Namrta Salonie --- drivers/gpu/drm/i915/i915_dma.c |2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 2336af9..ac1bca6 100644 ---

Re: [Intel-gfx] [PATCH 2/4] drm/i915: Fix possible null dereference in two debugfs functions

On Thu, Nov 19, 2015 at 04:57:29PM +0530, Namrta Salonie wrote: > Found by static code analysis tool. > > Signed-off-by: Namrta Salonie > Signed-off-by: Deepak S > --- > drivers/gpu/drm/i915/i915_debugfs.c | 19 +++ > 1 file

Re: [Intel-gfx] [PATCH 1/4] drm/i915: Fix for potential NULL pointer dereference at ctx access.

On Thu, Nov 19, 2015 at 04:57:28PM +0530, Namrta Salonie wrote: > Added a null check for the context pointer, before de-referencing it. > Found by static analysis tool. False positive. -Chris -- Chris Wilson, Intel Open Source Technology Centre

Re: [Intel-gfx] [PATCH v3] drm/i915: Ensure associated VMAs are inactive when contexts are destroyed

On Thu, Nov 19, 2015 at 09:42:17AM +, Tvrtko Ursulin wrote: > > On 19/11/15 09:17, Daniel Vetter wrote: > >On Wed, Nov 18, 2015 at 05:18:30PM +, Tvrtko Ursulin wrote: > >> > >>On 17/11/15 17:56, Daniel Vetter wrote: > >>>On Tue, Nov 17, 2015 at 05:24:01PM +, Tvrtko Ursulin wrote: >

Re: [Intel-gfx] [PATCH v3] drm/i915: Ensure associated VMAs are inactive when contexts are destroyed

Hi, On 19/11/15 12:13, Daniel Vetter wrote: On Thu, Nov 19, 2015 at 09:42:17AM +, Tvrtko Ursulin wrote: On 19/11/15 09:17, Daniel Vetter wrote: On Wed, Nov 18, 2015 at 05:18:30PM +, Tvrtko Ursulin wrote: On 17/11/15 17:56, Daniel Vetter wrote: On Tue, Nov 17, 2015 at 05:24:01PM

Re: [Intel-gfx] [PATCH 1/2] drm/i915: PSR: Let's rely more on frontbuffer tracking.

Em Qui, 2015-11-19 às 13:16 +0200, Jani Nikula escreveu: > On Wed, 18 Nov 2015, "Zanoni, Paulo R" > wrote: > > Em Qua, 2015-11-18 às 11:21 -0800, Rodrigo Vivi escreveu: > > > Cc: Paulo Zanoni > > s/Cc/Reviewed-by/ > > I don't think our

Re: [Intel-gfx] [PATCH i-g-t v4] lib/igt_core: Prefer CLOCK_MONOTONIC_RAW

On Thu, Nov 19, 2015 at 01:00:07PM +0200, Joonas Lahtinen wrote: > CLOCK_MONOTONIC_RAW is not affected by NTP, so it should be THE clock > used for timing execution of tests. > > When fetching either the starting or ending time of a test, show the > time as -1.000s. > > v4: > - Introduce

Re: [Intel-gfx] [PATCH] Add Kabylake PCI IDs

On Thu, Nov 19, 2015 at 10:44:51AM +, Chris Wilson wrote: > On Wed, Nov 18, 2015 at 10:39:42AM -0800, Wayne Boyer wrote: > > Add the Kabylake PCI IDs based on the following patches. > > > > commit d97044b661d0d56b2a2ae9b2b95ab0b359b417dc > > Author: Deepak S > > Date:

Re: [Intel-gfx] [V2 PATCH 2/2] drm/i915: start adding dp mst audio

(Cc'ing Paulo for the audio power domain question) On Wed, 2015-11-11 at 13:33 +0800, libin.y...@linux.intel.com wrote: > From: Libin Yang > > This patch adds support for DP MST audio in i915. > > Enable audio codec when DP MST is enabled if has_audio flag is set. >

Re: [Intel-gfx] [PATCH 1/2] drm/i915: PSR: Let's rely more on frontbuffer tracking.

On Wed, 18 Nov 2015, "Zanoni, Paulo R" wrote: > Em Qua, 2015-11-18 às 11:21 -0800, Rodrigo Vivi escreveu: >> Cc: Paulo Zanoni > s/Cc/Reviewed-by/ I don't think our patchwork is quite smart enough for that yet, so for future reference, please

Re: [Intel-gfx] [PATCH 1/1] drm/i915/audio: apply SKL codec wake up patch to BXT

On Thu, 19 Nov 2015 10:09:01 +0100, Jani Nikula wrote: > > On Thu, 19 Nov 2015, Jani Nikula wrote: > > On Thu, 19 Nov 2015, han...@intel.com wrote: > >> From: "Lu, Han" > >> > >> Signed-off-by: Lu, Han > >> > >> diff --git

[Intel-gfx] [PATCH i-g-t v2] lib/igt_core: Add kmsg capture and dumping

Capture the output from /dev/kmsg during test execution independantly of other concurrent watchers like Piglit test runner. The captured output is analyzed and the test will fail if log messages with higher priority than LOG_NOTICE are emitted from any domain. Also adding igt_capture to

Re: [Intel-gfx] Write GFX_FLSH_CNT after updating GGTT entries

On Thu, Nov 19, 2015 at 06:20:23PM +0800, Zhi Wang wrote: > Hi Gurus: > I'm curious about the register GFX_FLSH_CNT(0x101008) in > i915_gem_gtt.c. Does these register exist in recently generations? After > digging into b-spec, it looks only BXT and CHV has this register. Does > the desktop

Re: [Intel-gfx] i-g-t/libdrm email tagging & patchwork

On Wed, 18 Nov 2015, Daniel Vetter wrote: > On Sun, Nov 08, 2015 at 12:31:36AM +, Damien Lespiau wrote: >> Hi all, >> >> I've added a feature to sort the patches sent to intel-gfx into 3 >> buckets: i915, intel-gpu-tools and libdrm. This sorting relies on >> tagging patches,

[Intel-gfx] [PATCH 10/12] drm/i915: Nuke fbc members from intel_crtc->atomic.

This leaves intel_crtc->atomic empty, so zap it as well. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/intel_display.c | 87 ++-- drivers/gpu/drm/i915/intel_drv.h | 16 --- 2 files changed, 33 insertions(+),

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