Re: [Intel-wired-lan] [PATCH v2] ice: Fix enabling SR-IOV with Xen

2024-05-08 Thread Sergey Temerkhanov
This patch makes sense since VFs need to be assigned resources (especially MSI-X interrupt count) before making these VFs visible, so that the kernel PCI enumeration code reads correct MSI-X interrupt count for the VFs. Regards, Sergey

Re: [Intel-wired-lan] [PATCH v2] ice: Fix enabling SR-IOV with Xen

2024-05-06 Thread Tony Nguyen
On 4/29/2024 5:49 AM, Ross Lagerwall wrote: When the PCI functions are created, Xen is informed about them and caches the number of MSI-X entries each function has. However, the number of MSI-X entries is not set until after the hardware has been configured and the VFs have been started.

Re: [Intel-wired-lan] [PATCH v2] ice: Fix enabling SR-IOV with Xen

2024-04-30 Thread Ross Lagerwall
On Mon, Apr 29, 2024 at 2:04 PM Paul Menzel wrote: > > Dear Ross, > > > Thank you for your patch. > > Am 29.04.24 um 14:49 schrieb Ross Lagerwall: > > When the PCI functions are created, Xen is informed about them and > > caches the number of MSI-X entries each function has. However, the > >

Re: [Intel-wired-lan] [PATCH v2] ice: Fix enabling SR-IOV with Xen

2024-04-29 Thread Paul Menzel
Dear Ross, Thank you for your patch. Am 29.04.24 um 14:49 schrieb Ross Lagerwall: When the PCI functions are created, Xen is informed about them and caches the number of MSI-X entries each function has. However, the number of MSI-X entries is not set until after the hardware has been

[Intel-wired-lan] [PATCH v2] ice: Fix enabling SR-IOV with Xen

2024-04-29 Thread Ross Lagerwall
When the PCI functions are created, Xen is informed about them and caches the number of MSI-X entries each function has. However, the number of MSI-X entries is not set until after the hardware has been configured and the VFs have been started. This prevents PCI-passthrough from working because