On Wed, Apr 13, 2022 at 01:46:06PM +0800, Chao Gao wrote:
> On Wed, Apr 13, 2022 at 06:59:58AM +0200, Christoph Hellwig wrote:
> >So for now I'd be happy with the one liner presented here, but
> >eventually the whole area could use an overhaul.
>
> Thanks. Do you want me to post a new version
On Wed, Apr 13, 2022 at 06:59:58AM +0200, Christoph Hellwig wrote:
>So for now I'd be happy with the one liner presented here, but
>eventually the whole area could use an overhaul.
Thanks. Do you want me to post a new version with the Fixes tag or you
will take care of it?
Fixes: 55897af63091
On Wed, Apr 13, 2022 at 09:02:02AM +0800, Chao Gao wrote:
> dma_direct_sync_single_for_cpu() also calls arch_sync_dma_for_cpu_all()
> and arch_dma_mark_clean() in some cases. if SWIOTLB does sync internally,
> should these two functions be called by SWIOTLB?
>
> Personally, it might be better if
To calculate num_pages, the size should be aligned with
"page size", determined by the tg value. Otherwise, its
following "while (iova < end)" might become an infinite
loop if unaligned size is slightly greater than 1 << tg.
Signed-off-by: Nicolin Chen
---
On Mon 11 Apr 04:50 CDT 2022, Rohit Agarwal wrote:
> Add smem node to support shared memory manager on SDX65 platform.
>
> Signed-off-by: Rohit Agarwal
> ---
> arch/arm/boot/dts/qcom-sdx65.dtsi | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi
>
On Tue, Apr 12, 2022 at 02:33:05PM +0100, Robin Murphy wrote:
>On 12/04/2022 12:38 pm, Chao Gao wrote:
>> When we looked into FIO performance with swiotlb enabled in VM, we found
>> swiotlb_bounce() is always called one more time than expected for each DMA
>> read request.
>>
>> It turns out that
> From: Lu Baolu
> Sent: Tuesday, April 12, 2022 8:53 PM
>
> >
> >> + if (!handle) {
> >> + ret = -ENOMEM;
> >> + goto out_put_ioas;
> >> + }
> >> +
> >> + /* The reference to ioas will be kept until domain free. */
> >> + domain = iommu_sva_alloc_domain(dev, ioas);
> >
> >
> From: Lu Baolu
> Sent: Tuesday, April 12, 2022 9:03 PM
>
> On 2022/4/12 15:37, Tian, Kevin wrote:
> >> From: Lu Baolu
> >> Sent: Tuesday, April 12, 2022 1:09 PM
> >> On 2022/4/12 11:15, Tian, Kevin wrote:
> From: Lu Baolu
> Sent: Sunday, April 10, 2022 6:25 PM
> >>>
>
>
> From: Jason Gunthorpe
> Sent: Tuesday, April 12, 2022 9:21 PM
>
> On Tue, Apr 12, 2022 at 09:13:27PM +0800, Lu Baolu wrote:
>
> > > > > btw as discussed in last version it is not necessarily to recalculate
> > > > > snoop control globally with this new approach. Will follow up to
> > > > >
Hi Jason,
On 4/12/22 10:22 PM, Jason Gunthorpe wrote:
> On Tue, Apr 12, 2022 at 10:13:32PM +0200, Eric Auger wrote:
>> Hi,
>>
>> On 3/18/22 6:27 PM, Jason Gunthorpe wrote:
>>> iommufd is the user API to control the IOMMU subsystem as it relates to
>>> managing IO page tables that point at user
On Tue, Apr 12, 2022 at 10:13:32PM +0200, Eric Auger wrote:
> Hi,
>
> On 3/18/22 6:27 PM, Jason Gunthorpe wrote:
> > iommufd is the user API to control the IOMMU subsystem as it relates to
> > managing IO page tables that point at user space memory.
> >
> > It takes over from
Hi,
On 3/18/22 6:27 PM, Jason Gunthorpe wrote:
> iommufd is the user API to control the IOMMU subsystem as it relates to
> managing IO page tables that point at user space memory.
>
> It takes over from drivers/vfio/vfio_iommu_type1.c (aka the VFIO
> container) which is the VFIO specific
On 13/04/2022 01.12, Sven Peter wrote:
> It's the same people anyway.
>
> Signed-off-by: Sven Peter
> ---
> MAINTAINERS | 10 ++
> 1 file changed, 2 insertions(+), 8 deletions(-)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index fd768d43e048..5af879de869c 100644
> --- a/MAINTAINERS
>
Acked-by: Alyssa Rosenzweig
On Tue, Apr 12, 2022 at 06:12:11PM +0200, Sven Peter wrote:
> It's the same people anyway.
>
> Signed-off-by: Sven Peter
> ---
> MAINTAINERS | 10 ++
> 1 file changed, 2 insertions(+), 8 deletions(-)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index
It's the same people anyway.
Signed-off-by: Sven Peter
---
MAINTAINERS | 10 ++
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index fd768d43e048..5af879de869c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1375,14 +1375,6 @@ L:
Hi, Fenghua
On 2022/4/12 下午9:41, Fenghua Yu wrote:
Hi, Zhangfei,
On Tue, Apr 12, 2022 at 03:04:09PM +0800, zhangfei@foxmail.com wrote:
On 2022/4/11 下午10:52, Dave Hansen wrote:
On 4/11/22 07:44, zhangfei@foxmail.com wrote:
On 2022/4/11 下午10:36, Dave Hansen wrote:
On 4/11/22 07:20,
On 4/12/22 08:10, Jean-Philippe Brucker wrote:
>> I wonder if the Intel and ARM IOMMU code differ in the way they keep
>> references to the mm, or if this affects Intel as well, but we just
>> haven't tested the code enough.
> The Arm code was written expecting the PASID to be freed on unbind(),
Hi,
On Tue, Apr 12, 2022 at 07:36:21AM -0700, Dave Hansen wrote:
> On 4/12/22 00:04, zhangfei@foxmail.com wrote:
> > master process quit, mmput -> mm_pasid_drop->ioasid_free
> > But this ignore driver's iommu_sva_unbind_device function,
> > iommu_sva_bind_device and iommu_sva_unbind_device
Hi Joerg,
On 4/4/2022 3:29 PM, Vasant Hegde via iommu wrote:
> Newer AMD systems can support multiple PCI segments, where each segment
> contains one or more IOMMU instances. However, an IOMMU instance can only
> support a single PCI segment.
>
Did you get a chance to look into this series?
On 4/12/22 06:41, Fenghua Yu wrote:
>> master process quit, mmput -> mm_pasid_drop->ioasid_free
>> But this ignore driver's iommu_sva_unbind_device function,
>> iommu_sva_bind_device and iommu_sva_unbind_device are not pair, So driver
>> does not know ioasid is freed.
>>
>> Any suggestion?
>
On 4/12/22 00:04, zhangfei@foxmail.com wrote:
> master process quit, mmput -> mm_pasid_drop->ioasid_free
> But this ignore driver's iommu_sva_unbind_device function,
> iommu_sva_bind_device and iommu_sva_unbind_device are not pair, So
> driver does not know ioasid is freed.
>
> Any
+ Shaik, Bhupesh
On Mon, 11 Apr 2022 at 11:50, Rohit Agarwal wrote:
>
> The SDHCI controller on SDX65 is based on MSM SDHCI v5 IP. Hence,
> document the compatible with "qcom,sdhci-msm-v5" as the fallback.
>
> Signed-off-by: Rohit Agarwal
As stated in a couple of other threads for patches
Hi, Zhangfei,
On Tue, Apr 12, 2022 at 03:04:09PM +0800, zhangfei@foxmail.com wrote:
>
>
> On 2022/4/11 下午10:52, Dave Hansen wrote:
> > On 4/11/22 07:44, zhangfei@foxmail.com wrote:
> > > On 2022/4/11 下午10:36, Dave Hansen wrote:
> > > > On 4/11/22 07:20, zhangfei@foxmail.com wrote:
>
On 12/04/2022 12:38 pm, Chao Gao wrote:
When we looked into FIO performance with swiotlb enabled in VM, we found
swiotlb_bounce() is always called one more time than expected for each DMA
read request.
It turns out that the bounce buffer is copied to original DMA buffer twice
after the
On Tue, Apr 12, 2022 at 07:38:05PM +0800, Chao Gao wrote:
>When we looked into FIO performance with swiotlb enabled in VM, we found
>swiotlb_bounce() is always called one more time than expected for each DMA
>read request.
>
>It turns out that the bounce buffer is copied to original DMA buffer
On Tue, Apr 12, 2022 at 09:13:27PM +0800, Lu Baolu wrote:
> > > > btw as discussed in last version it is not necessarily to recalculate
> > > > snoop control globally with this new approach. Will follow up to
> > > > clean it up after this series is merged.
> > > Agreed. But it also requires the
On 2022/4/12 15:44, Tian, Kevin wrote:
From: Lu Baolu
Sent: Saturday, April 9, 2022 8:51 PM
On 2022/4/8 16:16, Tian, Kevin wrote:
From: Jason Gunthorpe
Sent: Thursday, April 7, 2022 11:24 PM
IOMMU_CACHE means "normal DMA to this iommu_domain's IOVA
should
be cache
coherent" and is used by
On 2022/4/12 15:39, Tian, Kevin wrote:
From: Lu Baolu
Sent: Sunday, April 10, 2022 6:25 PM
@@ -898,6 +941,20 @@ int iommu_group_add_device(struct iommu_group
*group, struct device *dev)
list_add_tail(>list, >devices);
if (group->domain && !iommu_is_attach_deferred(dev))
On 2022/4/12 15:37, Tian, Kevin wrote:
From: Lu Baolu
Sent: Tuesday, April 12, 2022 1:09 PM
On 2022/4/12 11:15, Tian, Kevin wrote:
From: Lu Baolu
Sent: Sunday, April 10, 2022 6:25 PM
This adds a flag in the iommu_group struct to indicate an immutable
singleton group, and uses standard PCI
On 2022/4/12 15:19, Tian, Kevin wrote:
From: Lu Baolu
Sent: Sunday, April 10, 2022 6:25 PM
+struct iommu_sva *
+iommu_sva_bind_device(struct device *dev, struct mm_struct *mm, void
*drvdata)
+{
+ int ret = -EINVAL;
+ struct iommu_sva *handle;
+ struct iommu_domain *domain;
+
On 2022/4/12 16:39, John Garry wrote:
+static int hisi_ptt_alloc_trace_buf(struct hisi_ptt *hisi_ptt)
+{
+ struct hisi_ptt_trace_ctrl *ctrl = _ptt->trace_ctrl;
+ struct device *dev = _ptt->pdev->dev;
+ int i;
+
+ hisi_ptt->trace_ctrl.buf_index = 0;
On 2022/4/12 14:56, Tian, Kevin wrote:
From: Lu Baolu
Sent: Sunday, April 10, 2022 6:25 PM
Use below data structures for SVA implementation in the IOMMU core:
- struct iommu_sva_ioas
Represent the I/O address space shared with an application CPU address
space. This structure has a 1:1
On 2022/4/12 14:49, Tian, Kevin wrote:
From: Lu Baolu
Sent: Sunday, April 10, 2022 6:25 PM
Use below data structures for SVA implementation in the IOMMU core:
- struct iommu_sva_ioas
Represent the I/O address space shared with an application CPU address
space. This structure has a 1:1
On 11/04/2022 11:50, Rohit Agarwal wrote:
> The SDHCI controller on SDX65 is based on MSM SDHCI v5 IP. Hence,
> document the compatible with "qcom,sdhci-msm-v5" as the fallback.
>
> Signed-off-by: Rohit Agarwal
> ---
> Documentation/devicetree/bindings/mmc/sdhci-msm.txt | 1 +
> 1 file changed,
On 11/04/2022 11:50, Rohit Agarwal wrote:
> Add devicetree binding for Qualcomm SDX65 SMMU.
>
> Signed-off-by: Rohit Agarwal
> ---
> Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Krzysztof Kozlowski
Best regards,
Krzysztof
Hi Yi,
On 2022/4/12 14:34, Yi Liu wrote:
This adds a flag in the iommu_group struct to indicate an immutable
singleton group, and uses standard PCI bus topology, isolation
features,
and DMA alias quirks to set the flag. If the device came from DT,
assume
it is static and then the
When we looked into FIO performance with swiotlb enabled in VM, we found
swiotlb_bounce() is always called one more time than expected for each DMA
read request.
It turns out that the bounce buffer is copied to original DMA buffer twice
after the completion of a DMA request (one is done by in
+static int hisi_ptt_alloc_trace_buf(struct hisi_ptt *hisi_ptt)
+{
+ struct hisi_ptt_trace_ctrl *ctrl = _ptt->trace_ctrl;
+ struct device *dev = _ptt->pdev->dev;
+ int i;
+
+ hisi_ptt->trace_ctrl.buf_index = 0;
+
+ /* If the trace buffer has already been allocated, zero it. */
I
> From: Lu Baolu
> Sent: Saturday, April 9, 2022 8:51 PM
>
> On 2022/4/8 16:16, Tian, Kevin wrote:
> >> From: Jason Gunthorpe
> >> Sent: Thursday, April 7, 2022 11:24 PM
> >>
> >> IOMMU_CACHE means "normal DMA to this iommu_domain's IOVA
> should
> >> be cache
> >> coherent" and is used by the
On 2022/4/12 1:19, John Garry wrote:
> On 07/04/2022 13:58, Yicong Yang wrote:
>> From: Qi Liu
>>
>> 'perf record' and 'perf report --dump-raw-trace' supported in this
>> patch.
>>
>> Example usage:
>>
>> Output will contain raw PTT data and its textual representation, such
>> as:
>>
>> 0 0
> From: Lu Baolu
> Sent: Sunday, April 10, 2022 6:25 PM
> @@ -898,6 +941,20 @@ int iommu_group_add_device(struct iommu_group
> *group, struct device *dev)
> list_add_tail(>list, >devices);
> if (group->domain && !iommu_is_attach_deferred(dev))
> ret =
> From: Lu Baolu
> Sent: Tuesday, April 12, 2022 1:09 PM
> On 2022/4/12 11:15, Tian, Kevin wrote:
> >> From: Lu Baolu
> >> Sent: Sunday, April 10, 2022 6:25 PM
> >
> >>
> >> This adds a flag in the iommu_group struct to indicate an immutable
> >> singleton group, and uses standard PCI bus
Hi John,
Thanks for the comments! some questions replied below.
On 2022/4/12 1:02, John Garry wrote:
> On 07/04/2022 13:58, Yicong Yang wrote:
>> HiSilicon PCIe tune and trace device(PTT) is a PCIe Root Complex integrated
>> Endpoint(RCiEP) device, providing the capability to dynamically monitor
> From: Lu Baolu
> Sent: Sunday, April 10, 2022 6:25 PM
> +struct iommu_sva *
> +iommu_sva_bind_device(struct device *dev, struct mm_struct *mm, void
> *drvdata)
> +{
> + int ret = -EINVAL;
> + struct iommu_sva *handle;
> + struct iommu_domain *domain;
> + struct iommu_sva_ioas
On 2022/4/11 下午10:52, Dave Hansen wrote:
On 4/11/22 07:44, zhangfei@foxmail.com wrote:
On 2022/4/11 下午10:36, Dave Hansen wrote:
On 4/11/22 07:20, zhangfei@foxmail.com wrote:
Is there nothing before this call trace? Usually there will be at least
some warning text.
I added
> From: Lu Baolu
> Sent: Sunday, April 10, 2022 6:25 PM
>
> Use below data structures for SVA implementation in the IOMMU core:
>
> - struct iommu_sva_ioas
> Represent the I/O address space shared with an application CPU address
> space. This structure has a 1:1 relationship with an
> From: Lu Baolu
> Sent: Sunday, April 10, 2022 6:25 PM
>
> Use below data structures for SVA implementation in the IOMMU core:
>
> - struct iommu_sva_ioas
> Represent the I/O address space shared with an application CPU address
> space. This structure has a 1:1 relationship with an
Hi Baolu,
On 2022/4/12 13:08, Lu Baolu wrote:
Hi Kevin,
Thanks for your time.
On 2022/4/12 11:15, Tian, Kevin wrote:
From: Lu Baolu
Sent: Sunday, April 10, 2022 6:25 PM
Some features require that a single device must be immutably isolated,
even when hot plug is supported.
This reads
On Wed, Apr 06, 2022 at 08:25:32PM -0400, Konrad Rzeszutek Wilk wrote:
> > diff --git a/arch/powerpc/platforms/pseries/svm.c
> > b/arch/powerpc/platforms/pseries/svm.c
> > index c5228f4969eb2..3b4045d508ec8 100644
> > --- a/arch/powerpc/platforms/pseries/svm.c
> > +++
49 matches
Mail list logo
