On Fri, 8 Jul 2022 15:12:30 +0530, Sai Prakash Ranjan wrote:
> TLB sync timeouts can be due to various reasons such as TBU power down
> or pending TCU/TBU invalidation/sync and so on. Debugging these often
> require dumping of some implementation defined registers to know the
> status of TBU/TCU
; 1 file changed, 14 insertions(+), 41 deletions(-)
Thanks for the cleanup:
Acked-by: Will Deacon
Will
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On Fri, Jul 08, 2022 at 12:19:51PM +0200, Christoph Hellwig wrote:
> On Fri, Jul 08, 2022 at 11:12:45AM +0100, Will Deacon wrote:
> > Heads up, but I think this might collide (trivially?) with:
> >
> > https://lore.kernel.org/r/20220615101044.1972-1-shameerali.kolo
On Fri, Jul 08, 2022 at 10:06:15AM +0200, Christoph Hellwig wrote:
> All drivers that implement get_resv_regions just use
> generic_put_resv_regions to implement the put side. Remove the
> indirections and document the allocations constraints.
>
> Signed-off-by: Christoph Hellwig
> ---
>
On Tue, 14 Jun 2022 16:01:35 -0700, Emma Anholt wrote:
> Required for turning on per-process page tables for the GPU.
>
>
Applied to will (for-joerg/arm-smmu/updates), thanks!
[1/2] iommu: arm-smmu-impl: Add 8250 display compatible to the client list.
On Wed, Jul 06, 2022 at 01:03:44PM +0100, John Garry wrote:
> On 06/07/2022 13:00, Will Deacon wrote:
> > On Mon, Apr 04, 2022 at 07:27:10PM +0800, John Garry wrote:
> > > Function iommu_group_store_type() supports changing the default domain
> > > of an IOMMU group.
&
On Thu, Apr 07, 2022 at 03:52:53PM +0800, Leizhen (ThunderTown) wrote:
> On 2022/4/4 19:27, John Garry wrote:
> > Some low-level drivers may request DMA mappings whose IOVA length exceeds
> > that of the current rcache upper limit.
> >
> > This means that allocations for those IOVAs will never be
@huawei.com/
>
> Signed-off-by: John Garry
> ---
> drivers/iommu/iova.c | 20 ++--
> include/linux/iova.h | 3 +++
> 2 files changed, 13 insertions(+), 10 deletions(-)
Acked-by: Will Deacon
Will
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hn Garry
> ---
> drivers/iommu/iommu.c | 96 ---
> 1 file changed, 62 insertions(+), 34 deletions(-)
Acked-by: Will Deacon
Will
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On Thu, May 26, 2022 at 09:44:03AM +0530, Sai Prakash Ranjan wrote:
> TLB sync timeouts can be due to various reasons such as TBU power down
> or pending TCU/TBU invalidation/sync and so on. Debugging these often
> require dumping of some implementation defined registers to know the
> status of
or both patches:
Acked-by: Will Deacon
Joerg -- please can you pick these up for 5.20?
Thanks,
Will
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On Sun, Jun 12, 2022 at 11:22:13AM +0200, Luca Weiss wrote:
> Document the compatible used for IOMMU on the msm8953 SoC.
>
> Signed-off-by: Luca Weiss
> ---
> Changes from v1:
> - new patch
>
> Documentation/devicetree/bindings/iommu/qcom,iommu.txt | 1 +
> 1 file changed, 1 insertion(+)
>
>
On Thu, Jun 30, 2022 at 09:39:59AM +0300, Xenia Ragiadakou wrote:
> The expression 1 << 31 results in undefined behaviour because the type of
> integer constant 1 is (signed) int and the result of shifting 1 by 31 bits
> is not representable in the (signed) int type.
>
> Change the type of 1 to
Hi,
For some reason, this series has landed in my spam folder so apologies
for the delay :/
On Sat, Jun 11, 2022 at 06:26:53PM +0800, yf.w...@mediatek.com wrote:
> From: Yunfei Wang
>
> Single memory zone feature will remove ZONE_DMA32 and ZONE_DMA and
> cause pgtable PA size larger than
gt; ---
> drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 28 +++--
> 1 file changed, 15 insertions(+), 13 deletions(-)
Acked-by: Will Deacon
Will
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On Tue, May 31, 2022 at 09:15:22AM -0700, Rob Clark wrote:
> On Tue, May 31, 2022 at 8:46 AM Will Deacon wrote:
> >
> > On Fri, May 27, 2022 at 11:28:56PM +0200, Konrad Dybcio wrote:
> > > From: AngeloGioacchino Del Regno
> > >
> > >
> >
On Fri, May 27, 2022 at 11:28:57PM +0200, Konrad Dybcio wrote:
> From: AngeloGioacchino Del Regno
>
> As also stated in the arm-smmu driver, we must write the TCR before
> writing the TTBRs, since the TCR determines the access behavior of
> some fields.
Where is this stated in the arm-smmu
On Fri, May 27, 2022 at 11:28:56PM +0200, Konrad Dybcio wrote:
> From: AngeloGioacchino Del Regno
>
> As specified in this driver, the context banks are 0x1000 apart.
> Problem is that sometimes the context number (our asid) does not
> match this logic and we end up using the wrong one: this
On Fri, May 20, 2022 at 12:02:23PM +0100, Robin Murphy wrote:
> On 2022-05-10 17:55, Jason Gunthorpe via iommu wrote:
> > This control causes the ARM SMMU drivers to choose a stage 2
> > implementation for the IO pagetable (vs the stage 1 usual default),
> > however this choice has no visible
On Mon, May 16, 2022 at 11:52:54AM +0300, cyn...@kapsi.fi wrote:
> From: Mikko Perttunen
>
> Set itself as the IOMMU for the host1x context device bus, containing
> "dummy" devices used for Host1x context isolation.
>
> Signed-off-by: Mikko Perttunen
> ---
>
Hi Joerg,
Please pull these Arm SMMU updates for 5.19. The bulk of it is just adding
new device-tree compatible strings for the existing drivers, but there
are some non-critical fixes in here as well. Please see the tag for more
details.
I used the previous fixes pull as a base for this so that
On Tue, 10 May 2022 09:38:58 +0100, Robin Murphy wrote:
> When using the legacy "mmu-masters" DT binding, we reject DMA domains
> since we have no guarantee of driver probe order and thus can't rely on
> client drivers getting the correct DMA ops. However, we can do better
> than fall back to the
iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 16
> 1 file changed, 16 insertions(+)
I still don't like this being part of the SMMU driver, but given that
(a) Robin doesn't seem to agree with the objection and (b) you've been
refreshing the patch series:
Acked-by: Will Deacon
If you
On Mon, 25 Apr 2022 19:41:36 +0800, Yang Yingliang wrote:
> It will cause null-ptr-deref when using 'res', if platform_get_resource()
> returns NULL, so move using 'res' after devm_ioremap_resource() that
> will check it to avoid null-ptr-deref.
> And use devm_platform_get_and_ioremap_resource()
On Fri, 29 Apr 2022 10:22:40 +0200, Thierry Reding wrote:
> From: Thierry Reding
>
> Hi Joerg,
>
> this is essentially a resend of v2 with a Acked-by:s from Robin and Will
> added. These have been on the list for quite a while now, but apparently
> there was a misunderstanding, so neither you
On Mon, 25 Apr 2022 19:45:25 +0800, Yang Yingliang wrote:
> It will cause null-ptr-deref if platform_get_resource() returns NULL,
> we need check the return value.
>
>
Applied to will (for-joerg/arm-smmu/updates), thanks!
[1/1] iommu/arm-smmu-v3: check return value after calling
On Mon, 11 Apr 2022 15:20:08 +0530, Rohit Agarwal wrote:
> This series adds devicetree nodes for SDX65. It adds reserved memory
> nodes, SDHCI, smmu and tcsr mutex support.
>
> Changes from v1:
> - Addressed Mani's Comments and made necessary.
> - Rebased on top of v5.18-rc2.
>
> [...]
On Tue, 26 Apr 2022 14:04:45 +0100, Jean-Philippe Brucker wrote:
> We currently call arm64_mm_context_put() without holding a reference to
> the mm, which can result in use-after-free. Call mmgrab()/mmdrop() to
> ensure the mm only gets freed after we unpinned the ASID.
>
>
Applied to will
On Tue, 3 May 2022 09:34:27 -0700, Bjorn Andersson wrote:
> This adds the compatible for the Qualcomm SC8280XP platform and associate the
> Qualcomm impl in the ARM SMMU driver to it.
>
> Bjorn Andersson (2):
> dt-bindings: arm-smmu: Add compatible for Qualcomm SC8280XP
> iommu/arm-smmu-qcom:
On Thu, May 05, 2022 at 04:15:29PM +0200, Thierry Reding wrote:
> On Fri, Apr 29, 2022 at 10:22:40AM +0200, Thierry Reding wrote:
> > From: Thierry Reding
> >
> > Hi Joerg,
> >
> > this is essentially a resend of v2 with a Acked-by:s from Robin and Will
> > added. These have been on the list
Hi Joerg,
Unusually, we've got some SMMU driver fixes this time around. Summary in
the tag -- please can you pull these for 5.18?
Cheers,
Will
--->8
The following changes since commit 3123109284176b1532874591f7c81f3837bbdc17:
Linux 5.18-rc1 (2022-04-03 14:08:21 -0700)
are available in the
On Thu, 21 Apr 2022 13:45:04 +0530, Ashish Mhetre wrote:
> Tegra194 and Tegra234 SoCs have the erratum that causes walk cache
> entries to not be invalidated correctly. The problem is that the walk
> cache index generated for IOVA is not same across translation and
> invalidation requests. This is
On Wed, Apr 20, 2022 at 05:05:03PM +0100, Robin Murphy wrote:
> On 2022-04-19 15:40, Will Deacon wrote:
> > On Thu, Apr 14, 2022 at 01:42:33PM +0100, Robin Murphy wrote:
> > > Stop calling bus_set_iommu() since it's now unnecessary. With device
> > > probes now replay
On Tue, 19 Apr 2022 14:01:58 -0700, Nicolin Chen wrote:
> The arm_smmu_mm_invalidate_range function is designed to be called
> by mm core for Shared Virtual Addressing purpose between IOMMU and
> CPU MMU. However, the ways of two subsystems defining their "end"
> addresses are slightly different.
> 1 file changed, 2 insertions(+), 51 deletions(-)
Acked-by: Will Deacon
Will
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ou tested this!
> Signed-off-by: Robin Murphy
> ---
> drivers/iommu/arm/arm-smmu/arm-smmu.c | 84 +--
> 1 file changed, 2 insertions(+), 82 deletions(-)
Assuming it works,
Acked-by: Will Deacon
Will
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On Tue, Mar 08, 2022 at 04:59:05PM +0100, Thierry Reding wrote:
> On Wed, Feb 16, 2022 at 02:25:20PM +0100, Thierry Reding wrote:
> > On Thu, Dec 09, 2021 at 05:35:57PM +0100, Thierry Reding wrote:
> > > From: Thierry Reding
> > >
> > > On NVIDIA SoC's the ARM SMMU needs to interact with the
Hi Joerg,
Please pull this handful of Arm SMMU updates for 5.18. Summary in the tag.
Cheers,
Will
--->8
The following changes since commit 26291c54e111ff6ba87a164d85d4a4e134b7315c:
Linux 5.17-rc2 (2022-01-30 15:37:07 +0200)
are available in the Git repository at:
On Tue, Feb 15, 2022 at 01:30:26PM +, Robin Murphy wrote:
> On 2022-02-15 13:00, Will Deacon wrote:
> > On Mon, Feb 14, 2022 at 08:55:20PM +0800, Yicong Yang wrote:
> > > On 2022/1/24 21:11, Yicong Yang wrote:
> > > > The DMA of HiSilicon PTT device can only work
On Mon, Feb 14, 2022 at 08:55:20PM +0800, Yicong Yang wrote:
> On 2022/1/24 21:11, Yicong Yang wrote:
> > The DMA of HiSilicon PTT device can only work with identical
> > mapping. So add a quirk for the device to force the domain
> > passthrough.
> >
> > Signed-off-by: Yicong Yang
> > ---
> >
On Wed, 19 Jan 2022 07:07:54 +, Zhou Guanghui wrote:
> During event processing, events are read from the event queue one
> by one until the queue is empty.If the master device continuously
> requests address access at the same time and the SMMU generates
> events, the cyclic processing of the
On Wed, 5 Jan 2022 10:16:19 +, Miaoqian Lin wrote:
> If the probe fails, we should use pm_runtime_disable() to balance
> pm_runtime_enable().
> Add missing pm_runtime_disable() for error handling.
>
>
Applied to will (for-joerg/arm-smmu/updates), thanks!
[1/1] iommu/arm-smmu: Add missing
On Mon, 7 Feb 2022 23:50:48 +0100, Christophe JAILLET wrote:
> kmalloc_array()/kcalloc() should be used to avoid potential overflow when
> a multiplication is needed to compute the size of the requested memory.
>
> So turn a devm_kzalloc()+explicit size computation into an equivalent
>
On Tue, Feb 08, 2022 at 03:28:50PM +, Robin Murphy wrote:
> On 2022-02-08 15:19, Will Deacon wrote:
> > On Thu, Dec 23, 2021 at 02:14:35PM +, Robin Murphy wrote:
> > > On 2021-12-23 13:00, Lad Prabhakar wrote:
> > > > platform_get_resource(pdev, IORESO
On Thu, Dec 23, 2021 at 02:14:35PM +, Robin Murphy wrote:
> On 2021-12-23 13:00, Lad Prabhakar wrote:
> > platform_get_resource(pdev, IORESOURCE_IRQ, ..) relies on static
> > allocation of IRQ resources in DT core code, this causes an issue
> > when using hierarchical interrupt domains using
Hi Joerg,
Please pull these Arm SMMU updates for 5.17.
Once again, there's not a lot here. In fact, it's mostly a combination
of non-critical fixes and DT compatible string additions. Summary in
the tag.
Cheers,
Will
--->8
The following changes since commit
On Tue, 7 Dec 2021 14:32:48 +0800, Zhou Wang wrote:
> The commit f115f3c0d5d8 ("iommu/arm-smmu-v3: Decrease the queue size of
> evtq and priq") decreases evtq and priq, which may lead evtq/priq to be
> full with fault events, e.g HiSilicon ZIP/SEC/HPRE have maximum 1024 queues
> in one device,
On Tue, Oct 05, 2021 at 08:16:25AM -0700, Rob Clark wrote:
> From: Rob Clark
>
> Add an io-pgtable method to retrieve the raw PTEs that would be
> traversed for a given iova access.
>
> Signed-off-by: Rob Clark
> ---
> drivers/iommu/io-pgtable-arm.c | 40 +++---
>
On Tue, 7 Dec 2021 19:33:15 +0800, yf.w...@mediatek.com wrote:
> From: Yunfei Wang
>
> In __arm_v7s_alloc_table function:
> iommu call kmem_cache_alloc to allocate page table, this function
> allocate memory may fail, when kmem_cache_alloc fails to allocate
> table, call virt_to_phys will be
On Wed, 1 Dec 2021 13:09:41 +0530, Vinod Koul wrote:
> This adds the binding and support for IOMMU found in SM8450 SoC
>
> Vinod Koul (2):
> dt-bindings: arm-smmu: Add compatible for SM8450 SoC
> iommu: arm-smmu-impl: Add SM8450 qcom iommu implementation
>
>
On Mon, 8 Nov 2021 09:17:23 -0800, Rob Clark wrote:
> From: Rob Clark
>
> It is a 64b register, lets not lose the upper bits.
>
>
Applied to will (for-joerg/arm-smmu/updates), thanks!
[1/1] iommu/arm-smmu-qcom: Fix TTBR0 read
https://git.kernel.org/will/c/c31112fbd407
Cheers,
--
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On Sat, 4 Dec 2021 23:33:01 +0100, Rikard Falkeborn wrote:
> The only usage of arm_smmu_mmu_notifier_ops is to assign its address to
> the ops field in the mmu_notifier struct, which is a pointer to const
> struct mmu_notifier_ops. Make it const to allow the compiler to put it
> in read-only
On Thu, 21 Oct 2021 01:17:00 +0200, David Heidelberg wrote:
> Add missing compatible for the SDX55 SoC.
>
>
Applied to will (for-joerg/arm-smmu/updates), thanks!
[1/1] dt-bindings: arm-smmu: Add compatible for the SDX55 SoC
https://git.kernel.org/will/c/ae377d342006
Cheers,
--
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On Tue, Dec 07, 2021 at 02:32:48PM +0800, Zhou Wang wrote:
> The commit f115f3c0d5d8 ("iommu/arm-smmu-v3: Decrease the queue size of
> evtq and priq") decreases evtq and priq, which may lead evtq/priq to be
> full with fault events, e.g HiSilicon ZIP/SEC/HPRE have maximum 1024 queues
> in one
On Wed, 17 Nov 2021 14:48:42 +, Jean-Philippe Brucker wrote:
> Add devicetree binding for the SMMUv3 PMU, called Performance Monitoring
> Counter Group (PMCG) in the spec. Each SMMUv3 implementation can have
> multiple independent PMCGs, for example one for the Translation Control
> Unit (TCU)
mpl;
>
> - if (of_device_is_compatible(np, "nvidia,tegra194-smmu") ||
> + if (of_device_is_compatible(np, "nvidia,tegra234-smmu") ||
> + of_device_is_compatible(np, "nvidia,tegra194-smmu") ||
> of_device_is
On Tue, Dec 07, 2021 at 10:47:22AM +0800, yf.w...@mediatek.com wrote:
> From: Yunfei Wang
>
> In __arm_v7s_alloc_table function:
> iommu call kmem_cache_alloc to allocate page table, this function
> allocate memory may fail, when kmem_cache_alloc fails to allocate
> table, call virt_to_phys will
On Mon, Nov 29, 2021 at 02:54:18PM +, Robin Murphy wrote:
> On 2021-11-29 14:42, Thomas Gleixner wrote:
> > On Mon, Nov 29 2021 at 13:13, Robin Murphy wrote:
> > > On 2021-11-29 10:55, Will Deacon wrote:
> > > > > - }
> > > > > + smm
Hi Thomas,
On Sat, Nov 27, 2021 at 02:20:59AM +0100, Thomas Gleixner wrote:
> Let the core code fiddle with the MSI descriptor retrieval.
>
> Signed-off-by: Thomas Gleixner
> ---
> drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 19 +++
> 1 file changed, 3 insertions(+), 16
Hi Joerg,
Please pull this tiny batch of Arm SMMU updates for 5.16. It's dominated
by compatible string additions for Qualcomm SMMUv2 implementations, but
there's a bit of cleanup on the SMMUv3 command-submission side as well.
Cheers,
Will
--->8
The following changes since commit
On Wed, Oct 13, 2021 at 09:31:40PM +0200, Arnd Bergmann wrote:
> On Wed, Oct 13, 2021 at 6:20 PM Will Deacon wrote:
> > On Wed, Oct 13, 2021 at 10:33:55AM +0200, Arnd Bergmann wrote:
> > > On Wed, Oct 13, 2021 at 9:58 AM Will Deacon wrote:
> > > > On Tue, Oct 12,
Hi Arnd,
On Wed, Oct 13, 2021 at 10:33:55AM +0200, Arnd Bergmann wrote:
> On Wed, Oct 13, 2021 at 9:58 AM Will Deacon wrote:
> > On Tue, Oct 12, 2021 at 05:18:00PM +0200, Arnd Bergmann wrote:
> > > From: Arnd Bergmann
> > >
> > > My previous bugfix ended
RM SMMU, this needs to be built into the SMMU driver.
> +
FWIW, I prefer this solution over changing the driver code, so:
Acked-by: Will Deacon
I assume you'll be getting this fixed for 5.15?
Cheers,
Will
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On Wed, Aug 18, 2021 at 04:04:52PM +0800, Zhen Lei wrote:
> Although the parameter 'cmd' is always passed by a local array variable,
> and only this function modifies it, the compiler does not know this. The
> compiler almost always reads the value of cmd[i] from memory rather than
> directly
On Tue, 17 Aug 2021 19:34:11 +0800, Zhen Lei wrote:
> Pre-zeroing the batched commands structure is inefficient, as individual
> commands are zeroed later in arm_smmu_cmdq_build_cmd(). Therefore, only
> the member 'num' needs to be initialized to 0.
>
>
Applied to will
On Wed, 18 Aug 2021 16:04:50 +0800, Zhen Lei wrote:
> v1 --> v2:
> 1. Add patch 1, Properly handle the return value of arm_smmu_cmdq_build_cmd()
> 2. Remove arm_smmu_cmdq_copy_cmd(). In addition, when build command fails,
> out_cmd is not filled.
>
>
> Zhen Lei (2):
> iommu/arm-smmu-v3:
On Fri, 20 Aug 2021 22:29:04 +0200, Konrad Dybcio wrote:
> Add the SoC specific compatible for SM6350 implementing
> arm,mmu-500.
>
>
Applied to will (for-joerg/arm-smmu/updates), thanks!
[1/2] dt-bindings: arm-smmu: Add compatible for SM6350 SoC
On Fri, 1 Oct 2021 16:00:31 +0200, Loic Poulain wrote:
>
Applied to will (for-joerg/arm-smmu/updates), thanks!
[1/2] iommu: arm-smmu-qcom: Add compatible for qcm2290
https://git.kernel.org/will/c/756a622c8f06
[2/2] dt-bindings: arm-smmu: Add qcm2290 compatible strings
On Fri, Sep 24, 2021 at 06:01:52PM +0800, John Garry wrote:
> The IOVA domain structure is a bit overloaded, holding:
> - IOVA tree management
> - FQ control
> - IOVA rcache memories
>
> Indeed only a couple of IOVA users use the rcache, and only dma-iommu.c
> uses the FQ feature.
>
> This
On Fri, Sep 24, 2021 at 06:01:57PM +0800, John Garry wrote:
> A similar crash to the following could be observed if initial CPU rcache
> magazine allocations fail in init_iova_rcaches():
>
> Unable to handle kernel NULL pointer dereference at virtual address
>
> Mem abort info:
gt; ---
> drivers/iommu/dma-iommu.c| 8
> drivers/iommu/iova.c | 9 +
> drivers/vdpa/vdpa_user/iova_domain.c | 8
> 3 files changed, 9 insertions(+), 16 deletions(-)
Acked-by: Will Deacon
Will
On Thu, 30 Sep 2021 04:30:37 +0300, Mike Rapoport wrote:
> From: Mike Rapoport
>
> Hi,
>
> This is a new attempt to drop HAVE_ARCH_PFN_VALID on arm64 and start using
> the generic implementation of pfn_valid().
>
> [...]
Applied to arm64 (for-next/pfn-valid), thanks!
[1/2] dma-mapping:
On Mon, Sep 27, 2021 at 05:22:13PM +0200, Arnd Bergmann wrote:
> From: Arnd Bergmann
>
> Now that SCM can be a loadable module, we have to add another
> dependency to avoid link failures when ipa or adreno-gpu are
> built-in:
>
> aarch64-linux-ld: drivers/net/ipa/ipa_main.o: in function
;& OF_RESERVED_MEM && SWIOTLB
> help
> This enables support for restricted DMA pools which provide a level of
> DMA memory protection on systems with limited hardware protection
Acked-by: Will Deacon
Will
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pinlock in alloc_iova() and free_iova()
> > during IOVA allocation.
> >
> > Signed-off-by: Xie Yongji
>
>
> This needs ack from iommu maintainers. Guys?
Looks fine to me:
Acked-by: Will Deacon
Will
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On Mon, Aug 23, 2021 at 06:47:19AM -0400, Konrad Rzeszutek Wilk wrote:
> On Mon, Aug 16, 2021 at 02:26:15PM +0100, Will Deacon wrote:
> > Hi all,
> >
> > This is v2 of the patch I previously posted here:
> >
> > https://lore.kernel.org/r/20210805094736.902-1
return ERR_PTR(-EINVAL);
> + }
Urgh, I should really have spotted that in review. Thanks:
Acked-by: Will Deacon
Joerg -- please can you throw this on top?
Will
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On Wed, Aug 18, 2021 at 02:08:25PM +0200, Joerg Roedel wrote:
> On Fri, Aug 13, 2021 at 05:47:35PM +0100, Will Deacon wrote:
> > This applies cleanly against iommu/next, but I suspect it will conflict
> > with Robin's series on the list. Please shout if you need anything from
Hellwig
Cc: Robin Murphy
Suggested-by: Rob Herring
Link:
https://lore.kernel.org/r/CAL_JsqJ7ROWWJX84x2kEex9NQ8G+2=ybrunoobx+j8bjzzs...@mail.gmail.com
Signed-off-by: Will Deacon
---
drivers/of/address.c| 33 -
drivers/of/device.c | 34
nd instead either returns early if CONFIG_DMA_RESTRICTED_POOL=n
or emits a diagnostic if the reserved DMA pool fails to initialise.
Cc: Claire Chang
Cc: Konrad Rzeszutek Wilk
Cc: Christoph Hellwig
Cc: Rob Herring
Cc: Robin Murphy
Signed-off-by: Will Deacon
---
drivers/of/device.c | 13 ++
devel/for-linus-5.15 branch in swiotlb.git
Cheers,
Will
Cc: Claire Chang
Cc: Konrad Rzeszutek Wilk
Cc: Christoph Hellwig
Cc: Rob Herring
Cc: Robin Murphy
--->8
Will Deacon (2):
of: Move of_dma_set_restricted_buffer() into device.c
of: restricted dma: Don't fail device probe on rmem i
On Mon, Aug 16, 2021 at 03:47:58PM +0800, Leizhen (ThunderTown) wrote:
>
>
> On 2021/8/16 15:24, John Garry wrote:
> >> In addition, I find that function arm_smmu_cmdq_build_cmd() can also be
> >> optimized
> >> slightly, three useless instructions can be reduced.
> >
> > I think that you
On Wed, 11 Aug 2021 19:48:48 +0800, Zhen Lei wrote:
> RFC --> v1
> 1. Resend the patches for ECMDQ preparation and remove the patches for ECMDQ
> implementation.
> 2. Patch 2 is modified. Other patches remain unchanged.
>1) Add static helper __arm_smmu_cmdq_issue_cmd(), and make
>
On Wed, 11 Aug 2021 21:34:26 +0530, Sai Prakash Ranjan wrote:
> Currently for iommu_unmap() of large scatter-gather list with page size
> elements, the majority of time is spent in flushing of partial walks in
> __arm_lpae_unmap() which is a VA based TLB invalidation invalidating
> page-by-page on
On Wed, 11 Aug 2021 23:49:26 +0800, John Garry wrote:
> Pre-zeroing the batched commands structure is inefficient, as individual
> commands are zeroed later in arm_smmu_cmdq_build_cmd(). The size is quite
> large and commonly most commands won't even be used:
>
> struct arm_smmu_cmdq_batch
On Wed, Aug 11, 2021 at 11:31:08AM +0100, John Garry wrote:
> > > > > Obviously, inserting as many commands at a time as possible can
> > > > > reduce the
> > > > > number of times the mutex contention participates, thereby improving
> > > > > the
> > > > > overall performance. At least it
On Wed, Aug 11, 2021 at 11:37:25AM +0530, Sai Prakash Ranjan wrote:
> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c
> b/drivers/iommu/arm/arm-smmu/arm-smmu.c
> index f7da8953afbe..3904b598e0f9 100644
> --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c
> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c
On Wed, Aug 11, 2021 at 10:16:39AM +0800, Leizhen (ThunderTown) wrote:
>
>
> On 2021/8/11 2:24, Will Deacon wrote:
> > On Sat, Jun 26, 2021 at 07:01:24PM +0800, Zhen Lei wrote:
> >> The obvious key to the performance optimization of commit 587e6c10a7ce
> >> (&quo
On Tue, 10 Aug 2021 12:18:08 +0530, Sai Prakash Ranjan wrote:
> Some clocks for SMMU can have parent as XO such as gpu_cc_hub_cx_int_clk
> of GPU SMMU in QTI SC7280 SoC and in order to enter deep sleep states in
> such cases, we would need to drop the XO clock vote in unprepare call and
> this
On Tue, 10 Aug 2021 10:13:59 +0530, Ashish Mhetre wrote:
> When two devices with same SID are getting probed concurrently through
> iommu_probe_device(), the iommu_group and iommu_domain are allocated more
> than once because they are not protected for concurrency. This is leading
> to context
On Sat, Jun 26, 2021 at 07:01:22PM +0800, Zhen Lei wrote:
> SMMU v3.3 added a new feature, which is Enhanced Command queue interface
> for reducing contention when submitting Commands to the SMMU, in this
> patch set, ECMDQ is the abbreviation of Enhanced Command Queue.
>
> When the hardware
On Sat, Jun 26, 2021 at 07:01:24PM +0800, Zhen Lei wrote:
> The obvious key to the performance optimization of commit 587e6c10a7ce
> ("iommu/arm-smmu-v3: Reduce contention during command-queue insertion") is
> to allow multiple cores to insert commands in parallel after a brief mutex
> contention.
On Tue, Aug 03, 2021 at 11:09:17AM +0530, Sai Prakash Ranjan wrote:
> On 2021-08-02 21:13, Will Deacon wrote:
> > On Wed, Jun 23, 2021 at 07:12:01PM +0530, Sai Prakash Ranjan wrote:
> > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c
> > > b/drivers/iommu/arm/arm-
On Mon, Aug 09, 2021 at 11:17:40PM +0530, Sai Prakash Ranjan wrote:
> On 2021-08-09 23:10, Will Deacon wrote:
> > On Mon, Aug 09, 2021 at 10:18:21AM -0700, Rob Clark wrote:
> > > On Mon, Aug 9, 2021 at 10:05 AM Will Deacon wrote:
> > > > On Mon, Aug 09, 2021 at 09:
On Mon, Aug 09, 2021 at 10:18:21AM -0700, Rob Clark wrote:
> On Mon, Aug 9, 2021 at 10:05 AM Will Deacon wrote:
> >
> > On Mon, Aug 09, 2021 at 09:57:08AM -0700, Rob Clark wrote:
> > > On Mon, Aug 9, 2021 at 7:56 AM Will Deacon wrote:
> > > > On Mon, Aug 02,
On Mon, Aug 09, 2021 at 09:57:08AM -0700, Rob Clark wrote:
> On Mon, Aug 9, 2021 at 7:56 AM Will Deacon wrote:
> > On Mon, Aug 02, 2021 at 06:36:04PM -0700, Rob Clark wrote:
> > > On Mon, Aug 2, 2021 at 8:14 AM Will Deacon wrote:
> > > > On Mon, Aug 02, 2021 at 08:
On Mon, Aug 02, 2021 at 06:36:04PM -0700, Rob Clark wrote:
> On Mon, Aug 2, 2021 at 8:14 AM Will Deacon wrote:
> >
> > On Mon, Aug 02, 2021 at 08:08:07AM -0700, Rob Clark wrote:
> > > On Mon, Aug 2, 2021 at 3:55 AM Will Deacon wrote:
> > > >
> > > &g
On Mon, Aug 02, 2021 at 04:46:37PM +0100, Robin Murphy wrote:
> On 2021-08-02 16:16, Will Deacon wrote:
> > On Fri, Jun 18, 2021 at 02:00:35AM +0530, Ashish Mhetre wrote:
> > > Multiple iommu domains and iommu groups are getting created for the
> > > devices
> > &
On Wed, Aug 04, 2021 at 06:15:52PM +0100, Robin Murphy wrote:
> Factor out flush queue setup from the initial domain init so that we
> can potentially trigger it from sysfs later on in a domain's lifetime.
>
> Reviewed-by: Lu Baolu
> Reviewed-by: John Garry
> Signed-off-by: Robin Murphy
> ---
On Wed, Aug 04, 2021 at 06:15:53PM +0100, Robin Murphy wrote:
> Allocating and enabling a flush queue is in fact something we can
> reasonably do while a DMA domain is active, without having to rebuild it
> from scratch. Thus we can allow a strict -> non-strict transition from
> sysfs without
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