Hi all,
I am curious memory mapping/unmapping performance.
Are there any applications that stress the memory mapping and unmapping utility?
Thanks a lot!
Yuxin
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Yes, I am not interested in L4Linux.
So there is no other example code to use network in L4Re.
Is this correct?
Thanks
Yuxin
On Wed, Nov 4, 2015 at 7:31 AM, Adam Lackorzynski
<a...@os.inf.tu-dresden.de> wrote:
> Hi,
>
> On Tue Nov 03, 2015 at 08:00:53 +0800, Yuxin Ren wrote:
Hi,
I have a few questions about network stack in Fiasco/L4Re.
Is network stack implemented in the kernel or user level?
If in user level, are different protocols (IP/TCP) implemented in a
single server or different servers?
If in different servers, how do they communicate with each other?
Is
<matthias.la...@kernkonzept.com> wrote:
> Hi,
>
> On 10/26/2015 01:55 AM, Yuxin Ren wrote:
>> Hi,
>>
>> Are there any relative complex and non-trivial applications on top of
>> Fiasco and l4Re?
>> If so, where can I get the source code?
>
> The questi
On Thu, Jul 16, 2015 at 7:31 AM, Qing Wei wq_i...@163.com wrote:
Hi,
I am a beginner to L4, and very interested in it. I think it is great in
terms of its minimality and security. However, I have some questions
about it,
(1) How is its performance compared to other monolithic kernel,
say,
this cxx library and libstdc++, libsupc++?
Thanks a lot!
Yuxin
On Mon, Jun 29, 2015 at 5:51 PM, Adam Lackorzynski
a...@os.inf.tu-dresden.de wrote:
Hi,
On Mon Jun 29, 2015 at 12:25:42 -0400, Yuxin Ren wrote:
For libstdc++ and libsupc++, I can their source code in
l4/pkg/libstdc++-v3/contrib
, 2015 at 19:01:21 -0400, Yuxin Ren wrote:
Hi,
I just want to make sure that you do not misunderstand my questions.
All my questions are related the user level, that is l4re, not the kernel.
Ok, I see, when you mention Fiasco I always think of the kernel. So for
userland:
Regarding new/delete
Lackorzynski
a...@os.inf.tu-dresden.de wrote:
On Fri Jun 26, 2015 at 22:44:07 +0800, Yuxin Ren wrote:
You said Fiasco implements its own new/delete operator, could you show
me where the code for those is?
There are several placement new's, for example in thread.cpp and
task.cpp. Just look for operator
Hi,
I find in the src/l4/pkg directory, there are some libraries --
libgcc, libstdc++-v3, and libsupc++. But in those libraries, I just
found very little source code. Instead, they include many makefiles.
Where is the source code of those libraries? And why are there those makefiles?
Thanks a
Do you want to use rtti in kernel or user level?
It seems to be pretty difficult to support rtti and exception handler in
run-time, especially in kernel.
I also want to know if Fiasco support exception handler in kernel or user
space.
If it supports, I want to learn to how to achieve such
Hi All,
Does Fiasco support floating point processing?
If it supports, where is code to initialize and save/store floating point
registers?
Thanks a lot.
Yuxin
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It seems this is the maximal amount of memory a process/thread can use.
Yuxin
On Fri, May 8, 2015 at 12:04 AM, watermirror 357836...@qq.com wrote:
hi, what is Ram_quota used for?
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I think a thread maybe migrated to another core due to contention of
helping lock.
But what do you mean by some extra work will need to be done in the
schedule function?
What is extra work and special context?
Yuxin
On Thu, Apr 23, 2015 at 8:52 PM, deng.ch...@zte.com.cn wrote:
Hi:
I am
At least, it supports pthread library.
On Fri, Oct 10, 2014 at 1:48 PM, teclis High Elf teclis.high@gmail.com
wrote:
So L4Re is POSIX compliant?
On Fri, Oct 10, 2014 at 12:16 PM, Björn Döbel doe...@os.inf.tu-dresden.de
wrote:
Am 10.10.2014 um 18:00 schrieb teclis High Elf:
I have
On Tue, Sep 30, 2014 at 5:15 PM, Adam Lackorzynski
a...@os.inf.tu-dresden.de wrote:
Hi,
On Mon Sep 29, 2014 at 13:24:56 -0400, Yuxin Ren wrote:
I found in the kernel, the capability mapping and memory mapping have
very
similar code path.
But I found their performance difference is around 1000
Hi,
Why moe is required during runtime? What is its job?
Thank you.
Yuxin
On Tue, Sep 30, 2014 at 5:17 PM, Adam Lackorzynski
a...@os.inf.tu-dresden.de wrote:
On Tue Sep 30, 2014 at 15:01:15 +, Masti Ramya Jayaram wrote:
I see that in the default l4linux configuration, it uses ned, moe
Hi All,
I found in the kernel, the capability mapping and memory mapping have very
similar code path.
But I found their performance difference is around 1000 cycles.
Is this true? If it is true, why do they have such large difference?
If this gap does not make sense, it should be a bug in my
:31 -0400, Yuxin Ren wrote:
I want to know what kernel idle thread does.
Does it just execute halt instruction or anything else?
Mostly it is calling a halt instruction but it can also do remote work.
Where is code for the idle thread?
Please look for 'for (;;) idle_op
Hi All,
I want to know what kernel idle thread does.
Does it just execute halt instruction or anything else?
Where is code for the idle thread?
Thank you so much.
Best,
Yuxin
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Thank you very much.
You are really helpful!
I have looked at that code and understand it very well.
Yuxin
On Tue, Sep 23, 2014 at 1:42 AM, Adam Lackorzynski
a...@os.inf.tu-dresden.de wrote:
On Thu Sep 18, 2014 at 21:38:30 -0400, Yuxin Ren wrote:
I have question about tlb flush.
When
Hi All,
Does Fiasco support yield system call?
Or other mechanism one thread can switch to another one without IPC?
Thank you very much.
Yuxin
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the
extra check here?
The author should have some reason to do so, right?
Thanks a lot!!
Best,
Yuxin
On Tue, Sep 9, 2014 at 5:03 PM, Adam Lackorzynski a...@os.inf.tu-dresden.de
wrote:
On Mon Sep 08, 2014 at 11:54:32 -0400, Yuxin Ren wrote:
Unfortunately this modification does not help.
I
but the
lock_cnt is 0?
Now in my test, the kernel goes into this dead loop.
I cannot figure out how to solve this problem.
Thank you very much.
Yuixn
On Sun, Aug 31, 2014 at 5:58 PM, Adam Lackorzynski
a...@os.inf.tu-dresden.de wrote:
On Fri Aug 29, 2014 at 13:46:38 -0400, Yuxin Ren wrote:
I have
Thanks a lot!
I will try it.
But could you explain to me why this is better?
I am really curious about how to implement and debug such staff.
Best
Yuxin
On Mon, Sep 1, 2014 at 5:58 AM, Adam Lackorzynski a...@os.inf.tu-dresden.de
wrote:
On Fri Aug 29, 2014 at 13:46:38 -0400, Yuxin Ren wrote
else?
Thank you very much.
Best,
Yuxin
On Wed, Aug 27, 2014 at 2:28 PM, Yuxin Ren r...@gwmail.gwu.edu wrote:
Hi All,
I have a question about the dec_lock_cnt method in Context class under
multiple processor.
In its implementation, it checks if thread's home cpu is equal to current
cpu
Hi All,
I have a question about the dec_lock_cnt method in Context class under
multiple processor.
In its implementation, it checks if thread's home cpu is equal to current
cpu.
If not, it does not unset _running_under_lock variable, even if the
_lock_cnt is 0.
Why does it check if home cpu is
Hi All,
In the Base_mappable class, in /fiasco/src/kern/mapping_tree.cpp file,
what is type of the lock in this class, helping lock, spin lock or others?
And usually I find it is hard to identify the type of a lock.
Could someone tell me how to figure out the lock's type?
Thank you very much.
Hi All,
I want to do cap/mem mapping without IPC to another thread.
In particular, I want a thread to map its own memory or capability to
itself.
How can I achieve this?
Thank you.
Yuxin
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I did not measure min value.
The avg is around 5000 cycs, and my machine is 2.8GHz.
Client and server are in different core.
On Wed, Aug 6, 2014 at 5:42 PM, Adam Lackorzynski a...@os.inf.tu-dresden.de
wrote:
On Tue Aug 05, 2014 at 17:19:09 -0400, Yuxin Ren wrote:
Sorry, it's my typo
Hi All,
Now I am testing the response time in Fiasco, especially for the worse case.
The results are strange.
The worse case result are always around 2us.
I have filtered out the timer interrupt, so I cannot understand what
happened.
I am using intel IA32 multi core cpu.
Do you have any idea
.
I filter out the timer interrupt, but do not flush the cache and tlb.
Thank you very much,
Yuixn
On Tue, Aug 5, 2014 at 4:41 PM, Adam Lackorzynski a...@os.inf.tu-dresden.de
wrote:
On Tue Aug 05, 2014 at 13:03:51 -0400, Yuxin Ren wrote:
Now I am testing the response time in Fiasco
Hi All,
I cannot understand the logic of the IPI interrupt handler very well.
I hope someone can help me.
Thanks a lot.
I am using intel IA32 multi core cpu.
My scenario is one client and one server thread on different core. Client
sends simple data-only IPC to the server.
1. The function
21, 2014 at 10:09:27 +0800, Yuxin Ren wrote:
I think I have found the reson. But I cannot understand the logic of that
code.
In the Context::enqueue_drq method, there is a piece of code to determin
if
IPI is needed.
if (!_pending_rq.queued
wrote:
On Thu Jul 17, 2014 at 13:03:31 -0400, Yuxin Ren wrote:
Now I want to how many IPIs are sent during an IPC. So I add a counter
for
IPI in the kernel, and in the user level, there is a client sending IPC
to
a server on another core.
But I found some behavior are very strange.
1
, Yuxin Ren wrote:
I note that when a thread does memory or capability mapping, both over
system call and IPC, it needs take a lock, which is the existence_lock of
target task. I cannot understand it needs take a per task, as cap/page
table are per thread.
What data does this lock to protect
Hi All,
Now I want to how many IPIs are sent during an IPC. So I add a counter for
IPI in the kernel, and in the user level, there is a client sending IPC to
a server on another core.
But I found some behavior are very strange.
1. The total number of IPI are not multiple times of the number of
Hi
I cannot understand the second and third arguments of this function.
Could someone tell me how to use those arguments?
Thank you
Yuixn
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Hi All,
I know in previous Fiasco kernel, there is a kernel option to use
scheduling timer in one-shot model. But I cannot find this option in the
latest Fiasco kernel.
So now how can I enable this feature?
In addition, where is the code for timer interrupt handler?
Could someone give me some
This makes sense.
However I think the receiver needs this queue to save senders who want to
talk to it.
So why does sender still need this _wq?
Thank you.
On Mon, Jul 14, 2014 at 5:06 PM, Adam Lackorzynski
a...@os.inf.tu-dresden.de wrote:
On Thu Jul 10, 2014 at 14:20:20 -0400, Yuxin Ren
Hi,
I note in the Sender class there is a variable _wq.
What is the role of this variable?
And in the IPC, we set it to the sender_list of receiver.
Why?
Thank you.
Yuxin
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.
Could you give me more hints about this?
Thanks so much,
Best
On Tue, Jul 1, 2014 at 5:44 PM, Adam Lackorzynski a...@os.inf.tu-dresden.de
wrote:
On Fri Jun 27, 2014 at 10:21:38 -0400, Yuxin Ren wrote:
Thank you very much.
I have a further question.
For simple data-only IPCs, do we still
Hi,
I find before handle IPC, we always call handshake_receiver function.
A basic question is why do we need to handshake receiver? What do we
do when we handshake_receiver?
Another thing I note is we have separate handshake_receiver
(remote_handshake_receiver)
if the receiver is on the other
Thank you very much.
I have a further question.
For simple data-only IPCs, do we still need 4 IPIs?
On Thu, Jun 26, 2014 at 4:38 PM, Adam Lackorzynski
a...@os.inf.tu-dresden.de wrote:
On Tue Jun 24, 2014 at 15:43:06 -0400, Yuxin Ren wrote:
When I go through the IPC code, I have some
Hi,
When I go through the IPC code, I have some questions about dqr handler.
In the remote_ipc_send function within the thread-ipc.cpp file, I find a
comment
// trigger remote_ipc_receiver_ready path, because we may need to grab
locks
// and this is forbidden in a DRQ handler. So transfer
Hi,
I think printf usually invoke system call. But in Fiasco only one system
call is capability invocation. So what capability is invoked by printf? Or
Fiasco implements printf in user level, so printf triggers a normal IPC?
Thank you.
Best
___
In the rcupdate.cpp file, line 141.
In the class, there is an enum Period.
And in the comment, it says this period is 10ms.
Sorry for my unclear question.
On Tue, Jun 17, 2014 at 5:42 PM, Adam Lackorzynski
a...@os.inf.tu-dresden.de wrote:
On Tue Jun 17, 2014 at 11:59:43 -0400, Yuxin Ren wrote
Hi
I do not understand the period in Rcu class.
How do we use it?
Now it is 10ms, how is it calculated?
Thanks a lot.
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I have some questions about the map_iro code.
1. In this example, server maps the capability in the client to itself?
2. In the server code, there are two caps rcv_cap and tmp. Why do we
use tmp here?
Can't we only use the rcv_cap to receive the capability?
3. Finally, in the server, where
Your reply is pretty clear!
But I want to make sure another two questions.
1. In the dispatch function of the server, it extracts a cap from the stream
L4::Ipc::Snd_fpage cap;
ios cap;
Why do we use cap here? What is the difference between cap and the
receive
Hi,
I want to write some code to transfer capabilities from server to client.
But I have no idea how to do this as I am not familiar with L4Re and its
interface.
Could anyone give me some example code or some hints?
Thank you very much.
Best
___
you tell me where is the code on IPC path to invoke
IPI operations?
Thanks so much.
On Tue, Jun 3, 2014 at 5:57 PM, Adam Lackorzynski a...@os.inf.tu-dresden.de
wrote:
Hi,
On Sun Jun 01, 2014 at 05:15:06 -0800, Yuxin Ren wrote:
I am learning the IPC code in the Fiasco kernel. I have some
Hi
I am learning the IPC code in the Fiasco kernel. I have some questions here.
If the receiver is not ready, we will add the sender to the sender_list.
But I did find any lock to protect the sender_list. So if two threads at
different cores try to add themselves to the sender_list at the same
Thank you very much for your detail reply.
It is really useful and helpful.
On Thu, May 29, 2014 at 9:17 AM, Marcus Hähnel
mhaeh...@os.inf.tu-dresden.de wrote:
On 2014-05-29 18:22, Yuxin Ren wrote:
On Tue, May 27, 2014 at 11:44 PM, Marcus Hähnel
mhaeh...@os.inf.tu-dresden.de wrote
On Tue, May 27, 2014 at 11:44 PM, Marcus Hähnel
mhaeh...@os.inf.tu-dresden.de wrote:
On 2014-05-28 03:59, Yuxin Ren wrote:
Thank you very much.
But how can I know which file is compiled?
This is decided during build time based on your configuration. The vuild
system decides which file
Hi,
Now I am learning the kernel code of Fiasco.
But as I do not know much about C++, I feel confused about some code.
In the file obj_space-virt.cpp, we have such code
EXTENSION class Generic_obj_space : Obj_space_virtGeneric_obj_spaceSPACE
And similarly, in the file obj_space-phys.cpp, we
Thank you very much.
But how can I know which file is compiled?
On Wed, May 28, 2014 at 6:55 AM, Adam Lackorzynski
a...@os.inf.tu-dresden.de wrote:
Hi,
On Tue May 27, 2014 at 13:51:31 -0800, Yuxin Ren wrote:
Now I am learning the kernel code of Fiasco.
But as I do not know much about C
Hi,
Where is the code around kernel entry, including both l4Re and kernel?
What is the register format of system call in Fiasco?
Thanks a lot.
Best
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thread guarantee all children finish
migration.
Thank you.
On Wed, May 14, 2014 at 7:14 PM, Adam Lackorzynski
a...@os.inf.tu-dresden.de wrote:
On Tue May 13, 2014 at 17:05:34 -0800, Yuxin Ren wrote:
How can I get the id of cpu(core) the current thread is running on?
The system does not do
wrote:
Hi,
On Sat May 10, 2014 at 11:23:47 +0800, Yuxin Ren wrote:
I cannot understand dataspace very well. I have some questions about it.
Each time I want to alloc a piece of memory, I must create a dataspace
first?
I think you mean that you need to allocate a capability before calling
How can I get the id of cpu(core) the current thread is running on?
Thank you
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For the unmapping stuff, can you tell me a little more in detail.
I do not understand the parameters of unmap function.
Thank you so much.
On Tue, May 13, 2014 at 3:55 PM, Adam Lackorzynski
a...@os.inf.tu-dresden.de wrote:
On Tue May 13, 2014 at 20:56:54 +0800, Yuxin Ren wrote:
Can I alloc
Thank you very much for your reply.
But I still have some questions.
Can I alloc and free memory without dataspace?
I know we can do memory mapping over IPC, using L4::Ipc::Snd_fpage
and L4::Ipc::Rcv_fpage.
So after a client gets a piece of memory mapping in, how does it ummap that
memory? Still
code?
Bjoern
Am 08.05.2014 21:02, schrieb Yuxin Ren:
Year,
I did those thing. Each server tread has its own server obj and register
server instance, and it calls register_obj() and server.loop() on their
own.
But this does not work. And actually the master thread in server always
I cannot understand dataspace very well. I have some questions about it.
Each time I want to alloc a piece of memory, I must create a dataspace
first?
I look at the example code of memory allocation.
I found after create adataspace, we call
I have one client and one server talking to each other, and both of them
have 2 threads.
I want thread 1 in client only talk to thread 1 in server, and thread 2 in
client only talk to
thread 2 in server.
How can I achieve this?
Thanks
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