On Mon, Oct 19, 2015 at 10:58:55AM +0100, Chris Wilson wrote:
> During testing we observed that the last cacheline was not being flushed
> from a
>
> mb()
> for (addr = addr & -clflush_size; addr < end; addr += clflush_size)
> clflushopt();
> mb()
>
> loop (where
On Mon, 19 Oct 2015, Sekhar Nori wrote:
> + /*
> + * A spurious IRQ can result if interrupt that triggered the
> + * sorting is no longer active during the sorting (10 INTC
> + * functional clock cycles after interrupt assertion). Or a
> + * change in interrupt mask
Hi Thierry,
Am Montag, 21. September 2015, 11:33:17 schrieb Boris Brezillon:
> Hello,
>
> This series adds support for atomic PWM update, or IOW, the capability
> to update all the parameters of a PWM device (enabled/disabled, period,
> duty and polarity) in one go.
is anything more blocking
On Mon, Oct 19, 2015 at 03:31:51PM +0530, Vineet Gupta wrote:
> Peter this is awesome documentation and would be a shame to get lost in lkml
> archives. Can it please make it's way into git :-)
Its in tip/perf/core and should see the next merge window if I'm not
mistaken.
Thanks!
--
To
Hi Doug/ Krzysztof ,
On 15 October 2015 at 04:10, Doug Anderson wrote:
> Hi,
>
> On Tue, Oct 13, 2015 at 6:06 PM, Alim Akhtar wrote:
>> +Doug
>> Hello,
>> AFAIR, dw_mmc host controller does support UHS-I [1], specially SDR50
>> and SDR104 modes.
>>
>> [1]:
On Monday 19 October 2015 09:34:15 Geert Uytterhoeven wrote:
> On Wed, Oct 7, 2015 at 1:23 PM, Arnd Bergmann wrote:
> > static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
> >
> > which truncates the result to 32 bit.
>
> Woops.
>
> See also my unanswered question in
Hi Thomas,
Found it - I think there is an easy way to get rid of all global
variables in each pinctrl-. It's enough to:
- extend struct mvebu_pinctrl with generic pointer
- pass SoC specific structure to mvebu_pinctrl_probe via dev->driver_data
- in mvebu_pinconf_group_set/get pass an additional
On Monday 19 October 2015 11:37:00 Ralf Baechle wrote:
> On Wed, Oct 07, 2015 at 01:23:07PM +0200, Arnd Bergmann wrote:
>
> > > I haven't checked all architectures, but I assume what happens is that
> > > 64-bit ones just #define atomic64_t atomic_long_t, so they don't have
> > > to provide three
On Monday 19 October 2015 03:22 PM, Peter Zijlstra wrote:
> On Mon, Oct 19, 2015 at 09:46:35AM +, Vineet Gupta wrote:
>> > On ARC we could use the atomic EXchange to implement a user space only
>> > binary
>> > semaphore - these atomic ops will be small duration so it is OK to spin
>> > wait
On 10/19/2015 05:36 PM, Roger Pau Monné wrote:
> El 10/10/15 a les 6.08, Bob Liu ha escrit:
>> On 10/05/2015 10:55 PM, Roger Pau Monné wrote:
>>> The same for the pool of persistent grants, it should be per-device and
>>> not per-ring.
>>>
>>> And I think this issue is far worse than the others,
On Wednesday 26 August 2015 07:55 PM, Peter Zijlstra wrote:
> On Wed, Aug 26, 2015 at 03:12:25PM +0200, Peter Zijlstra wrote:
>> On Mon, Aug 24, 2015 at 05:20:20PM +0300, Alexey Brodkin wrote:
>>> @@ -295,6 +317,16 @@ static int arc_pmu_add(struct perf_event *event, int
>>> flags)
>>> }
>>>
During testing we observed that the last cacheline was not being flushed
from a
mb()
for (addr = addr & -clflush_size; addr < end; addr += clflush_size)
clflushopt();
mb()
loop (where the initial addr and end were not cacheline aligned).
Changing the loop
On Mon, Oct 19, 2015 at 03:31:42PM +0900, Minchan Kim wrote:
> Hello, it's too late since I sent previos patch.
> https://lkml.org/lkml/2015/6/3/37
>
> This patch is alomost new compared to previos approach.
> I think this is more simple, clear and easy to review.
>
> One thing I should notice
On Monday 19 October 2015 11:39:31 Arnd Bergmann wrote:
> On Monday 19 October 2015 16:54:23 Tony Cho wrote:
> > Hi Arnd Bergmann,
> >
> > When I apply this patch, I cannot make WILC1000 module (wilc1000.ko)
> > because CONFIG_WILC1000 is y and also I can see some link errors for the
> >
On Mon, Oct 19, 2015 at 10:44:41AM +0100, David Woodhouse wrote:
> On Sun, 2015-10-18 at 20:53 +0100, Mark Brown wrote:
> > On Sun, Oct 18, 2015 at 12:37:57PM -0700, Greg Kroah-Hartman wrote:
> > > On Sun, Oct 18, 2015 at 08:29:31PM +0100, Mark Brown wrote:
> > > > On Fri, Oct 16, 2015 at
On Mon, Oct 19, 2015 at 09:46:35AM +, Vineet Gupta wrote:
> On ARC we could use the atomic EXchange to implement a user space only binary
> semaphore - these atomic ops will be small duration so it is OK to spin wait
> for a
> little bit. That's how the old pthread library worked for ARC w/o
On 10/19/2015 09:36 AM, Hannes Frederic Sowa wrote:
Hi,
On Sun, Oct 18, 2015, at 22:59, Alexei Starovoitov wrote:
On 10/18/15 9:49 AM, Daniel Borkmann wrote:
Okay, I have pushed some rough working proof of concept here:
Under some conditions, irq sorting procedure used by INTC can go wrong
resulting in a spurious irq getting reported.
This condition is flagged by INTC by setting "Spurious IRQ Flag" in SIR
register to 0x1ff. Section 6.2.5 of AM335x TRM revised Jun 2014
describes this.
Using IRQ number 0 for
On Monday 19 October 2015 03:05 PM, Peter Zijlstra wrote:
> On Mon, Oct 19, 2015 at 09:28:43AM +, Vineet Gupta wrote:
>> > On Monday 19 October 2015 11:20 AM, Andi Kleen wrote:
>>> > > Vineet Gupta writes:
> >> But this user space - so IMHO UP/SMP doesn't matter and we can't
> >>
On Mon, Oct 19, 2015 at 10:27:22AM +0800, ling.ma.prog...@gmail.com wrote:
> From: Ma Ling
>
> All load instructions can run speculatively but they have to follow
> memory order rule in multiple cores as below:
> _x = _y = 0
>
> Processor 0 Processor 1
>
> mov r1, [
Hi,
On 19 October 2015 at 11:19, Dmitry Kalinkin wrote:
[...]
> There is no optimal solution. In vanilla kernel you have just two drivers. You
> can either have 8 GE PIO2 boards or 4 GE PIO2 boards and any amount of boards
> potentially accessible through vme_user. None of this provides for the
On Sun, 2015-10-18 at 20:53 +0100, Mark Brown wrote:
> On Sun, Oct 18, 2015 at 12:37:57PM -0700, Greg Kroah-Hartman wrote:
> > On Sun, Oct 18, 2015 at 08:29:31PM +0100, Mark Brown wrote:
> > > On Fri, Oct 16, 2015 at 11:57:50PM -0700, Greg Kroah-Hartman wrote:
>
> > > > I can't see adding calls
Hi,
On Sat, Oct 17, 2015 at 07:25:07PM +, Insu Yun wrote:
> Since kzalloc can be failed in memory pressure,
> its return value should be checked and handled.
Thanks, queued.
-- Sebastian
signature.asc
Description: PGP signature
Olaf Hering writes:
> The Backup integration service on WS2012 has appearently trouble to
> negotiate with a guest which does not support the provided util version.
> Currently the VSS driver supports only version 5/0. A WS2012 offers only
> version 1/x and 3/x, and vmbus_prep_negotiate_resp
El 10/10/15 a les 10.30, Bob Liu ha escrit:
>
> On 10/03/2015 01:02 AM, Roger Pau Monné wrote:
>> El 05/09/15 a les 14.39, Bob Liu ha escrit:
>>> Split per ring information to an new structure:blkfront_ring_info, also
>>> rename
>>> per blkfront_info to blkfront_dev_info.
>> ^ removed.
>>>
>>>
On 17/10/15 23:56, kbuild test robot wrote:
Hi Suzuki,
[auto build test ERROR on v4.3-rc5 -- if it's inappropriate base, please
suggest rules for selecting the more suitable base]
url:
On Monday 19 October 2015 16:54:23 Tony Cho wrote:
> Hi Arnd Bergmann,
>
> When I apply this patch, I cannot make WILC1000 module (wilc1000.ko) because
> CONFIG_WILC1000 is y and also I can see some link errors for the cfg80211
> APIs.
>
> Can you consider this patch?
Ah, you are right. I see
Hi,
On Fri, Oct 16, 2015 at 09:49:20AM -0500, Andrew F. Davis wrote:
> I2C is only required when using the config item BATTERY_BQ27XXX_I2C which
> already depends on the I2C subsystem, remove the unneeded dependency from
> BATTERY_BQ27XXX.
Thanks, queued.
-- Sebastian
signature.asc
On Fri, Oct 16, 2015 at 10:01:33AM -0500, Andrew F. Davis wrote:
> On 10/16/2015 09:47 AM, Pali Rohár wrote:
> >On Friday 16 October 2015 15:44:12 Sebastian Reichel wrote:
> >>If BQ27XXX is enabled, but neither I2C based initialization, nor
> >>platform based initialization are activated,
On 19/10/2015 08:13, Takuya Yoshikawa wrote:
> Commit fd1369021878 ("KVM: x86: MMU: Move mapping_level_dirty_bitmap()
> call in mapping_level()") forgot to initialize force_pt_level to false
> in FNAME(page_fault)() before calling mapping_level() like
> nonpaging_map() does. This can sometimes
On Wed, Oct 07, 2015 at 01:23:07PM +0200, Arnd Bergmann wrote:
> > I haven't checked all architectures, but I assume what happens is that
> > 64-bit ones just #define atomic64_t atomic_long_t, so they don't have
> > to provide three sets of functions.
>
> scratch that, I just looked at all the
El 10/10/15 a les 6.08, Bob Liu ha escrit:
> On 10/05/2015 10:55 PM, Roger Pau Monné wrote:
>> The same for the pool of persistent grants, it should be per-device and
>> not per-ring.
>>
>> And I think this issue is far worse than the others, because a frontend
>> might use a persistent grant on
On Mon, Oct 19, 2015 at 09:28:43AM +, Vineet Gupta wrote:
> On Monday 19 October 2015 11:20 AM, Andi Kleen wrote:
> > Vineet Gupta writes:
> >> But this user space - so IMHO UP/SMP doesn't matter and we can't simulate
> >> them in
> >> C just by itself.
> > It matters when you access the
Not zeroing EFER means that a 32-bit firmware cannot enter paging mode
without clearing EFER.LME first (which it should not know about).
Yang Zhang from Intel confirmed that the manual is wrong and EFER is
cleared to zero on INIT.
Fixes: d28bc9dd25ce023270d2e039e7c98d38ecbf7758
Cc:
On Mon, Oct 19, 2015 at 09:58:23AM +0200, Ingo Molnar wrote:
>
> * ling.ma.prog...@gmail.com wrote:
>
> > From: Ma Ling
> >
> > All load instructions can run speculatively but they have to follow
> > memory order rule in multiple cores as below:
> > _x = _y = 0
> >
> > Processor 0
Not zeroing EFER means that a 32-bit firmware cannot enter paging mode
without clearing EFER.LME first (which it should not know about).
Yang Zhang from Intel confirmed that the manual is wrong and EFER is
cleared to zero on INIT.
Fixes: d28bc9dd25ce023270d2e039e7c98d38ecbf7758
Cc:
On Sat, Oct 17, 2015 at 11:01:44AM -0300, Ezequiel Garcia wrote:
> On 15 Oct 09:17 AM, Antoine Tenart wrote:
> > Rework the pxa3xx_nand driver to allow using functions exported by the
> > nand framework to detect the flash and the timings. Then setup the
> > timings using the helpers previously
On Mon, Oct 19, 2015 at 10:27:22AM +0800, ling.ma.prog...@gmail.com wrote:
> From: Ma Ling
>
> All load instructions can run speculatively but they have to follow
> memory order rule in multiple cores as below:
> _x = _y = 0
>
> Processor 0 Processor 1
>
> mov r1, [
Ezequiel,
On Sat, Oct 17, 2015 at 10:57:26AM -0300, Ezequiel Garcia wrote:
> On 15 Oct 09:17 AM, Antoine Tenart wrote:
> > /*
> > * Set the data and OOB size, depending on the selected
> > * spare and ECC configuration.
> > @@ -1538,6 +1660,19 @@ KEEP_CONFIG:
> > if (nand_scan_ident(mtd,
On Fri, 2015-10-16 at 22:09 +0200, Christophe JAILLET wrote:
> Le 16/10/2015 12:02, Michael Ellerman a écrit :
> > As the kbuild robot detected you have left an extra "}" here.
> >
> > I don't mind too much if you send patches that aren't compile tested, but
> > you
> > might save yourself
On Mon, Oct 19, 2015 at 11:30 AM, David Howells wrote:
> Dmitry Vyukov wrote:
>
>> > Does the attached patch fix it for you?
>>
>> Yes, it fixes the crash for me.
>
> Can I put you down as a Tested-by?
>
> David
Yes, sure. Do I need to say something like:
Tested-by: Dmitry Vyukov
in future?
Signed-off-by: Fengguang Wu
---
pcie-altera.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/host/pcie-altera.c b/drivers/pci/host/pcie-altera.c
index b5e7bc2..45f03e3 100644
--- a/drivers/pci/host/pcie-altera.c
+++ b/drivers/pci/host/pcie-altera.c
@@ -114,7
Hi Ley,
[auto build test WARNING on pci/next -- if it's inappropriate base, please
suggest rules for selecting the more suitable base]
url:
https://github.com/0day-ci/linux/commits/Ley-Foon-Tan/arm-add-msi-h-to-Kbuild/20151019-162417
reproduce:
# apt-get install sparse
make
Dmitry Vyukov wrote:
> > Does the attached patch fix it for you?
>
> Yes, it fixes the crash for me.
Can I put you down as a Tested-by?
David
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On Monday 19 October 2015 11:20 AM, Andi Kleen wrote:
> Vineet Gupta writes:
>> But this user space - so IMHO UP/SMP doesn't matter and we can't simulate
>> them in
>> C just by itself.
> It matters when you access the perf ring buffer which is updated by kernel.
That's part of the problem. The
On Fri, 2015-10-16 at 23:38 +0200, Christophe JAILLET wrote:
> of_get_property() is used inside the loop, but then the reference to the
> node is dropped before dereferencing the prop pointer, which could by then
> point to junk if the node has been freed.
>
> Instead use of_property_read_u32()
Thomas,
2015-10-19 9:23 GMT+02:00 Thomas Petazzoni
:
> Hello,
>
> On Mon, 19 Oct 2015 08:04:49 +0200, Marcin Wojtas wrote:
>
>> > I don't like this. The mvebu_pinctrl_soc_info structure is meant to be
>> > a read-only structure that only describes static information giving
>> > SoC-specific
On Fri, 16 Oct 2015, Andrew F. Davis wrote:
> Add support for the TPS65912 device. It provides communication
> through I2C and contains the following components:
>
> - Regulators
> - Load switches
> - GPO controller
What's a GPO controller?
> Signed-off-by: Andrew F. Davis
> ---
>
From: Aravind Gopalakrishnan
This function doesn't give us the "Node ID" as the function name
suggests. Rather, it receives a PCI device as argument, checks the
available F3 PCI device IDs in the system and returns the index of the
matching Bus/Device IDs.
Rename it to amd_pci_dev_to_node_id().
From: Borislav Petkov
* Shorten variable names
* Realign code, space out for better readability
No code changed:
# arch/x86/kernel/setup.o:
textdata bss dec hex filename
45433096 69904 77543 12ee7 setup.o.before
45433096 69904 77543 12ee7
> On 2015/10/18, at 18:04, Martyn Welch wrote:
>
>
>
> On 18/10/15 18:53, Dmitry Kalinkin wrote:
>> On Sun, Oct 18, 2015 at 10:31 AM, Martyn Welch wrote:
>>>
>>> On 11/10/15 01:13, Dmitry Kalinkin wrote:
This introduces a new dma device that provides a single ioctl call that
From: Borislav Petkov
memblock_reserve() can fail but the crashkernel reservation code
doesn't check that and this can lead the user into believing that the
crashkernel region was actually reserved. Make sure we check that return
value and we exit early with a failure message in the error case.
From: Borislav Petkov
* Remove unused auto_set variable
* Cleanup local function variable declarations
* Reformat printk string and use pr_info()
No functionality change.
Reviewed-by: Dave Young
Reviewed-by: Joerg Roedel
Cc: Andrew Morton
Cc: Andy Lutomirski
Cc: "H. Peter Anvin"
Cc: Ingo
From: Baoquan He
People reported that when allocating crashkernel memory using the
",high" and ",low" syntax, there were cases where the reservation of the
high portion succeeds but the reservation of the low portion fails.
Then kexec can load the kdump kernel successfully, but booting the
From: Borislav Petkov
It is helpful when the crashkernel cmdline parsing routines actually say
which character is the unrecognized one. Make them do so.
Reviewed-by: Dave Young
Reviewed-by: Joerg Roedel
Cc: Andrew Morton
Cc: Andy Lutomirski
Cc: Baoquan He
Cc: "H. Peter Anvin"
Cc: Ingo
From: Borislav Petkov
Use a macro instead. No functionality change.
Reviewed-by: Dave Young
Reviewed-by: Joerg Roedel
Cc: Andrew Morton
Cc: Andy Lutomirski
Cc: "H. Peter Anvin"
Cc: Ingo Molnar
Cc: jerry_hoem...@hp.com
Cc: Jiri Kosina
Cc: Juergen Gross
Cc: Mark Salter
Cc: Thomas
From: Borislav Petkov
Hi Ingo,
a couple of fixes/cleanups this week. I even think each patch's commit
message actually sufficiently explains each change. I know, it is
unbelievable. :-)
Please apply,
thanks.
Andi Kleen (1):
x86/mce: Fix thermal throttling reporting after kexec
Aravind
From: Andi Kleen
The per CPU thermal vector init code checks if the thermal vector is
already installed and complains and bails out if it is.
This happens after kexec, as kernel shut down does not clear the thermal
vector APIC register.
This causes two problems:
1. So we always do not fully
On Thu, 2015-10-15 at 17:06 -0500, Konstantin Shkolnyy wrote:
> cp2108 GET_LINE_CTL returns the 16-bit value with the 2 bytes swapped.
> However, SET_LINE_CTL functions properly. When the driver tries to modify
> the register, it reads it, modifies some bits and writes back. Because the
> read
On Fri, 16 Oct 2015, Andrew F. Davis wrote:
> The TPS65086 PMIC contains several regulators and a GPO controller.
> Add bindings for the TPS65086 PMIC.
>
> Signed-off-by: Andrew F. Davis
> ---
> .../devicetree/bindings/gpio/gpio-tps65086.txt | 17
>
On Mon, Oct 19, 2015 at 12:58:47AM -0700, Stephane Eranian wrote:
> Peter,
>
> On Sat, Oct 17, 2015 at 2:56 AM, Peter Zijlstra wrote:
> >
> > On Sat, Oct 17, 2015 at 03:28:11AM +0200, Stephane Eranian wrote:
> > >
> > > This patch eliminates all known RCU violations detected
> > > by the RCU
[Dropped stable from Cc:. I can't see how this is still relevant for
that list.]
Hi Tilman,
On ma, 2015-10-12 at 11:18 +0200, Tilman Schmidt wrote:
> While it doesn't make any sense indeed to run two instances of
> ldattach
> in parallel on one and the same serial port, it is entirely
On Mon, Oct 19, 2015 at 09:06:05AM +0200, Ingo Molnar wrote:
>
> * Peter Zijlstra wrote:
>
> > In any case, its all moot now, since Paul no longer requires schedule() to
> > imply
> > a full barrier.
> >
> > [...]
>
> Nevertheless from a least-surprise POV it might be worth guaranteeing it,
The following patch adds support for describing ACPI enumerated I2C mux ports
like this (added as Documentation/acpi/i2c-muxes.txt):
+--+ +--+
| SMB1 |-->| MUX0 |--CH00--> i2c client A (0x50)
| | | 0x70 |--CH01--> i2c client B (0x50)
+--+ +--+
Device (SMB1)
{
Name
On Sunday 18 October 2015 17:44:19 WEN Pingbo wrote:
> Two replacements happened in this patch:
> 1. using timespec64 to prevent time overflow in 2038
> 2. using ktime_get_ts64 to avoid wall time issues(leap second, etc)
>
> Signed-off-by: WEN Pingbo
>
The patch looks correct, but I
On Fri, Oct 16, 2015 at 06:33:44PM +0200, Ulf Hansson wrote:
> On 16 October 2015 at 17:01, Ludovic Desroches
> wrote:
> > Add suspend and resume PM ops.
> >
> > Signed-off-by: Ludovic Desroches
>
> I have no problem with this patch, nice and easy.
>
> Although it would be interesting to see
On Sunday 18 October 2015 17:45:19 WEN Pingbo wrote:
> Using struct timeval will cause time overflow in 2038, replacing it with
> a 64bit version.
>
> In addition, the origin driver try to covert usec to jiffies manually in
> hilse_donode(). This is not a universal and safe way, using
>
The Marvell Berlin BG2CD has 3 watchdogs which are compatible with the
snps,dw-wdt driver sit in the sysmgr domain. This patch adds the
corresponding device tree nodes.
NOTE: although BG2CD doesn't have a HW sysmgr, but the sysmgr domain
exists.
Signed-off-by: Jisheng Zhang
---
The Marvell Berlin BG4CT has 3 watchdogs which are compatible with the
snps,dw-wdt driver sit in the sysmgr domain. This patch adds the
corresponding device tree nodes.
Signed-off-by: Jisheng Zhang
---
arch/arm64/boot/dts/marvell/berlin4ct.dtsi | 24
1 file changed, 24
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business opportunity you having being looking for is here again. email
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Enable wdt0 on Marvell Berlin BG2 based Sony NSZ-GS7 to make use of the
watchdog functionality.
Signed-off-by: Jisheng Zhang
---
arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts
The Marvell Berlin BG2Q has 3 watchdogs which are compatible with the
snps,dw-wdt driver sit in the sysmgr domain. This patch adds the
corresponding device tree nodes.
Signed-off-by: Jisheng Zhang
---
arch/arm/boot/dts/berlin2q.dtsi | 24
1 file changed, 24
The Marvell Berlin BG2 has 3 watchdogs which are compatible with the
snps,dw-wdt driver sit in the sysmgr domain. This patch adds the
corresponding device tree nodes.
Signed-off-by: Jisheng Zhang
---
arch/arm/boot/dts/berlin2.dtsi | 24
1 file changed, 24 insertions(+)
On 10/19/2015 10:47 AM, John Garry wrote:
> Hi James,
>
> Could we please get a review for our driver? We have got some good
> input on changes we need to make, and we will produce another
> patchset in the coming days. However it would good to get a
> subsystem maintainer review/acknowledgement
On 10/19/2015 09:10 AM, yalin wang wrote:
This patch change map_lookup_elem() and map_update_elem() function
to use u64 temp variable if the key_size or value_size is less than
u64, we don't need use kmalloc() for these small variables.
Signed-off-by: yalin wang
From an application PoV that
Enable wdt0 on the Marvell BG4CT STB board to make use of the watchdog
functionality.
Signed-off-by: Jisheng Zhang
---
arch/arm64/boot/dts/marvell/berlin4ct-stb.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/berlin4ct-stb.dts
Enable wdt0 on the Marvell BG2Q DMP board to make use of the watchdog
functionality.
Signed-off-by: Jisheng Zhang
---
arch/arm/boot/dts/berlin2q-marvell-dmp.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts
Enable wdt0 on the Google Chromecast to make use of the watchdog
functionality.
Signed-off-by: Jisheng Zhang
---
arch/arm/boot/dts/berlin2cd-google-chromecast.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/berlin2cd-google-chromecast.dts
Hi Bjorn,
Thanks for the review.
On 16 October 2015 22:34, Bjorn wrote:
> On Fri, Oct 02, 2015 at 11:25:05AM +0100, Phil Edworthy wrote:
> > The R-Car PCIe host controller driver uses pci_common_init_dev(),
> > which is ARM-specific and requires the ARM struct hw_pci. The part of
> >
In Marvell berlin SoCs, there are watchdogs which are compatible with the
snps,dw-wdt driver. This series try to add watchdog support for them.
Jisheng Zhang (8):
arm: dts: berlin2q: add watchdog nodes
arm: dts: berlin2cd: add watchdog nodes
arm: dts: berlin2: add watchdog nodes
arm64:
Hi Peter,
On Fri, Oct 16, 2015 at 11:08:42AM +0200, Peter Rosin wrote:
> On 2015-10-16 01:47, Peter Rosin wrote:
> > On 2015-10-14 07:43, Ludovic Desroches wrote:
> >> On Tue, Oct 13, 2015 at 08:01:34PM +0200, Peter Rosin wrote:
> >>> On 2015-10-13 18:47, Cyrille Pitchen wrote:
> Le
On 19/10/15 11:08, Ingo Molnar wrote:
>
> * Adrian Hunter wrote:
>
>> Commit b20112edeadf ("perf/x86: Improve accuracy of perf/sched clock")
>> allowed the time_shift value in perf_event_mmap_page to be as much
>> as 32. Unfortunately the documented algorithms for using time_shift
>> have it
Hi Tejun,
On 2015/10/16 4:41, Tejun Heo wrote:
On Wed, Oct 14, 2015 at 09:38:09PM -0400, Tejun Heo wrote:
Hello,
On Fri, Oct 09, 2015 at 11:29:27PM -0400, Tejun Heo wrote:
The patchset is pretty lightly tested and I need to verify that the
corner cases behave as expected.
Fixed several
On Mon 2015-10-19 10:16:07, Geert Uytterhoeven wrote:
> If an architecture's main Kconfig file doesn't include
> kernel/power/Kconfig, but CONFIG_PM=y and HAVE_CLK=y (e.g. m68knommu
> allmodconfig):
>
> drivers/base/power/clock_ops.c: In function ‘__pm_clk_add’:
>
Hi James,
Could we please get a review for our driver? We have got some good input
on changes we need to make, and we will produce another patchset in the
coming days. However it would good to get a subsystem maintainer
review/acknowledgement to progress our upstreaming.
Thanks in advance,
Hi Erin,
On 05/10/15 08:27, Erin Lo wrote:
MT2701 is a SoC based on 32bit ARMv7 architecture. It contains 4 CA7 cores.
MT2701 share many HW IP with MT65xx series. This patchset was tested
on MT2701 evaluation board, and boot to shell ok.
This series contains document bindings, device tree
On 19/10/15 09:33, Jon Medhurst (Tixy) wrote:
On Wed, 2015-10-14 at 09:48 +0100, Sudeep Holla wrote:
[...]
OK, I understand what you mean now. I don't have a strong opinion, but
here is the reason why I prefer the approach I said earlier:
clk_set_rate doesn't return error if the h/w or
From: Borislav Petkov
Move the generic help text explaining each CPU type and what to select
under the "Processor Family" prompt and not under the M486 option. Also,
amend it with the missing options.
Signed-off-by: Borislav Petkov
---
arch/x86/Kconfig.cpu | 24 +---
1
On Thu, Oct 15, 2015 at 11:03:19AM +0200, Benjamin Cama wrote:
> Hi everyone,
>
> Le 2015-10-15 08:22, Gregory CLEMENT a écrit :
> > On jeu., oct. 15 2015, Ben Hutchings wrote:
> >
> >>On Wed, 2015-09-30 at 10:50 +0100, Luis Henriques wrote:
> >>>3.16.7-ckt18 -stable review patch. If anyone has
Changes since v4:
- Rename back to READ_ONCE_NOCHECK().
Changes since v3:
- Fixed build failure.
- Rename: s/READ_ONCE_NOCHECK/READ_ONCE_NOKSAN
- Spelling fix.
Changes since v2:
- Added some code comments in the first patch.
Andrey Ryabinin (2):
compiler, atomics: Provide
get_wchan() is racy by design, it may access volatile stack
of running task, thus it may access redzone in a stack frame
and cause KASAN to warn about this.
Use READ_ONCE_NOCHECK() to silence these warnings.
Signed-off-by: Andrey Ryabinin
Reported-by: Sasha Levin
---
arch/x86/kernel/process.c
Some code may perform racy by design memory reads. This could be
harmless, yet such code may produce KASAN warnings.
To hide such accesses from KASAN this patch introduces
READ_ONCE_NOCHECK() macro. KASAN will not check the memory
accessed by READ_ONCE_NOCHECK(). The KernelThreadSanitizer (KTSAN)
On 2015/10/19 15:50, Ulf Hansson wrote:
[...]
I understand the phy is optional, but you still need to handle the
EPROBE_DEFER case.
Perhaps you should also use devm_phy_optional_get() instead!?
I already changed it in version-2 [1]. :)
phy is mandatory for sdhci-arasan,5.1.
[1]:
This add power management suspend/resume support for the fsl-edma
driver.
eDMA acted as a basic function used by others. What it needs to do
is the two steps below to support power management.
In fsl_edma_suspend_late:
Check whether the DMA chan is idle, if it is not idle disable DMA
request.
On Sunday 18 October 2015 01:27:08 Chen-Yu Tsai wrote:
> Hi everyone,
>
> This is v6 of the Allwinner Reduced Serial Bus driver. This version puts
> the driver under drivers/bus instead of drivers/soc/sunxi. There are no
> changes to the binding or the driver itself.
>
> The series is based on
Hi,
> Sent: Saturday, October 17, 2015 10:54 AM
>
> Hi,
>
> On Tuesday 13 October 2015 03:52 PM, Yoshihiro Shimoda wrote:
> > This patch adds support for runtime ID/VBUS pin detection if
> > the channel 0 of R-Car gen3 is used. So, we are able to use
> > the channel as both host and peripheral.
On Wed, 2015-10-14 at 09:48 +0100, Sudeep Holla wrote:
>
> On 14/10/15 08:12, Jon Medhurst (Tixy) wrote:
> > On Tue, 2015-10-13 at 11:36 +0100, Sudeep Holla wrote:
> >>
> >> On 13/10/15 08:19, Jon Medhurst (Tixy) wrote:
> > [...]
> >>> But then we wouldn't get the WARN_ON and pr_err triggered
Hi,
> Sent: Saturday, October 17, 2015 10:48 AM
>
> Hi,
>
> On Tuesday 13 October 2015 03:52 PM, Yoshihiro Shimoda wrote:
> > To use the channel 0 of R-Car gen3 as periperal mode, This patch changes
> > the mode to OTG instead of HOST. Then, this driver needs to set some
> > registers to enable
Hi,
> Sent: Saturday, October 17, 2015 10:44 AM
>
> Hi,
>
> On Tuesday 13 October 2015 03:52 PM, Yoshihiro Shimoda wrote:
< snip >
> > diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> > index 7eb5859d..45c6131 100644
> > --- a/drivers/phy/Kconfig
> > +++ b/drivers/phy/Kconfig
> > @@
On Thu, Oct 15, 2015 at 9:21 PM, David Howells wrote:
> Does the attached patch fix it for you?
Yes, it fixes the crash for me.
> David
> ---
> commit a7609e0bb3973d6ee3c9f1ecd0b6a382d99d6248
> Author: David Howells
> Date: Thu Oct 15 17:21:37 2015 +0100
>
> KEYS: Fix crash when attempt
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