From: Long Li
When a NVMe hardware queue is mapped to several CPU queues, it is possible
that the CPU this hardware queue is bound to is flooded by returning I/O for
other CPUs.
For example, consider the following scenario:
1. CPU 0, 1, 2 and 3 share the same hardware queue
2. the hardware
On Sun, 2019-08-18 at 13:54 -0500, Wenwen Wang wrote:
> In fault_opcodes_write(), 'data' is allocated through kcalloc().
> However,
> it is not deallocated in the following execution if an error occurs,
> leading to memory leaks. To fix this issue, introduce the 'free_data'
> label
> to free
On Wed, Aug 14, 2019 at 11:19:37AM +0200, Vlastimil Babka wrote:
> On 8/14/19 8:57 AM, Wei Yang wrote:
> > On Tue, Aug 13, 2019 at 10:16:11PM -0700, Christoph Hellwig wrote:
> >>Btw, is there any good reason we don't use a list_head for vma linkage?
> >
> > Not sure, maybe there is some
On Sun, 2019-08-18 at 14:29 -0500, Wenwen Wang wrote:
> In fault_opcodes_read(), 'data' is not deallocated if
> debugfs_file_get()
> fails, leading to a memory leak. To fix this bug, introduce the
> 'free_data'
> label to free 'data' before returning the error.
>
> Signed-off-by: Wenwen Wang
Add base DTS file for pm8150 along with GPIOs, power-on, rtc and vadc
nodes
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/pm8150.dtsi | 97
1 file changed, 97 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/pm8150.dtsi
diff --git
This add base DTS file for sm8150-mtp and enables boot to console, adds
tlmm reserved range, resin node, volume down key and also includes pmic
file.
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/sm8150-mtp.dts | 51
Add the reserved memory regions in SM8150
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 111 +++
1 file changed, 111 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi
b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index
PMIC pm8150l is a slave pmic and this adds base DTS file for pm8150l
with power-on, adc and gpio nodes
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/pm8150l.dtsi | 80 +++
1 file changed, 80 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/pm8150l.dtsi
Add the regulators found in the mtp platform. This platform consists of
pmic PM8150, PM8150L and PM8009.
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/sm8150-mtp.dts | 327
1 file changed, 327 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts
Add hwlock, pmu, smem, tcsr_mutex_regs, apss_shared mailbox, apps_rsc
including the rpmhcc child nodes to the SM8150 DTSI
Co-developed-by: Sibi Sankar
Signed-off-by: Sibi Sankar
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 63
1 file
This add base DTS file for sm8150-mtp and enables boot to console, adds
tlmm reserved range, resin node, volume down key and also includes pmic
file.
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/sm8150-mtp.dts | 51
PMIC pm8150b is a slave pmic and this adds base DTS file for pm8150b
with power-on, adc, and gpio nodes
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/pm8150b.dtsi | 86 +++
1 file changed, 86 insertions(+)
create mode 100644
This add base DTS file with cpu, psci, firmware, clock node tlmm and
spmi and enables boot to console
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 307 +++
1 file changed, 307 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/sm8150.dtsi
This series adds DTS for SM8150, PMIC PM8150, PM8150B, PM8150L and
the MTP for SM8150.
Changes in v3:
- Fix copyright comment style to Linux kernel style
- Make property values all hex or decimal
- Fix patch titles and logs and make them consistent
- Fix line breaks
Changes in v2:
- Squash
On Tue, 20 Aug 2019 08:58:02 +
Parav Pandit wrote:
> + Dave.
>
> Hi Jiri, Dave, Alex, Kirti, Cornelia,
>
> Please provide your feedback on it, how shall we proceed?
>
> Short summary of requirements.
> For a given mdev (mediated device [1]), there is one representor
> netdevice and
> On Aug 18, 2019, at 12:20 PM, Thomas Gleixner wrote:
>
> While at it could you please ask your legal folks whether that custom
> license boilerplate can go away as well?
If you’re referring to the GPL boilerplate with “no warranty" and physical
address, then yes, as a matter of best practice
On Sun, 2019-08-18 at 15:23 -0500, Wenwen Wang wrote:
> In mlx4_ib_alloc_pv_bufs(), 'tun_qp->tx_ring' is allocated through
> kcalloc(). However, it is not always deallocated in the following
> execution
> if an error occurs, leading to memory leaks. To fix this issue, free
> 'tun_qp->tx_ring'
On Tue, Aug 20, 2019 at 07:08:18PM +0200, Sebastian Siewior wrote:
> Bit spinlocks are problematic if PREEMPT_RT is enabled, because they
> disable preemption, which is undesired for latency reasons and breaks when
> regular spinlocks are taken within the bit_spinlock locked region because
>
On 2019-08-10 01:18:34 [-0700], Christoph Hellwig wrote:
> > > Does SLUB work on -rt at all?
> >
> > It's the only allocator we support with a few tweaks :)
>
> What do you do about this particular piece of code there?
This part remains untouched. This "lock" is acquired within ->list_lock
On Tue, Aug 20, 2019 at 03:56:24PM +0200, Sebastian Duda wrote:
>
> so the status of the files is inherited from the subsystem `INPUT MULTITOUCH
> (MT) PROTOCOL`?
>
> Is it the same with the subsystem `NOKIA N900 POWER SUPPLY DRIVERS`
> (respectively `POWER SUPPLY CLASS/SUBSYSTEM and DRIVERS`)?
Hi Paul,
Bumping this thread; we'd really like to be able to boot test another
ISA in our CI. This lone patch is affecting our ability to boot. Can
you please pick it up?
https://lore.kernel.org/lkml/20190729211014.39333-1-ndesaulni...@google.com/
On Wed, Aug 7, 2019 at 2:12 PM Nick Desaulniers
+ /*
+* The new group must can be scheduled
+* together with current pinned events.
+* Otherwise, it will never get a chance
+* to be scheduled later.
That's wrapped short; also I don't think it is sufficient; what if you
happen to have a pinned event on
Em Mon, Aug 19, 2019 at 10:22:07PM +, Lubashev, Igor escreveu:
> On Mon, August 19, 2019 at 12:51 PM Mathieu Poirier
> wrote:
> > On Thu, 15 Aug 2019 at 15:42, Arnaldo Carvalho de Melo
> > wrote:
> > Things are working properly on your perf/cap branch. I tested with on both
> > x86 and
Kryo485 is found in SM8150, so add it it list of cpu compatibles
Signed-off-by: Vinod Koul
---
Documentation/devicetree/bindings/arm/cpus.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml
b/Documentation/devicetree/bindings/arm/cpus.yaml
From: Thomas Gleixner
Bit spinlocks are problematic if PREEMPT_RT is enabled, because they
disable preemption, which is undesired for latency reasons and breaks when
regular spinlocks are taken within the bit_spinlock locked region because
regular spinlocks are converted to 'sleeping spinlocks'
On Tue, 2019-08-20 at 16:25 +0100, Andrew Murray wrote:
> On Tue, Aug 20, 2019 at 02:52:30PM +, Chocron, Jonathan wrote:
> > On Mon, 2019-08-19 at 19:23 +0100, Andrew Murray wrote:
> > > On Tue, Jul 23, 2019 at 12:25:29PM +0300, Jonathan Chocron wrote:
> > > > The Root Port (identified by
> -Original Message-
> From: Lukas Wunner
> Sent: Tuesday, August 20, 2019 6:34 AM
> To: Limonciello, Mario
> Cc: mika.westerb...@linux.intel.com; linux-kernel@vger.kernel.org;
> andreas.noe...@gmail.com; michael.ja...@intel.com;
> yehezkel...@gmail.com; r...@rjwysocki.net;
On Tue, Aug 20, 2019 at 10:35 AM Krzysztof Kozlowski wrote:
>
> Add the compatibles for Kontron i.MX6UL N6310 SoM and boards.
>
> Signed-off-by: Krzysztof Kozlowski
>
> ---
>
> Changes since v5:
> New patch
> ---
> Documentation/devicetree/bindings/arm/fsl.yaml | 3 +++
> 1 file changed, 3
On Tue, Aug 20, 2019 at 09:08:55PM +0800, zhangfei wrote:
>
>
> On 2019/8/15 下午10:13, Greg Kroah-Hartman wrote:
> > On Wed, Aug 14, 2019 at 05:34:25PM +0800, Zhangfei Gao wrote:
> > > +int uacce_register(struct uacce *uacce)
> > > +{
> > > + int ret;
> > > +
> > > + if (!uacce->pdev) {
> > > +
On Thu, Aug 15, 2019 at 05:01:37PM +, Haiyang Zhang wrote:
> Currently in Azure cloud, for passthrough devices, the host sets the device
> instance ID's bytes 8 - 15 to a value derived from the host HWID, which is
> the same on all devices in a VM. So, the device instance ID's bytes 8 and 9
>
On Fri, 2019-08-16 at 14:39 +0300, Dan Carpenter wrote:
> This line was indented a bit too far.
>
> Signed-off-by: Dan Carpenter
Thanks, applied to for-next.
--
Doug Ledford
GPG KeyID: B826A3330E572FDD
Fingerprint = AE6B 1BDA 122B 23B4 265B 1274 B826 A333 0E57 2FDD
signature.asc
On Mon, 19 Aug 2019 at 16:22, Lubashev, Igor wrote:
>
> On Mon, August 19, 2019 at 12:51 PM Mathieu Poirier
> wrote:
> > On Thu, 15 Aug 2019 at 15:42, Arnaldo Carvalho de Melo
> > wrote:
> > >
> > > Em Thu, Aug 15, 2019 at 02:16:48PM -0600, Mathieu Poirier escreveu:
> > > > On Wed, 14 Aug 2019
Up until now, the pata_buddha driver would only check for cards on
initcall time. Now, the kernel will call its probe function as soon
as a compatible card is detected.
v6: Only do the drvdata workaround for X-Surf (remove breaks otherwise)
Style
v5: Remove module_exit(): There's no good way
On Tue, Aug 20, 2019 at 11:34 AM Ondřej Jirman wrote:
>
> On Tue, Aug 20, 2019 at 11:20:22AM -0500, Rob Herring wrote:
> > On Tue, Aug 20, 2019 at 9:53 AM wrote:
> > >
> > > From: Ondrej Jirman
> > >
> > > Some PHYs require separate power supply for I/O pins in some modes
> > > of operation.
Am Di., 20. Aug. 2019 um 17:40 Uhr schrieb Miroslav Lichvar
:
>
> On Tue, Aug 20, 2019 at 05:23:06PM +0200, Andrew Lunn wrote:
> > > - take a second "post" system timestamp after the completion
> >
> > For this hardware, completion is an interrupt, which has a lot of
> > jitter on it. But this
On Tue, 2019-08-20 at 10:00 -0400, Song Liu wrote:
>
> From 9ae74cff4faf4710a11cb8da4c4a3f3404bd9fdd Mon Sep 17 00:00:00
> 2001
> From: Song Liu
> Date: Mon, 19 Aug 2019 23:59:47 -0700
> Subject: [PATCH] x86/mm/pti: in pti_clone_pgtable(), increase addr
> properly
>
> Before 32-bit support,
On 8/20/19 6:42 PM, Max Staudt wrote:
> Hi Bartlomiej,
>
> On 08/20/2019 02:06 PM, Bartlomiej Zolnierkiewicz wrote:
>> WARNING: line over 80 characters
>> #354: FILE: drivers/ata/pata_buddha.c:287:
>> +while ((z =
>> zorro_find_device(ZORRO_PROD_INDIVIDUAL_COMPUTERS_X_SURF, z))) {
>
>
On 8/20/19 5:59 PM, Max Staudt wrote:
> Hi Bartlomiej,
>
> Thank you very much for your review!
>
> Question below.
>
>
> On 08/20/2019 02:06 PM, Bartlomiej Zolnierkiewicz wrote:
>>> + /* Workaround for X-Surf: Save drvdata in case zorro8390 has set it */
>>> + old_drvdata =
On Tue, Aug 20, 2019 at 3:45 AM Michal Hocko wrote:
>
> On Tue 20-08-19 17:48:23, Alex Shi wrote:
> > This patchset move lru_lock into lruvec, give a lru_lock for each of
> > lruvec, thus bring a lru_lock for each of memcg.
> >
> > Per memcg lru_lock would ease the lru_lock contention a lot in
>
The original clean up of "cut here" missed the WARN_ON() case (that
does not have a printk message), which was fixed recently by adding
an explicit printk of "cut here". This had the downside of adding a
printk() to every WARN_ON() caller, which reduces the utility of using
an instruction
Hi Eric,
On 08/08/2019 21:05, Greg Kroah-Hartman wrote:
> commit b617158dc096709d8600c53b6052144d12b89fab upstream.
>
> Some applications set tiny SO_SNDBUF values and expect
> TCP to just work. Recent patches to address CVE-2019-11478
> broke them in case of losses, since retransmits might
> be
Hi Bartlomiej,
On 08/20/2019 02:06 PM, Bartlomiej Zolnierkiewicz wrote:
> WARNING: line over 80 characters
> #354: FILE: drivers/ata/pata_buddha.c:287:
> +while ((z =
> zorro_find_device(ZORRO_PROD_INDIVIDUAL_COMPUTERS_X_SURF, z))) {
I see no good way to shorten this one. I think it's
On Tue, Aug 20, 2019 at 10:25 AM Uwe Kleine-König
wrote:
>
> A mux regulator is used to provide current on one of several outputs. It
> might look as follows:
>
> ,.
> -- -- -- -- -- -- -- -- `'
>
> Depending on which address is
+++ Matthew Garrett [19/08/19 17:17 -0700]:
From: David Howells
Provided an annotation for module parameters that specify hardware
parameters (such as io ports, iomem addresses, irqs, dma channels, fixed
dma buffers and other types).
Suggested-by: Alan Cox
Signed-off-by: David Howells
On 20-08-19, 19:03, Amit Kucheria wrote:
> On Tue, Aug 20, 2019 at 12:14 PM Vinod Koul wrote:
> >
> > This add base DTS file with cpu, psci, firmware, clock, tlmm and
> > spmi nodes which enables boot to console
> >
> > Signed-off-by: Vinod Koul
> > ---
> > arch/arm64/boot/dts/qcom/sm8150.dtsi
> On Aug 20, 2019, at 9:05 AM, Song Liu wrote:
>
>
>
>> On Aug 20, 2019, at 7:18 AM, Dave Hansen wrote:
>>
>> On 8/20/19 7:14 AM, Song Liu wrote:
*But*, that shouldn't get hit on a Skylake CPU since those have PCIDs
and shouldn't have a global kernel image. Could you confirm
There is no reason to print warnings when balloon page allocation fails,
as they are expected and can be handled gracefully. Since VMware
balloon now uses balloon-compaction infrastructure, and suppressed these
warnings before, it is also beneficial to suppress these warnings to
keep the same
On Tue, Aug 20, 2019 at 11:20:22AM -0500, Rob Herring wrote:
> On Tue, Aug 20, 2019 at 9:53 AM wrote:
> >
> > From: Ondrej Jirman
> >
> > Some PHYs require separate power supply for I/O pins in some modes
> > of operation. Add phy-io-supply property, to allow enabling this
> > power supply.
>
>
On Tue, Aug 20, 2019 at 12:58:49PM +0200, Christophe Leroy wrote:
> Le 20/08/2019 à 12:06, Peter Zijlstra a écrit :
> > On Mon, Aug 19, 2019 at 04:41:11PM -0700, Kees Cook wrote:
> >
> > > diff --git a/include/asm-generic/bug.h b/include/asm-generic/bug.h
> > > index 588dd59a5b72..da471fcc5487
On Tue, 20 Aug 2019 11:25:05 +
Parav Pandit wrote:
> > -Original Message-
> > From: Christophe de Dinechin
> > Subject: Re: [PATCH v2 0/2] Simplify mtty driver and mdev core
> >
> >
> > Parav Pandit writes:
> >
> > > + Dave.
> > >
> > > Hi Jiri, Dave, Alex, Kirti, Cornelia,
> >
On Fri, Aug 16, 2019 at 09:14:12AM +0200, Greg Kroah-Hartman wrote:
> On Fri, Aug 16, 2019 at 11:42:22AM +1000, Michael Ellerman wrote:
> > Greg Kroah-Hartman writes:
> > > On Thu, Aug 15, 2019 at 02:55:42PM +1000, Alastair D'Silva wrote:
> > >> From: Alastair D'Silva
> > >>
> > >> Heads Up:
Hi Ben,
> Hi Justin,
>
> > Hi Ben,
> >
> > I have similar fix locally with different approach as the command handler
> > may have some expectation for those byes.
> > We can use NCSI_PKT_CMD_OEM handler as it only copies data based on the
> > payload length.
>
> Great! Yes I was thinking
Hi!
> >No need to move ctrl_brt_pointer... to keep order consistent with docs.
>
> OK I will reset the patches and get rid of that change. I think this got
> moved when I applied the v1 patch.
>
>
> >>+ fs_current_val = led->full_scale_current - LM3532_FS_CURR_MIN /
> >>+
On Sun, Aug 18, 2019 at 09:58:05AM -0700, Deepa Dinamani wrote:
> Note that the min timestamp is assumed to be
> 01 Jan 1970 00:00:00 (Unix epoch). This is consistent
> with the way we convert timestamps in adfs_adfs2unix_time().
That's not actually correct. RISC OS timestamps are centiseconds
On Mon, 2019-08-19 at 14:08 -0500, Rob Herring wrote:
> On Mon, Aug 19, 2019 at 12:26 PM Dafna Hirschfeld
> wrote:
> > From: Gary Bisson
> >
> > The Nitrogen8M is an ARM based single board computer (SBC)
> > designed to leverage the full capabilities of NXP’s i.MX8M
> > Quad processor.
> >
> >
If hw_free() gets called after hw_params(), GCLK remains prepared,
preventing further use of it. This patch fixes this by unpreparing the
clock in hw_free() or if hw_params() gets an error.
Fixes: 7e0cdf545a55 ("ASoC: mchp-i2s-mcc: add driver for I2SC Multi-Channel
Controller")
Signed-off-by:
Since hw_free() can be called multiple times and not just after a stop
trigger command, we should check whether the RX or TX ready interrupt was
truly enabled previously. For this, we assure that the condition of the
wait event is always true, except when RX/TX interrupts are enabled.
Fixes:
This controller supports capture and playback running at the same time,
with the limitation that both capture and playback must be configured the
same way (sample rate, sample format, number of channels, etc). For this,
we have to assure that the configuration registers look the same when
capture
This pathset fixes some issues detected while testing some more the
Microchip I2S multichannel controller. The first two patches fix some
issues that appear mostly when hw_free() and hw_params() callbacks
are called multiple times. The third patch fixes a problem caused
when the controller is in
On Mon, Aug 19, 2019 at 12:30:18PM -0700, John Hubbard wrote:
> On 8/19/19 12:06 PM, Bharath Vedartham wrote:
> >On Mon, Aug 19, 2019 at 07:56:11AM -0500, Dimitri Sivanich wrote:
> >>Reviewed-by: Dimitri Sivanich
> >Thanks!
> >
> >John, would you like to take this patch into your miscellaneous
>
> Subject: Re: [PATCH v8 11/28] x86/asm/head: annotate data appropriatelly
appropriately
On Thu, Aug 08, 2019 at 12:38:37PM +0200, Jiri Slaby wrote:
> Use the new SYM_DATA, SYM_DATA_START, and SYM_DATA_END in both 32 and 64
> bit heads. In the 64-bit version, define also
>
On Tue, Aug 20, 2019 at 10:52:29AM -0500, Rob Herring wrote:
> On Tue, Aug 20, 2019 at 4:50 AM Maxime Ripard wrote:
> > On Tue, Aug 20, 2019 at 09:15:26AM +0100, Sean Young wrote:
> > > On Mon, Aug 19, 2019 at 08:26:18PM +0200, Maxime Ripard wrote:
> > > > From: Maxime Ripard
> > > >
> > > > The
On Tue, Aug 20, 2019 at 9:53 AM wrote:
>
> From: Ondrej Jirman
>
> Some PHYs require separate power supply for I/O pins in some modes
> of operation. Add phy-io-supply property, to allow enabling this
> power supply.
Perhaps since this is new, such phys should have *-supply in their nodes.
>
>
Hi,
On Tue, Aug 20, 2019 at 05:57:44PM +0200, Andrew Lunn wrote:
> On Tue, Aug 20, 2019 at 05:47:14PM +0200, Ondřej Jirman wrote:
> > Hi Andrew,
> >
> > On Tue, Aug 20, 2019 at 05:39:39PM +0200, Andrew Lunn wrote:
> > > On Tue, Aug 20, 2019 at 04:53:40PM +0200, meg...@megous.com wrote:
> > > >
On Tue, Aug 20, 2019 at 9:53 AM wrote:
>
> From: Ondrej Jirman
>
> This is already supported by the driver, but is missing from the
> bindings.
Really, the supply for the phy should be in the phy's node...
>
> Signed-off-by: Ondrej Jirman
> ---
>
On Tue, Aug 20, 2019 at 9:41 AM Neil Armstrong wrote:
>
> Add the compatible for the Amlogic SM1 Based SEI610 board.
>
> Signed-off-by: Neil Armstrong
> ---
> Documentation/devicetree/bindings/arm/amlogic.yaml | 2 ++
> 1 file changed, 2 insertions(+)
Reviewed-by: Rob Herring
On Tue, Aug 20, 2019 at 9:41 AM Neil Armstrong wrote:
>
> Add bindings for the new Amlogic SM1 SoC Family.
>
> It a derivative of the G12A SoC Family with :
> - Cortex-A55 core instead of A53
> - more power domains
> - a neural network co-processor
> - a CSI input and image processor
>
>
On Tue, 2019-08-20 at 07:36 +0200, Florian Westphal wrote:
> Wouldn't fib_netdev.c have the same problem?
Probably, but I haven't hit this issue yet.
> If so, might be better to place this test in both
> nft_fib6_eval_type and nft_fib6_eval.
I think that is possible, and not very hard to do.
But
On 2019-08-20 18:02:17 [+0200], Peter Zijlstra wrote:
> On Tue, Aug 20, 2019 at 05:54:01PM +0200, Sebastian Andrzej Siewior wrote:
> > On 2019-08-20 17:20:25 [+0200], Peter Zijlstra wrote:
>
> > > And am I right in thinking that that, again, is specific to the
> > > sleeping-spinlocks from
On Tue, Aug 20, 2019 at 07:59:54AM -0700, Randy Dunlap wrote:
> On 8/20/19 12:09 AM, Stephen Rothwell wrote:
> > Hi all,
> >
> > Changes since 20190819:
> >
>
> on i386 or x86_64:
>
> ../mm/memcontrol.c: In function ‘__mem_cgroup_free’:
> ../mm/memcontrol.c:4885:2: error: implicit declaration
set_msi_sid_cb() is used to determine whether device aliases share the
same bus, but it can provide false indications that aliases use the same
bus when in fact they do not. The reason is that set_msi_sid_cb()
assumes that pdev is fixed, while actually pci_for_each_dma_alias() can
call fn() when
On Tue, Aug 20, 2019 at 05:06:29PM +0100, Mark Rutland wrote:
> On Tue, Aug 20, 2019 at 04:57:45PM +0100, Raphael Gault wrote:
>
> It would be worth having a body for the commit message like:
>
> | in perf_event.c we use smp_processor_id(), but we haven't included
> | where it is defined, and
On Thu, Aug 15, 2019 at 10:22:07PM +0200, Thomas Gleixner wrote:
> We have the following existing _SHORT variants:
>
> _G
> _EP
> _EX
> _CORE
> _ULT
> _GT3E
> _XEON_D
> _MOBILE
> _DESKTOP
> _NNPI
> _MID
> _TABLET
> _PLUS
Your list is missing: _L and _X.
_X is the generic 'server'
And we have
On 8/20/19 4:06 AM, Kirill Tkhai wrote:
On 07.08.2019 05:17, Yang Shi wrote:
Currently THP deferred split shrinker is not memcg aware, this may cause
premature OOM with some configuration. For example the below test would
run into premature OOM easily:
$ cgcreate -g memory:thp
$ echo 4G >
On Thu, Aug 15, 2019 at 08:26:43PM +0200, Paolo Bonzini wrote:
> Oh, I see. Sorry I didn't understand the question. In the case of KVM,
> there's simply no code that runs in interrupt context and needs to use
> virtual addresses.
>
> In fact, there's no code that runs in interrupt context at all.
On 8/20/19 4:01 AM, Kirill Tkhai wrote:
On 07.08.2019 05:17, Yang Shi wrote:
Currently shrinker is just allocated and can work when memcg kmem is
enabled. But, THP deferred split shrinker is not slab shrinker, it
doesn't make too much sense to have such shrinker depend on memcg kmem.
It
On Tue, Aug 20, 2019 at 3:29 AM Rahul Tanwar
wrote:
>
> Convert the existing DT binding document for Lantiq SoC ASC serial controller
> from txt format to YAML format.
>
> Signed-off-by: Rahul Tanwar
> ---
> .../devicetree/bindings/serial/lantiq_asc.txt | 31 --
>
On Fri, Jun 14, 2019 at 01:33:47PM -0600, Rob Herring wrote:
> On Fri, Jun 14, 2019 at 11:07 AM Andreas Färber wrote:
> >
> > Am 14.06.19 um 19:04 schrieb Manivannan Sadhasivam:
> > > On Thu, Jun 13, 2019 at 04:44:35PM -0600, Rob Herring wrote:
> > >> On Fri, May 17, 2019 at 10:32:23AM -0500, Rob
On Tue, Aug 20, 2019 at 04:57:45PM +0100, Raphael Gault wrote:
It would be worth having a body for the commit message like:
| in perf_event.c we use smp_processor_id(), but we haven't included
| where it is defined, and rely on this being pulled in
| via a transitive include. Let's make this
> On Aug 20, 2019, at 7:18 AM, Dave Hansen wrote:
>
> On 8/20/19 7:14 AM, Song Liu wrote:
>>> *But*, that shouldn't get hit on a Skylake CPU since those have PCIDs
>>> and shouldn't have a global kernel image. Could you confirm whether
>>> PCIDs are supported on this CPU?
>> Yes, pcid is
On Tue, Aug 20, 2019 at 06:02:38PM +0200, Oleg Nesterov wrote:
> userfaultfd_release() should clear vm_flags/vm_userfaultfd_ctx even
> if mm->core_state != NULL.
>
> Otherwise a page fault can see userfaultfd_missing() == T and use an
> already freed userfaultfd_ctx.
>
> Reported-by: Kefeng Wang
On Tue, Aug 20, 2019 at 04:55:24PM +0100, Raphael Gault wrote:
> Hi Mark,
>
> Thank you for your comments.
>
> On 8/20/19 4:49 PM, Mark Rutland wrote:
> > On Tue, Aug 20, 2019 at 04:23:17PM +0100, Mark Rutland wrote:
> > > Hi Raphael,
> > >
> > > On Fri, Aug 16, 2019 at 01:59:31PM +0100,
userfaultfd_release() should clear vm_flags/vm_userfaultfd_ctx even
if mm->core_state != NULL.
Otherwise a page fault can see userfaultfd_missing() == T and use an
already freed userfaultfd_ctx.
Reported-by: Kefeng Wang
Fixes: 04f5866e41fb ("coredump: fix race condition between
On Tue, Aug 20, 2019 at 05:54:01PM +0200, Sebastian Andrzej Siewior wrote:
> On 2019-08-20 17:20:25 [+0200], Peter Zijlstra wrote:
> > And am I right in thinking that that, again, is specific to the
> > sleeping-spinlocks from PREEMPT_RT? Is there really nothing else that
> > identifies those
On Tue, Aug 20, 2019 at 3:29 AM Rahul Tanwar
wrote:
>
> Intel Lightning Mountain(LGM) SoC reuses Lantiq ASC serial controller IP.
> Update the dt bindings to support LGM as well.
>
> Signed-off-by: Rahul Tanwar
> ---
> .../devicetree/bindings/serial/lantiq_asc.yaml | 17
>
Hi Bartlomiej,
Thank you very much for your review!
Question below.
On 08/20/2019 02:06 PM, Bartlomiej Zolnierkiewicz wrote:
>> +/* Workaround for X-Surf: Save drvdata in case zorro8390 has set it */
>> +old_drvdata = dev_get_drvdata(>dev);
>
> This should be done only for type ==
On 20.08.2019 18:35, Alexander Duyck wrote:
> On Tue, Aug 20, 2019 at 8:18 AM Ilya Maximets wrote:
>>
>> Tx code doesn't clear the descriptor status after cleaning.
>> So, if the budget is larger than number of used elems in a ring, some
>> descriptors will be accounted twice and
On Tue 20 Aug 2019 at 17:39, Philipp Zabel wrote:
> Hi Jerome,
>
> thank you for the patch. Just one nitpick and one real issue below:
>
> On Tue, 2019-08-20 at 11:46 +0200, Jerome Brunet wrote:
>> Add the new arb reset lines of the SM1 SoC family
>>
>> Signed-off-by: Jerome Brunet
>> ---
>>
On Tue, Aug 20, 2019 at 05:47:14PM +0200, Ondřej Jirman wrote:
> Hi Andrew,
>
> On Tue, Aug 20, 2019 at 05:39:39PM +0200, Andrew Lunn wrote:
> > On Tue, Aug 20, 2019 at 04:53:40PM +0200, meg...@megous.com wrote:
> > > From: Ondrej Jirman
> > >
> > > Use devm_regulator_get instead of
Acked-by: Mark Rutland
Signed-off-by: Raphael Gault
---
arch/arm64/kernel/perf_event.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index 96e90e270042..24575c0a0065 100644
--- a/arch/arm64/kernel/perf_event.c
+++
On Tue, Aug 20, 2019 at 05:39:39PM +0200, Andrew Lunn wrote:
> On Tue, Aug 20, 2019 at 04:53:40PM +0200, meg...@megous.com wrote:
> > From: Ondrej Jirman
> >
> > Use devm_regulator_get instead of devm_regulator_get_optional and rely
> > on dummy supply. This avoids NULL checks before
Hi Mark,
Thank you for your comments.
On 8/20/19 4:49 PM, Mark Rutland wrote:
On Tue, Aug 20, 2019 at 04:23:17PM +0100, Mark Rutland wrote:
Hi Raphael,
On Fri, Aug 16, 2019 at 01:59:31PM +0100, Raphael Gault wrote:
This feature is required in order to enable PMU counters direct
access from
On 8/19/19 11:20 AM, Maxime Ripard wrote:
From: Maxime Ripard
The watchdogs have a bunch of generic properties that are needed in a
device tree. Add a YAML schemas for those.
Signed-off-by: Maxime Ripard
What is the target subsystem for this series ? You didn't copy the watchdog
mailing
Hi Luis,
I'm glad you are a subject expert in this area.
Some more comments inline.
On 2019-08-19 6:26 p.m., Luis Chamberlain wrote:
On Mon, Aug 19, 2019 at 09:19:51AM -0700, Scott Branden wrote:
To be honest, I find the entire firmware code sloppy.
And that is after years of cleanup on my
On Tue, Aug 20, 2019 at 5:31 AM Ramuthevar,Vadivel MuruganX
wrote:
>
> From: Ramuthevar Vadivel Murugan
>
> Add a YAML schema to use the host controller driver with the
> eMMC PHY on Intel's Lightning Mountain SoC.
>
> Signed-off-by: Ramuthevar Vadivel Murugan
>
> ---
> changes in v2:
> As
On Tue, Aug 20, 2019 at 05:40:11PM +0200, Peter Zijlstra wrote:
> > _ULT
> > _MOBILE
>
> I suspect these two are the same.
for i in `git grep -l "INTEL_FAM6_.*_MOBILE"`
do
sed -i -e 's/\(INTEL_FAM6_.*\)_MOBILE/\1_ULT/g' ${i}
done
---
arch/x86/events/intel/core.c | 16
On 2019-08-20 17:20:25 [+0200], Peter Zijlstra wrote:
> > There isc RCU (boosting) and futex. I'm sceptical about the i2c users…
>
> Well, yes, I too was/am sceptical, but it was tglx who twisted my arm
> and said the i2c people were right and rt_mutex is/should-be a generic
> usable interface.
Pavel
On 8/19/19 5:48 AM, Pavel Machek wrote:
On Tue 2019-08-13 13:11:51, Dan Murphy wrote:
Fix the brightness control for I2C mode. Instead of
changing the full scale current register update the ALS target
register for the appropriate banks.
In addition clean up some code errors and random
On Tue, Aug 20, 2019 at 4:50 AM Maxime Ripard wrote:
>
> Hi Sean,
>
> On Tue, Aug 20, 2019 at 09:15:26AM +0100, Sean Young wrote:
> > On Mon, Aug 19, 2019 at 08:26:18PM +0200, Maxime Ripard wrote:
> > > From: Maxime Ripard
> > >
> > > The RC controllers have a bunch of generic properties that
Pavel
Thanks for the review
On 8/19/19 5:55 AM, Pavel Machek wrote:
Hi!
Allow the full scale current to be configured at init.
Valid rangles are 5mA->29.8mA.
Signed-off-by: Dan Murphy
@@ -121,6 +125,7 @@ struct lm3532_als_data {
* @mode - Mode of the LED string
* @ctrl_brt_pointer -
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