[PATCH v9 2/2] memory tier: create CPUless memory tiers after obtaining HMAT info

2024-03-28 Thread Ho-Ren (Jack) Chuang
The current implementation treats emulated memory devices, such as CXL1.1 type3 memory, as normal DRAM when they are emulated as normal memory (E820_TYPE_RAM). However, these emulated devices have different characteristics than traditional DRAM, making it important to distinguish them. Thus, we

[PATCH v9 1/2] memory tier: dax/kmem: introduce an abstract layer for finding, allocating, and putting memory types

2024-03-28 Thread Ho-Ren (Jack) Chuang
Since different memory devices require finding, allocating, and putting memory types, these common steps are abstracted in this patch, enhancing the scalability and conciseness of the code. Signed-off-by: Ho-Ren (Jack) Chuang Reviewed-by: "Huang, Ying" --- drivers/dax/kmem.c | 20

[PATCH v9 0/2] Improved Memory Tier Creation for CPUless NUMA Nodes

2024-03-28 Thread Ho-Ren (Jack) Chuang
When a memory device, such as CXL1.1 type3 memory, is emulated as normal memory (E820_TYPE_RAM), the memory device is indistinguishable from normal DRAM in terms of memory tiering with the current implementation. The current memory tiering assigns all detected normal memory nodes to the same DRAM

Re: [PATCH v3] vhost/vdpa: Add MSI translation tables to iommu for software-managed MSI

2024-03-28 Thread Jason Wang
On Wed, Mar 27, 2024 at 5:08 PM Jason Wang wrote: > > On Thu, Mar 21, 2024 at 3:00 PM Michael S. Tsirkin wrote: > > > > On Wed, Mar 20, 2024 at 06:19:12PM +0800, Wang Rong wrote: > > > From: Rong Wang > > > > > > Once enable iommu domain for one device, the MSI > > > translation tables have to

[PATCH net-next v3 3/3] tcp: add location into reset trace process

2024-03-28 Thread Jason Xing
From: Jason Xing In addition to knowing the 4-tuple of the flow which generates RST, the reason why it does so is very important because we have some cases where the RST should be sent and have no clue which one exactly. Adding location of reset process can help us more, like what

[PATCH net-next v3 2/3] trace: tcp: fully support trace_tcp_send_reset

2024-03-28 Thread Jason Xing
From: Jason Xing Prior to this patch, what we can see by enabling trace_tcp_send is only happening under two circumstances: 1) active rst mode 2) non-active rst mode and based on the full socket That means the inconsistency occurs if we use tcpdump and trace simultaneously to see how rst

[PATCH net-next v3 1/3] trace: adjust TP_STORE_ADDR_PORTS_SKB() parameters

2024-03-28 Thread Jason Xing
From: Jason Xing Introducing entry_saddr and entry_daddr parameters in this macro for later use can help us record the reverse 4-tuple by analyzing the 4-tuple of the incoming skb when receiving. Signed-off-by: Jason Xing --- include/trace/events/tcp.h | 21 +++-- 1 file

[PATCH net-next v3 0/3] tcp: make trace of reset logic complete

2024-03-28 Thread Jason Xing
From: Jason Xing Before this, we miss some cases where the TCP layer could send RST but we cannot trace it. So I decided to complete it :) v3 1. fix a format problem in patch [3/3] v2 1. fix spelling mistakes Jason Xing (3): trace: adjust TP_STORE_ADDR_PORTS_SKB() parameters trace: tcp:

Re: [PATCH] trace/sched: add tgid for sched_wakeup_template

2024-03-28 Thread 张元瀚 Tio Zhang
Make sense to me, thank you for your explanation. On 3/27/24, 10:24 PM, "Steven Rostedt" mailto:rost...@goodmis.org>> wrote: On Wed, 27 Mar 2024 16:50:57 +0800 Tio Zhang mailto:tiozh...@didiglobal.com>> wrote: > By doing this, we are able to filter tasks by tgid while we are > tracing wakeup

Re: [PATCH net-next v2 3/3] tcp: add location into reset trace process

2024-03-28 Thread Jason Xing
On Fri, Mar 29, 2024 at 9:15 AM Jakub Kicinski wrote: > > On Tue, 26 Mar 2024 12:08:01 +0100 Paolo Abeni wrote: > > > - TP_PROTO(const struct sock *sk, const struct sk_buff *skb), > > > + TP_PROTO( > > > + const struct sock *sk, > > > + const struct sk_buff *skb, > > > +

Re: [External] Re: [PATCH v8 2/2] memory tier: create CPUless memory tiers after obtaining HMAT info

2024-03-28 Thread Ho-Ren (Jack) Chuang
On Thu, Mar 28, 2024 at 5:59 PM Huang, Ying wrote: > > "Ho-Ren (Jack) Chuang" writes: > > > The current implementation treats emulated memory devices, such as > > CXL1.1 type3 memory, as normal DRAM when they are emulated as normal memory > > (E820_TYPE_RAM). However, these emulated devices have

Re: [PATCH net v2 1/2] virtio_net: Do not set rss_indir if RSS is not supported

2024-03-28 Thread Heng Qi
在 2024/3/28 下午10:37, Breno Leitao 写道: On Wed, Mar 27, 2024 at 09:37:43AM +0800, Xuan Zhuo wrote: On Tue, 26 Mar 2024 08:19:08 -0700, Breno Leitao wrote: Do not set virtnet_info->rss_indir_table_size if RSS is not available for the device. Currently, rss_indir_table_size is set if either

Re: [PATCH net-next v2 3/3] tcp: add location into reset trace process

2024-03-28 Thread Jakub Kicinski
On Tue, 26 Mar 2024 12:08:01 +0100 Paolo Abeni wrote: > > - TP_PROTO(const struct sock *sk, const struct sk_buff *skb), > > + TP_PROTO( > > + const struct sock *sk, > > + const struct sk_buff *skb, > > + void *location), > > Very minor nit: the above lines

Re: [PATCH v8 2/2] memory tier: create CPUless memory tiers after obtaining HMAT info

2024-03-28 Thread Huang, Ying
"Ho-Ren (Jack) Chuang" writes: > The current implementation treats emulated memory devices, such as > CXL1.1 type3 memory, as normal DRAM when they are emulated as normal memory > (E820_TYPE_RAM). However, these emulated devices have different > characteristics than traditional DRAM, making it

[PATCH v8 1/2] memory tier: dax/kmem: introduce an abstract layer for finding, allocating, and putting memory types

2024-03-28 Thread Ho-Ren (Jack) Chuang
Since different memory devices require finding, allocating, and putting memory types, these common steps are abstracted in this patch, enhancing the scalability and conciseness of the code. Signed-off-by: Ho-Ren (Jack) Chuang Reviewed-by: "Huang, Ying" --- drivers/dax/kmem.c | 20

[PATCH v8 2/2] memory tier: create CPUless memory tiers after obtaining HMAT info

2024-03-28 Thread Ho-Ren (Jack) Chuang
The current implementation treats emulated memory devices, such as CXL1.1 type3 memory, as normal DRAM when they are emulated as normal memory (E820_TYPE_RAM). However, these emulated devices have different characteristics than traditional DRAM, making it important to distinguish them. Thus, we

[PATCH v8 0/2] Improved Memory Tier Creation for CPUless NUMA Nodes

2024-03-28 Thread Ho-Ren (Jack) Chuang
When a memory device, such as CXL1.1 type3 memory, is emulated as normal memory (E820_TYPE_RAM), the memory device is indistinguishable from normal DRAM in terms of memory tiering with the current implementation. The current memory tiering assigns all detected normal memory nodes to the same DRAM

[PATCH v7 0/2] Improved Memory Tier Creation for CPUless NUMA Nodes

2024-03-28 Thread Ho-Ren (Jack) Chuang
When a memory device, such as CXL1.1 type3 memory, is emulated as normal memory (E820_TYPE_RAM), the memory device is indistinguishable from normal DRAM in terms of memory tiering with the current implementation. The current memory tiering assigns all detected normal memory nodes to the same DRAM

[RESEND v5 2/2] tracing: Include Microcode Revision in mce_record tracepoint

2024-03-28 Thread Avadhut Naik
Currently, the microcode field (Microcode Revision) of struct mce is not exported to userspace through the mce_record tracepoint. Knowing the microcode version on which the MCE was received is critical information for debugging. If the version is not recorded, later attempts to acquire the

[RESEND v5 1/2] tracing: Include PPIN in mce_record tracepoint

2024-03-28 Thread Avadhut Naik
Machine Check Error information from struct mce is exported to userspace through the mce_record tracepoint. Currently, however, the PPIN (Protected Processor Inventory Number) field of struct mce is not exported through the tracepoint. Export PPIN through the tracepoint as it provides a unique

[RESEND v5 0/2] Update mce_record tracepoint

2024-03-28 Thread Avadhut Naik
This patchset updates the mce_record tracepoint so that the recently added fields of struct mce are exported through it to userspace. The first patch adds PPIN (Protected Processor Inventory Number) field to the tracepoint. The second patch adds the microcode field (Microcode Revision) to the

Re: [PATCH v5 0/2] Update mce_record tracepoint

2024-03-28 Thread Naik, Avadhut
On 3/28/2024 13:14, Sohil Mehta wrote: > On 3/28/2024 11:04 AM, Avadhut Naik wrote: > >> - Since only caps of words which are not acronyms have been changed in >>this version and the word "REVISION" has been removed i.e. changes are >>very minor, have retained the the below tags

Re: [PATCH v5 0/2] Update mce_record tracepoint

2024-03-28 Thread Sohil Mehta
On 3/28/2024 11:04 AM, Avadhut Naik wrote: > - Since only caps of words which are not acronyms have been changed in >this version and the word "REVISION" has been removed i.e. changes are >very minor, have retained the the below tags received for previous >versions: >

[PATCH v5 1/2] tracing: Include PPIN in mce_record tracepoint

2024-03-28 Thread Avadhut Naik
Machine Check Error information from struct mce is exported to userspace through the mce_record tracepoint. Currently, however, the PPIN (Protected Processor Inventory Number) field of struct mce is not exported through the tracepoint. Export PPIN through the tracepoint as it provides a unique

[PATCH v5 2/2] tracing: Include Microcode Revision in mce_record tracepoint

2024-03-28 Thread Avadhut Naik
Currently, the microcode field (Microcode Revision) of struct mce is not exported to userspace through the mce_record tracepoint. Knowing the microcode version on which the MCE was received is critical information for debugging. If the version is not recorded, later attempts to acquire the

[PATCH v5 0/2] Update mce_record tracepoint

2024-03-28 Thread Avadhut Naik
This patchset updates the mce_record tracepoint so that the recently added fields of struct mce are exported through it to userspace. The first patch adds PPIN (Protected Processor Inventory Number) field to the tracepoint. The second patch adds the microcode field (Microcode Revision) to the

Re: [PATCH 1/3] remoteproc: k3-dsp: Fix usage of omap_mbox_message and mbox_msg_t

2024-03-28 Thread Andrew Davis
On 3/28/24 10:28 AM, Mathieu Poirier wrote: Hi Andrew, On Mon, Mar 25, 2024 at 11:58:06AM -0500, Andrew Davis wrote: The type of message sent using omap-mailbox is always u32. The definition of mbox_msg_t is uintptr_t which is wrong as that type changes based on the architecture (32bit vs

Re: [PATCH v4 2/2] tracing: Include Microcode Revision in mce_record tracepoint

2024-03-28 Thread Borislav Petkov
On Thu, Mar 28, 2024 at 01:17:43AM -0500, Naik, Avadhut wrote: > SOCKET -> Socket > PROCESSOR -> Processor > MICROCODE -> Microcode SOCKET -> socket PROCESSOR -> processor MICROCODE -> microcode And yeah, the acronyms need to obviously stay in all caps. Thx. -- Regards/Gruss, Boris.

Re: [PATCH 1/3] remoteproc: k3-dsp: Fix usage of omap_mbox_message and mbox_msg_t

2024-03-28 Thread Mathieu Poirier
Hi Andrew, On Mon, Mar 25, 2024 at 11:58:06AM -0500, Andrew Davis wrote: > The type of message sent using omap-mailbox is always u32. The definition > of mbox_msg_t is uintptr_t which is wrong as that type changes based on > the architecture (32bit vs 64bit). Use u32 unconditionally and remove >

Re: [PATCH 2/2] remoteproc: mediatek: Don't parse extraneous subnodes for multi-core

2024-03-28 Thread Mathieu Poirier
On Wed, Mar 27, 2024 at 01:49:58PM +0100, AngeloGioacchino Del Regno wrote: > Il 21/03/24 16:27, Mathieu Poirier ha scritto: > > On Thu, Mar 21, 2024 at 09:46:14AM +0100, AngeloGioacchino Del Regno wrote: > > > When probing multi-core SCP, this driver is parsing all sub-nodes of > > > the

Re: [PATCH net v2 1/2] virtio_net: Do not set rss_indir if RSS is not supported

2024-03-28 Thread Breno Leitao
> > On Wed, Mar 27, 2024 at 09:37:43AM +0800, Xuan Zhuo wrote: > > > On Tue, 26 Mar 2024 08:19:08 -0700, Breno Leitao > > > wrote: > > > > Do not set virtnet_info->rss_indir_table_size if RSS is not available > > > > for the device. > > > > > > > > Currently, rss_indir_table_size is set if

[RFC PATCH] ftrace: riscv: move from REGS to ARGS

2024-03-28 Thread Puranjay Mohan
This commit replaces riscv's support for FTRACE_WITH_REGS with support for FTRACE_WITH_ARGS. This is required for the ongoing effort to stop relying on stop_machine() for RISCV's implementation of ftrace. The main relevant benefit that this change will bring for the above use-case is that now we

[PATCH 00/11] address remaining stringop-truncation warnings

2024-03-28 Thread Arnd Bergmann
From: Arnd Bergmann We are close to being able to turn on -Wstringop-truncation unconditionally instead of only at the 'make W=1' level, these ten warnings are all that I saw in randconfig testing across compiler versions on arm, arm64 and x86. The final patch is only there for reference at the

[PATCH RFC 04/10] mm: page_frag: add '_va' suffix to page_frag API

2024-03-28 Thread Yunsheng Lin
Currently most of the API for page_frag API is returning 'virtual address' as output or expecting 'virtual address' as input, in order to differentiate the API handling between 'virtual address' and 'struct page', add '_va' suffix to the corresponding API mirroring the page_pool_alloc_va() API of

Re: [PATCH v10 05/14] x86/sgx: Implement basic EPC misc cgroup functionality

2024-03-28 Thread Huang, Kai
> --- /dev/null > +++ b/arch/x86/kernel/cpu/sgx/epc_cgroup.c > @@ -0,0 +1,74 @@ > +// SPDX-License-Identifier: GPL-2.0 > +// Copyright(c) 2022 Intel Corporation. It's 2024 now. And looks you need to use C style comment for /* Copyright ... */, after looking at some other C files. > + >

Re: [PATCH v7 2/2] arch/riscv: Enable kprobes when CONFIG_MODULES=n

2024-03-28 Thread Christophe Leroy
Le 26/03/2024 à 14:46, Jarkko Sakkinen a écrit : > Tacing with kprobes while running a monolithic kernel is currently > impossible due the kernel module allocator dependency. > > Address the issue by implementing textmem API for RISC-V. > > Link: https://www.sochub.fi # for power on testing

Re: [PATCH v7 1/2] kprobes: Implement trampoline memory allocator for tracing

2024-03-28 Thread Christophe Leroy
Le 26/03/2024 à 14:46, Jarkko Sakkinen a écrit : > Tracing with kprobes while running a monolithic kernel is currently > impossible because CONFIG_KPROBES depends on CONFIG_MODULES. > > Introduce alloc_execmem() and free_execmem() for allocating executable > memory. If an arch implements these

Re: [PATCH v3 2/3] vhost: Add smp_rmb() in vhost_enable_notify()

2024-03-28 Thread Stefano Garzarella
On Thu, Mar 28, 2024 at 10:21:48AM +1000, Gavin Shan wrote: A smp_rmb() has been missed in vhost_enable_notify(), inspired by Will. Otherwise, it's not ensured the available ring entries pushed by guest can be observed by vhost in time, leading to stale available ring entries fetched by vhost in

Re: [PATCH v3 1/3] vhost: Add smp_rmb() in vhost_vq_avail_empty()

2024-03-28 Thread Stefano Garzarella
On Thu, Mar 28, 2024 at 10:21:47AM +1000, Gavin Shan wrote: A smp_rmb() has been missed in vhost_vq_avail_empty(), spotted by Will. Otherwise, it's not ensured the available ring entries pushed by guest can be observed by vhost in time, leading to stale available ring entries fetched by vhost in

Re: [PATCH v3 3/3] vhost: Improve vhost_get_avail_idx() with smp_rmb()

2024-03-28 Thread Michael S. Tsirkin
On Thu, Mar 28, 2024 at 10:21:49AM +1000, Gavin Shan wrote: > All the callers of vhost_get_avail_idx() are concerned to the memory > barrier, imposed by smp_rmb() to ensure the order of the available > ring entry read and avail_idx read. > > Improve vhost_get_avail_idx() so that smp_rmb() is

Re: [PATCH v2 1/1] vhost: Added pad cleanup if vnet_hdr is not present.

2024-03-28 Thread Andrew Melnichenko
Thanks, I'll look into it. On Thu, Mar 28, 2024 at 6:03 AM Jason Wang wrote: > > On Thu, Mar 28, 2024 at 7:44 AM Andrew Melnychenko wrote: > > > > When the Qemu launched with vhost but without tap vnet_hdr, > > vhost tries to copy vnet_hdr from socket iter with size 0 > > to the page that may

Re: [External] Re: [PATCH v6 2/2] memory tier: create CPUless memory tiers after obtaining HMAT info

2024-03-28 Thread Ho-Ren (Jack) Chuang
On Wed, Mar 27, 2024 at 6:37 PM Huang, Ying wrote: > > "Ho-Ren (Jack) Chuang" writes: > > [snip] > > > @@ -655,6 +672,34 @@ void mt_put_memory_types(struct list_head > > *memory_types) > > } > > EXPORT_SYMBOL_GPL(mt_put_memory_types); > > > > +/* > > + * This is invoked via `late_initcall()`

[PATCH v4 2/2] tracing: Include Microcode Revision in mce_record tracepoint

2024-03-28 Thread Naik, Avadhut
On 3/27/2024 17:35, Borislav Petkov wrote: > On Wed, Mar 27, 2024 at 03:31:01PM -0700, Sohil Mehta wrote: >> On 3/27/2024 1:54 PM, Avadhut Naik wrote: >> >>> - TP_printk("CPU: %d, MCGc/s: %llx/%llx, MC%d: %016Lx, IPID: %016Lx, >>> ADDR/MISC/SYND: %016Lx/%016Lx/%016Lx, RIP: %02x:<%016Lx>,

Re: [PATCH v4 2/2] tracing: Include Microcode Revision in mce_record tracepoint

2024-03-28 Thread Naik, Avadhut
On 3/27/2024 17:31, Sohil Mehta wrote: > On 3/27/2024 1:54 PM, Avadhut Naik wrote: > >> -TP_printk("CPU: %d, MCGc/s: %llx/%llx, MC%d: %016Lx, IPID: %016Lx, >> ADDR/MISC/SYND: %016Lx/%016Lx/%016Lx, RIP: %02x:<%016Lx>, TSC: %llx, PPIN: >> %llx, PROCESSOR: %u:%x, TIME: %llu, SOCKET: %u,