Re: [PATCH 1/1] PCI: iproc: Invalidate PAXB address mapping before programming it

Hi Lorenzo, Please see my comments inline: On Tue, Oct 15, 2019 at 10:13 PM Lorenzo Pieralisi wrote: > > On Fri, Sep 06, 2019 at 09:28:13AM +0530, Abhishek Shah wrote: > > Invalidate PAXB inbound/outbound address mapping each time before > > programming it. This is helpful f

Re: [PATCH 1/1] PCI: iproc: Invalidate PAXB address mapping before programming it

Hi Bjorn/Lorenzo, Can you please help review this patch? Regards, Abhishek On Fri, Sep 6, 2019 at 7:41 PM Abhishek Shah wrote: > > Hi Andrew, > > > On Fri, Sep 6, 2019 at 3:31 PM Andrew Murray wrote: > > > > On Fri, Sep 06, 2019 at 02:55:19PM +0530, Abhishek

Re: [PATCH 1/1] PCI: iproc: Invalidate PAXB address mapping before programming it

Hi Andrew, On Fri, Sep 6, 2019 at 3:31 PM Andrew Murray wrote: > > On Fri, Sep 06, 2019 at 02:55:19PM +0530, Abhishek Shah wrote: > > Hi Andrew, > > > > Thanks for the review. Please see my response inline: > > > > On Fri, Sep 6, 2019 at 2:08 PM Andrew Murra

Re: [PATCH 1/1] PCI: iproc: Invalidate PAXB address mapping before programming it

Hi Andrew, Thanks for the review. Please see my response inline: On Fri, Sep 6, 2019 at 2:08 PM Andrew Murray wrote: > > On Fri, Sep 06, 2019 at 09:28:13AM +0530, Abhishek Shah wrote: > > Invalidate PAXB inbound/outbound address mapping each time before > > programming i

[PATCH 1/1] PCI: iproc: Invalidate PAXB address mapping before programming it

Invalidate PAXB inbound/outbound address mapping each time before programming it. This is helpful for the cases where we need to reprogram inbound/outbound address mapping without resetting PAXB. kexec kernel is one such example. Signed-off-by: Abhishek Shah Reviewed-by: Ray Jui Reviewed

timer-sp804: sched_clock: issue after first suspend

Hi Daniel/Thomas/All, One of our arm64 SoCs have 4 instances of sp804 timers apart form the architecture timer. The arch timer (implemented in "drivers/clocksource/arm_arch_timer.c") is being used as clocksource (-done with clocksource_register_hz callback) as well as sched_clock

timer-sp804: sched_clock: issue after first suspend

Hi Daniel/Thomas/All, One of our arm64 SoCs have 4 instances of sp804 timers apart form the architecture timer. The arch timer (implemented in "drivers/clocksource/arm_arch_timer.c") is being used as clocksource (-done with clocksource_register_hz callback) as well as sched_clock

Re: Add hierarchical irq_domain for i2c based gpio expander pca9505

+BCM kernel feedback. Sorry for duplicated mails, had HTML formatting issue. On Wed, Oct 11, 2017 at 5:50 PM, Abhishek Shah <abhishek.s...@broadcom.com> wrote: > Hi Linus, > > I am facing one issue, where; while disabling/ masking interrupts just > before kexec reboot, acces

Re: Add hierarchical irq_domain for i2c based gpio expander pca9505

+BCM kernel feedback. Sorry for duplicated mails, had HTML formatting issue. On Wed, Oct 11, 2017 at 5:50 PM, Abhishek Shah wrote: > Hi Linus, > > I am facing one issue, where; while disabling/ masking interrupts just > before kexec reboot, access to gpio expander pca9505 residing ov

Add hierarchical irq_domain for i2c based gpio expander pca9505

Hi Linus, I am facing one issue, where; while disabling/ masking interrupts just before kexec reboot, access to gpio expander pca9505 residing over i2c bus hangs, because i2c interrupts are disabled prior to writing pca9505 register. In our chip, we have 3 irq_domain, namely gicv3,

Add hierarchical irq_domain for i2c based gpio expander pca9505

Hi Linus, I am facing one issue, where; while disabling/ masking interrupts just before kexec reboot, access to gpio expander pca9505 residing over i2c bus hangs, because i2c interrupts are disabled prior to writing pca9505 register. In our chip, we have 3 irq_domain, namely gicv3,

Re: [PATCH v2] nvme-pci: Use PCI bus address for data/queues in CMB

yes, this patch works for our platform. On Wed, Oct 4, 2017 at 12:00 PM, Christoph Hellwig wrote: > On Mon, Oct 02, 2017 at 11:21:29AM -0600, Keith Busch wrote: >> Yah, calling this a DMA address was a misnomer and confusing. > > Abhishek, can you test if this works for you?

Re: [PATCH v2] nvme-pci: Use PCI bus address for data/queues in CMB

yes, this patch works for our platform. On Wed, Oct 4, 2017 at 12:00 PM, Christoph Hellwig wrote: > On Mon, Oct 02, 2017 at 11:21:29AM -0600, Keith Busch wrote: >> Yah, calling this a DMA address was a misnomer and confusing. > > Abhishek, can you test if this works for you?

[PATCH v2] nvme-pci: Use PCI bus address for data/queues in CMB

, as well as on x86 platform, which has 1:1 outbound mapping. Fixes: 8ffaadf7 ("NVMe: Use CMB for the IO SQes if available") Cc: sta...@vger.kernel.org Signed-off-by: Abhishek Shah <abhishek.s...@broadcom.com> Reviewed-by: Anup Patel <anup.pa...@broadcom.com> Rev

[PATCH v2] nvme-pci: Use PCI bus address for data/queues in CMB

, as well as on x86 platform, which has 1:1 outbound mapping. Fixes: 8ffaadf7 ("NVMe: Use CMB for the IO SQes if available") Cc: sta...@vger.kernel.org Signed-off-by: Abhishek Shah Reviewed-by: Anup Patel Reviewed-by: Ray Jui Reviewed-by: Scott Branden --- drivers/nvme/host/

Re: [PATCH] nvme-pci: Use PCI bus address for data/queues in CMB

Hi Keith, On Fri, Sep 29, 2017 at 8:12 PM, Keith Busch <keith.bu...@intel.com> wrote: > > On Fri, Sep 29, 2017 at 10:59:26AM +0530, Abhishek Shah wrote: > > Currently, NVMe PCI host driver is programming CMB dma address as > > I/O SQs addresses. This results in failu

Re: [PATCH] nvme-pci: Use PCI bus address for data/queues in CMB

Hi Keith, On Fri, Sep 29, 2017 at 8:12 PM, Keith Busch wrote: > > On Fri, Sep 29, 2017 at 10:59:26AM +0530, Abhishek Shah wrote: > > Currently, NVMe PCI host driver is programming CMB dma address as > > I/O SQs addresses. This results in failures on systems where 1:1 &g

[PATCH] nvme-pci: Use PCI bus address for data/queues in CMB

, as well as on x86 platform, which has 1:1 outbound mapping. Fixes: 8ffaadf7 ("NVMe: Use CMB for the IO SQes if available") Cc: sta...@vger.kernel.org Signed-off-by: Abhishek Shah <abhishek.s...@broadcom.com> Reviewed-by: Anup Patel <anup.pa...@broadcom.com> Rev

[PATCH] nvme-pci: Use PCI bus address for data/queues in CMB

, as well as on x86 platform, which has 1:1 outbound mapping. Fixes: 8ffaadf7 ("NVMe: Use CMB for the IO SQes if available") Cc: sta...@vger.kernel.org Signed-off-by: Abhishek Shah Reviewed-by: Anup Patel Reviewed-by: Ray Jui Reviewed-by: Scott Branden --- drivers/nvme/host/

[PATCH 5/7] arm64: dts: Add SATA DT nodes for Stingray SoC

From: Srinath Mannam Add DT nodes for SATA host controllers and SATA PHYs on Stingray SoC Signed-off-by: Srinath Mannam Reviewed-by: Ray Jui Reviewed-by: Scott Branden ---

[PATCH 7/7] arm64: dts: Add SBA-RAID DT nodes for Stingray SoC

From: Anup Patel This patch adds Broadcom SBA-RAID DT nodes for Stingray SoC. The Stingray SoC has total 32 SBA-RAID FlexRM rings and it has 8 CPUs so we create 8 SBA-RAID instances (one for each CPU). This way Linux DMAENGINE will have one SBA-RAID DMA device for each

[PATCH 6/7] arm64: dts: Add FlexRM DT nodes for Stingray

From: Anup Patel We have two instances of FlexRM on Stingray. One for SBA RAID offload engine and another for SPU2 Crypto offload engine. This patch adds FlexRM mailbox controller DT nodes for Stingray. Signed-off-by: Anup Patel Signed-off-by:

[PATCH 5/7] arm64: dts: Add SATA DT nodes for Stingray SoC

From: Srinath Mannam Add DT nodes for SATA host controllers and SATA PHYs on Stingray SoC Signed-off-by: Srinath Mannam Reviewed-by: Ray Jui Reviewed-by: Scott Branden --- .../boot/dts/broadcom/stingray/bcm958742-base.dtsi | 64 + .../boot/dts/broadcom/stingray/stingray-sata.dtsi |

[PATCH 7/7] arm64: dts: Add SBA-RAID DT nodes for Stingray SoC

From: Anup Patel This patch adds Broadcom SBA-RAID DT nodes for Stingray SoC. The Stingray SoC has total 32 SBA-RAID FlexRM rings and it has 8 CPUs so we create 8 SBA-RAID instances (one for each CPU). This way Linux DMAENGINE will have one SBA-RAID DMA device for each CPU. Signed-off-by: Anup

[PATCH 6/7] arm64: dts: Add FlexRM DT nodes for Stingray

From: Anup Patel We have two instances of FlexRM on Stingray. One for SBA RAID offload engine and another for SPU2 Crypto offload engine. This patch adds FlexRM mailbox controller DT nodes for Stingray. Signed-off-by: Anup Patel Signed-off-by: Raveendra Padasalagi ---

[PATCH 3/7] arm64: dts: Add sp804 DT nodes for Stingray SoC

From: Anup Patel We have 8 instances of sp804 in Stingray SoC. Let's enable it in Stingray DT. Signed-off-by: Anup Patel Reviewed-by: Ray Jui Reviewed-by: Scott Branden ---

[PATCH 4/7] arm64: dts: Add DT node to enable BGMAC driver on Stingray

This patch adds DT node to enable BGMAC driver on Stingray Signed-off-by: Abhishek Shah <abhishek.s...@broadcom.com> Reviewed-by: Ray Jui <ray@broadcom.com> Reviewed-by: Oza Oza <oza@broadcom.com> Reviewed-by: Scott Branden <scott.bran...@broadcom.com> --- arch

[PATCH 3/7] arm64: dts: Add sp804 DT nodes for Stingray SoC

From: Anup Patel We have 8 instances of sp804 in Stingray SoC. Let's enable it in Stingray DT. Signed-off-by: Anup Patel Reviewed-by: Ray Jui Reviewed-by: Scott Branden --- .../arm64/boot/dts/broadcom/stingray/stingray.dtsi | 87 ++ 1 file changed, 87 insertions(+) diff

[PATCH 4/7] arm64: dts: Add DT node to enable BGMAC driver on Stingray

This patch adds DT node to enable BGMAC driver on Stingray Signed-off-by: Abhishek Shah Reviewed-by: Ray Jui Reviewed-by: Oza Oza Reviewed-by: Scott Branden --- arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi | 14 ++ arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts

[PATCH 2/7] arm64: dts: Add MDIO multiplexer DT node for Stingray

From: Srinath Mannam Added MDIO multiplexer iproc DT node for Stingray, which contains the child nodes of PCIe serdes, RGMII, SATA and USB phy MDIO slaves. Signed-off-by: Srinath Mannam Reviewed-by: Ray Jui

[PATCH 0/7] Add more DT nodes for Stingray SoC

This is round two of adding DT nodes for Stingray SoC. Corresponding drivers and dt binding documents are already checked in the kernel and will be present in v4.14. Abhishek Shah (1): arm64: dts: Add DT node to enable BGMAC driver on Stingray Anup Patel (3): arm64: dts: Add sp804 DT nodes

[PATCH 1/7] arm64: dts: Enable stats for CCN-502 interconnect on Stingray

From: Velibor Markovski This patch enables stats for CCN-502 interconnect on Stingray. Signed-off-by: Velibor Markovski Reviewed-by: Ray Jui Reviewed-by: Scott Branden ---

[PATCH 2/7] arm64: dts: Add MDIO multiplexer DT node for Stingray

From: Srinath Mannam Added MDIO multiplexer iproc DT node for Stingray, which contains the child nodes of PCIe serdes, RGMII, SATA and USB phy MDIO slaves. Signed-off-by: Srinath Mannam Reviewed-by: Ray Jui Reviewed-by: Scott Branden --- .../arm64/boot/dts/broadcom/stingray/stingray.dtsi |

[PATCH 0/7] Add more DT nodes for Stingray SoC

This is round two of adding DT nodes for Stingray SoC. Corresponding drivers and dt binding documents are already checked in the kernel and will be present in v4.14. Abhishek Shah (1): arm64: dts: Add DT node to enable BGMAC driver on Stingray Anup Patel (3): arm64: dts: Add sp804 DT nodes

[PATCH 1/7] arm64: dts: Enable stats for CCN-502 interconnect on Stingray

From: Velibor Markovski This patch enables stats for CCN-502 interconnect on Stingray. Signed-off-by: Velibor Markovski Reviewed-by: Ray Jui Reviewed-by: Scott Branden --- arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi | 6 ++ 1 file changed, 6 insertions(+) diff --git

Re: [PATCH 2/3] net: ethernet: bgmac: Make IDM register space optional

Hi Jon, > This also will need to be added to > drivers/net/ethernet/broadcom/bgmac-bcma.c. Otherwise, the driver > will no longer work for those platforms. Since this was already > accepted, please push out a fix ASAP. > I do not see how the bcma driver [bgmac-bcma.c] will no longer work. The

Re: [PATCH 2/3] net: ethernet: bgmac: Make IDM register space optional

Hi Jon, > This also will need to be added to > drivers/net/ethernet/broadcom/bgmac-bcma.c. Otherwise, the driver > will no longer work for those platforms. Since this was already > accepted, please push out a fix ASAP. > I do not see how the bcma driver [bgmac-bcma.c] will no longer work. The

[PATCH 3/3] Documentation: devicetree: net: optional idm regs for bgmac

Specifying IDM register space in DT is not mendatory for SoCs where firmware takes care of IDM operations. This patch updates BGMAC driver's DT binding documentation indicating the same. Signed-off-by: Abhishek Shah <abhishek.s...@broadcom.com> Reviewed-by: Ray Jui <ray@broadcom.com&

[PATCH 2/3] net: ethernet: bgmac: Make IDM register space optional

-by: Abhishek Shah <abhishek.s...@broadcom.com> Reviewed-by: Oza Oza <oza@broadcom.com> Reviewed-by: Ray Jui <ray@broadcom.com> Reviewed-by: Scott Branden <scott.bran...@broadcom.com> --- drivers/net/ethernet/broadcom/bgmac-platform.c | 19 --- drivers/net/ethernet/broadc

[PATCH 3/3] Documentation: devicetree: net: optional idm regs for bgmac

Specifying IDM register space in DT is not mendatory for SoCs where firmware takes care of IDM operations. This patch updates BGMAC driver's DT binding documentation indicating the same. Signed-off-by: Abhishek Shah Reviewed-by: Ray Jui Reviewed-by: Oza Oza Reviewed-by: Scott Branden

[PATCH 2/3] net: ethernet: bgmac: Make IDM register space optional

-by: Abhishek Shah Reviewed-by: Oza Oza Reviewed-by: Ray Jui Reviewed-by: Scott Branden --- drivers/net/ethernet/broadcom/bgmac-platform.c | 19 --- drivers/net/ethernet/broadcom/bgmac.c | 70 +++--- drivers/net/ethernet/broadcom/bgmac.h | 1 + 3 files changed

[PATCH 0/3] Extend BGMAC driver for Stingray SoC

The patchset extends Broadcom BGMAC driver for Broadcom Stingray SoC. This patchset is based on Linux-4.12 and tested on NS2 and Stingray. Abhishek Shah (3): net: ethernet: bgmac: Remove unnecessary 'return' from platform_bgmac_idm_write net: ethernet: bgmac: Make IDM register space

[PATCH 1/3] net: ethernet: bgmac: Remove unnecessary 'return' from platform_bgmac_idm_write

Return type for idm register write callback should be void as 'writel' API is used for write operation. However, there no need to have 'return' in this function. Signed-off-by: Abhishek Shah <abhishek.s...@broadcom.com> Reviewed-by: Oza Oza <oza@broadcom.com> Reviewed-by:

[PATCH 0/3] Extend BGMAC driver for Stingray SoC

The patchset extends Broadcom BGMAC driver for Broadcom Stingray SoC. This patchset is based on Linux-4.12 and tested on NS2 and Stingray. Abhishek Shah (3): net: ethernet: bgmac: Remove unnecessary 'return' from platform_bgmac_idm_write net: ethernet: bgmac: Make IDM register space

[PATCH 1/3] net: ethernet: bgmac: Remove unnecessary 'return' from platform_bgmac_idm_write

Return type for idm register write callback should be void as 'writel' API is used for write operation. However, there no need to have 'return' in this function. Signed-off-by: Abhishek Shah Reviewed-by: Oza Oza Reviewed-by: Ray Jui Reviewed-by: Scott Branden --- drivers/net/ethernet

[PATCH] net: phy: Allow BCM5481x PHYs to setup internal TX/RX clock delay

through "phy-mode" property in the platform device tree. Signed-off-by: Abhishek Shah <abhishek.s...@broadcom.com> --- drivers/net/phy/broadcom.c | 69 ++ 1 file changed, 33 insertions(+), 36 deletions(-) diff --git a/drivers/net/phy/broa

[PATCH] net: phy: Allow BCM5481x PHYs to setup internal TX/RX clock delay

through "phy-mode" property in the platform device tree. Signed-off-by: Abhishek Shah --- drivers/net/phy/broadcom.c | 69 ++ 1 file changed, 33 insertions(+), 36 deletions(-) diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadc