i.MX8
> SCU OCOTP driver.
>
> Signed-off-by: Peng Fan
> Cc: Rob Herring
> Cc: Mark Rutland
> Cc: Aisheng Dong
> Cc: Shawn Guo
> Cc: Ulf Hansson
> Cc: Stephen Boyd
> Cc: Anson Huang
> Cc: devicet...@vger.kernel.org
> ---
> Documentation/devicetree/bin
> From: Fabio Estevam [mailto:feste...@gmail.com]
> Sent: Saturday, May 4, 2019 7:02 PM
>
> Hi Kay-Liu,
>
> On Thu, Apr 25, 2019 at 8:14 AM wrote:
> >
> > From: Kay-Liu
> >
> > The imx6sx's dts file defines five clocks for fec, the 'ahb'clock's
> > value is IMX6SX_CLK_ENET_AHB, but in the
> From: Fabio Estevam [mailto:feste...@gmail.com]
> Sent: Saturday, May 4, 2019 7:04 PM
>
> Hi Kay-Liu,
>
> On Thu, Apr 25, 2019 at 8:09 AM wrote:
> >
> > From: Kay-Liu
> >
> > The imx6sx's dts file defines five clocks for fec, the 'ahb'clock's
> > value is IMX6SX_CLK_ENET_AHB, but in the
> From: Anson Huang
> Sent: Sunday, May 5, 2019 11:32 AM
> Subject: [PATCH] i2c: imx: Use __maybe_unused instead of #if CONFIG_PM
>
> Use __maybe_unused for runtime PM related functions instead of #if
> CONFIG_PM to simply the code.
>
> Signed-off-by: Anson Huang
Reviewed-by: Dong Aisheng
> From: Anson Huang
> Sent: Sunday, May 5, 2019 2:19 PM
>
> Use imx_mmdc_mask_handshake() API instead of programming CCM register
> directly in each platform to mask unused MMDC channel's handshake.
>
> Signed-off-by: Anson Huang
Reviewed-by: Dong Aisheng
Regards
Dong Aisheng
> From: Anson Huang
> Sent: Sunday, May 5, 2019 2:19 PM
> Subject: [PATCH 1/2] clk: imx: Add common API for masking MMDC handshake
>
> All i.MX6 SoCs need to mask unused MMDC channel's handshake for low
> power modes, this patch provides common API for masking the MMDC
> channel passed from
> From: Stephen Boyd [mailto:sb...@kernel.org]
> Sent: Saturday, May 4, 2019 12:01 AM
> Subject: RE: [PATCH V2] clk: imx: pllv4: add fractional-N pll support
>
> Quoting Aisheng Dong (2019-05-02 19:38:34)
> > > From: Stephen Boyd [mailto:sb...@kernel.org]
> > > Se
> From: Stephen Boyd [mailto:sb...@kernel.org]
> Sent: Thursday, May 2, 2019 5:01 AM
>
> The Content-transfer-encoding header is still base64. I guess it can't be
> fixed.
>
How can we know it's base64?
As I saw from the 'Headers' in patchwork, it's:
"Content-Type: text/plain;
> From: Anson Huang
> Sent: Tuesday, April 30, 2019 3:00 PM
> Subject: [PATCH] i2c: imx-lpi2c: Use __maybe_unused instead of #if
> CONFIG_PM_SLEEP
>
> Use __maybe_unused for power management related functions instead of #if
> CONFIG_PM_SLEEP to simply the code.
>
> Signed-off-by: Anson Huang
> From: Anson Huang
> Sent: Tuesday, April 30, 2019 9:55 AM
> Subject: [PATCH] clk: imx: pllv3: Fix fall through build warning
>
> Fix below fall through build warning:
>
> drivers/clk/imx/clk-pllv3.c:453:21: warning:
> this statement may fall through [-Wimplicit-fallthrough=]
>
>
> From: Anson Huang
> Sent: Monday, April 29, 2019 11:19 AM
>
clk: imx: pllv4: add fractional-N pll support
> The pllv4 supports fractional-N function, the formula is:
>
> PLL output freq = input * (mult + num/denom),
>
> This patch adds fractional-N function support, including clock round
> From: Aisheng Dong
> Sent: Monday, April 29, 2019 7:28 PM
> Subject: RE: [PATCH] clk: imx: add fractional-N pll support to pllv4
> > The pllv4 supports fractional-N function, the formula is:
> >
> > PLL output freq = input * (mult + num/denom),
> >
> >
> From: Anson Huang
> Sent: Monday, April 29, 2019 3:03 PM
>
> Use __maybe_unused for power management related functions instead of #if
> CONFIG_PM_SLEEP to simply the code.
>
> Signed-off-by: Anson Huang
Reviewed-by: Dong Aisheng
Regards
Dong Aisheng
> From: S.j. Wang
> Sent: Sunday, April 28, 2019 5:53 PM
>
> Add macros to define masks and bits for imx6sx MQS registers
>
> Signed-off-by: Shengjiu Wang
Reviewed-by: Dong Aisheng
Regards
Dong Aisheng
> From: Anson Huang
> Sent: Tuesday, April 16, 2019 11:22 AM
>
> i.MX8QXP is an ARMv8 SoC which has a Cortex-M4 system controller inside,
> the system controller is in charge of controlling power, clock and thermal
> sensors etc..
>
> This patch adds i.MX system controller thermal driver
> From: Anson Huang
> Sent: Tuesday, April 16, 2019 11:22 AM
>
> NXP i.MX8QXP is an ARMv8 SoC with a Cortex-M4 core inside as system
> controller, the system controller is in charge of system power, clock and
> thermal sensors etc. management, Linux kernel has to communicate with
> system
[...]
> >
> > Fixes: 90ad2cbe88c2("i2c: imx: use clk notifier for rate changes")
> > Signed-off-by: Anson Huang
>
> Please also provide how to reproduce it.
> And it seems not a new issue, should we CC stable?
Besides above comments:
Reviewed-by: Dong Aisheng
Regards
Dong Aisheng
>
>
> From: Anson Huang
> Sent: Wednesday, April 17, 2019 10:00 AM
>
> The way of getting private imx_i2c_struct in i2c_imx_clk_notifier_call() is
> incorrect, should use clk_change_nb element to get correct address and avoid
> below kernel dump during POST_RATE_CHANGE notify by clk
> framework:
>
>
> From: Anson Huang
> Sent: Friday, April 12, 2019 9:06 AM
>
> Hello, Alexandre
> As i.MX SCU general irq function is picked up by Shawn, could you please
> also pick up below i.MX SC RTC alarm support patch ?
> https://patchwork.kernel.org/patch/10890525/
>
No, it can't go through
> From: Abel Vesa
> Sent: Tuesday, April 9, 2019 2:53 AM
>
> i.MX8MQ needs it for RTC support.
>
> Signed-off-by: Abel Vesa
Reviewed-by: Dong Aisheng
Regards
Dong Aisheng
[...]
> > > +static int imx_sc_rtc_alarm_irq_enable(struct device *dev, unsigned
> > > +int
> > > +enable) {
> > > + imx_scu_irq_enable(SC_IRQ_GROUP_RTC, SC_IRQ_RTC, enable);
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static int imx_sc_rtc_read_alarm(struct device *dev, struct
> > >
> From: Abel Vesa
> Sent: Tuesday, April 9, 2019 2:39 AM
>
> To support pinctl hog restore after LPSR resume back, add the generic
> suspend/resume in pinctrl-imx along with the generic pm ops to be used by
> platform specific drivers. Then make use of the newly added ops in i.MX8MQ
> platform
> From: Anson Huang
> Sent: Tuesday, April 9, 2019 10:44 AM
> Subject: [PATCH V6 4/4] rtc: imx-sc: add rtc alarm support
>
> Add i.MX system controller RTC alarm support, the RTC alarm is implemented
> via SIP(silicon provider) runtime service call and ARM-Trusted-Firmware will
> communicate with
> From: Anson Huang
> Sent: Tuesday, April 9, 2019 10:43 AM
> Subject: [PATCH V6 2/4] firmware: imx: enable imx scu general irq function
>
> The System Controller Firmware (SCFW) controls RTC, thermal and WDOG etc.,
> these resources' interrupt function are managed by SCU. When any IRQ
> pending,
[...]
> so I will add another API in imx-scu-irq
> driver to provide function of enabling/disabling irq, each driver can just
> call the
> API to enable/disable its own IRQ, ONLY need to pass the corresponding
> arguments:
>
That's exactly what I mean.
> >
> > > + msg.group =
> From: Linus Walleij [mailto:linus.wall...@linaro.org]
> Sent: Monday, April 8, 2019 8:10 PM
> On Wed, Apr 3, 2019 at 10:43 AM Shawn Guo wrote:
>
> > I assume this will go via your tree. Let me know if you think
> > differently.
>
> OK I applied it, if you're not merging any device trees using
> From: Abel Vesa
> Sent: Monday, April 8, 2019 6:43 PM
> Subject: [PATCH v2] pinctrl: pinctrl-imx8mq: Add suspend/resume ops
pinctrl: imx8mq:
> To support pinctl hog restore after LPSR resume back, add the generic
> suspend/resume in pinctrl-imx along with the generic pm opsto be used by
>
> From: Anson Huang
> Sent: Monday, March 18, 2019 11:10 AM
>
> Add i.MX system controller RTC alarm support, the RTC alarm is implemented
> via SIP(silicon provider) runtime service call and ARM-Trusted-Firmware will
> communicate with system controller via MU(message unit) IPC to set RTC
>
> From: Anson Huang
> Sent: Monday, March 18, 2019 11:10 AM
>
> The System Controller Firmware (SCFW) controls RTC, thermal and WDOG etc.,
> these resources' interrupt function are managed by SCU. When any IRQ
> pending, SCU will notify Linux via MU general interrupt channel #3, and Linux
>
> From: Abel Vesa
> Sent: Monday, March 25, 2019 10:00 PM
>
> Add suspend/resume pm ops to the pinctrl i.MX8MQ driver.
> Make the suspend late and the resume early since some of the pins might be
> needed active very late.
> These call the pinctrl-imx generic handlers.
>
> Signed-off-by: Abel
> From: Daniel Baluta
> Sent: Sunday, March 31, 2019 1:08 AM
>
> lpuart nodes are part of the ADMA subsystem. See Audio DMA memory map in
> iMX8 QXP RM [1]
>
> This patch is based on the dtsi file initially submitted by Teo Hall in i.MX
> NXP
> internal tree.
>
> [1]
> From: Christina Quast [mailto:cqu...@hanoverdisplays.com]
> Sent: Wednesday, March 13, 2019 10:21 PM
>
> In the iMX7d datasheet, the PAD_CTL_DSE_X* values are different from the
> documentation.
>
> Changes since v2:
> * Changed patch title to 'dt-bindings: pinctrl: imx7d:'
>
> Signed-off-by:
> From: Angus Ainslie (Purism) [mailto:an...@akkea.ca]
> Sent: Thursday, March 28, 2019 9:38 PM
>
> Fix a typo in the compatible string
>
> Signed-off-by: Angus Ainslie (Purism)
> ---
> arch/arm64/boot/dts/freescale/imx8mq.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff
[...]
> > * All SPIs are connected to GPC in a 1:1 mapping
> > * This series deals with SGIs
> > * The timer PPIs are not required; covered by local-timer-stop
> > * LPIs are currently unused (I understand imx-pci uses SPI by default
> > from Lucas)
> >
> > Anything missing?
> >
> > My
[...]
> > > Anything that isn't visible to the GPC and requires the GIC
> > > wake_request signal to behave as specified is broken by this erratum.
> >
> > I really wonder how a timer interrupt (a PPI, hence not routed through
> > the GPC) can wake up the CPU in this case. It really feels like
> >
> From: Marc Zyngier [mailto:marc.zyng...@arm.com]
> Sent: Thursday, March 28, 2019 2:13 AM
> On 27/03/2019 17:00, Leonard Crestez wrote:
> > On Wed, 2019-03-27 at 17:06 +0100, Lucas Stach wrote:
> >> Am Mittwoch, den 27.03.2019, 15:57 + schrieb Marc Zyngier:
> >>> On 27/03/2019 15:44, Lucas
> > > diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > > b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > > index 0cb939861a60..84c7c3eca1a1 100644
> > > --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > > +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > > @@ -182,6 +182,78 @@
>
> From: laurentiu.tu...@nxp.com [mailto:laurentiu.tu...@nxp.com]
> Sent: Monday, March 25, 2019 11:30 PM
>
> From: Laurentiu Tudor
>
> If the dma controller is not yet probed, defer i2c probe.
> The error path in probe was slightly modified (no functional change) to avoid
> triggering this
> From: Igor Plyatov [mailto:plya...@gmail.com]
>
> Dear developers,
>
> please, help to resolve two issues with SPI DMA transfers at i.MX6Q platform.
>
> First issue is
> [ 4465.008003] spi_master spi0: I/O Error in DMA RX
>
> Second issue is duplication for one of received bytes.
>
Copy
> From: Daniel Baluta
> Sent: Thursday, March 28, 2019 3:03 AM
>
> i.MX8QXP contains a total of 4 EDMA controllers of which two are primarily
> for audio components and the other two are for non-audio periperhals.
>
> This patch adds the EDMA0/EDMA1 nodes used by audio peripherals.
>
> EDMA0
> From: Daniel Baluta
> Sent: Tuesday, March 26, 2019 5:43 PM
>
> i.MX8QXP contains a total of 4 EDMA controllers of which two are primarily
> for audio components and the other two are for non-audio periperhals.
>
> This patch adds the EDMA0/EDMA1 nodes used by audio peripherals.
>
> EDMA0
> From: Peng Fan
>
> > > > > Follow other i.MX6/7 machince code to check return value of
> > > > > imx_soc_device_init and warn when fail.
> > > > >
> > > > > Also drop of_platform_default_populate, because
> > > > > "arch_initcall_sync(of_platform_default_populate_init);" could
> > > > > be used
> From: Stephen Boyd [mailto:sb...@kernel.org]
>
> Quoting Eric Nelson (2019-03-11 13:48:55)
> > > On March 11, 2019, 6:35 p.m. UTC, Stephen Boyd wrote:
> > > Quoting Eric Nelson (2019-03-11 08:59:56)
> > >> + *
> > >> + * Renamed to _BROKEN to prevent inadvertent use,
> > >> + * but reserved
> From: Jonathan Neuschäfer [mailto:j.neuschae...@gmx.net]
>
> There are a few differences between the i.MX50 clock tree and those of
> i.MX51 and i.MX53 that are not yet handled in clk-imx51-imx53.c.
> This patch handles the following differences:
>
> - i.MX50 does not have a periph_apm clock.
[...]
> > > Follow other i.MX6/7 machince code to check return value of
> > > imx_soc_device_init and warn when fail.
> > >
> > > Also drop of_platform_default_populate, because
> > > "arch_initcall_sync(of_platform_default_populate_init);" could be
> > > used to populate the device tree.
> > >
>
[...]
> > Originally devices are registered in arch_initcall. Now it will be a
> > bit later in arch_initcall_sync and this may cause a bit risk if the
> > code under the default_populate want to access the device service provided
> by early probe.
> >
> > Probably it's more safe to leave as it
> From: Stephen Boyd [mailto:sb...@kernel.org]
>
> Quoting Patrick Wildt (2019-03-12 00:36:54)
> > On Fri, Mar 08, 2019 at 07:29:05AM -0800, Stephen Boyd wrote:
> > > It's mostly about making sure that any existing dtbs don't have
> > > their numbers shifted around. So hopefully any overlapping
>
> From: Anson Huang
>
> On i.MX8QXP, SCU uses MU1 general interrupt channel #3 to notify user for
> IRQs of RTC alarm, thermal alarm and WDOG etc., mailbox RX doorbell mode is
> used for this function, this patch adds support for it.
>
> Signed-off-by: Anson Huang
> ---
> Changes since V3:
>
> From: Anson Huang
>
> The System Controller Firmware (SCFW) controls RTC, thermal and WDOG etc.,
> these resources' interrupt function are managed by SCU. When any IRQ
> pending, SCU will notify Linux via MU general interrupt channel #3, and Linux
> kernel needs to call SCU APIs to get IRQ
> From: Anson Huang
>
> Add scu general interrupt function support.
>
> Signed-off-by: Anson Huang
> Reviewed-by: Rob Herring
Reviewed-by: Dong Aisheng
Regards
Dong Aisheng
> From: Peng Fan
>
> Subject: [PATCH] arm64: dts: imx8qxp: fix mbox-cells
>
> Currently lsio_mu1 is used by Linux Kernel with mbox-cells as 2, but actually
> mu0-4 could be used to communicate with SCU. So fix the mbox-cells.
>
> Signed-off-by: Peng Fan
Reviewed-by: Dong Aisheng
Regards
Dong
> From: Peng Fan
>
> Add lsio_mu2 node which could be used communicate with SCU.
>
> Signed-off-by: Peng Fan
Reviewed-by: Dong Aisheng
Regards
Dong Aisheng
> ---
> arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 8
> 1 file changed, 8 insertions(+)
>
> diff --git
> From: Peng Fan
>
> [PATCH 2/2] ARM: imx: mach-imx7ulp: warn when imx_soc_device_init fail
ARM: imx: imx7ulp: ...
> Follow other i.MX6/7 machince code to check return value of
> imx_soc_device_init and warn when fail.
>
> Also drop of_platform_default_populate, because
>
> From: Peng Fan
>
> "arch_initcall_sync(of_platform_default_populate_init);" could be used to
> populate the device tree, there is no need to call
> of_platform_default_populate
> in machine code.
>
> Tested on i.MX6Q-SDB i.MX6SL-EVK i.MX6UL-EVK board.
>
> Signed-off-by: Peng Fan
> ---
>
+Jacky and Leonard, Ranjani
Hi Alexandre,
> From: Alexandre Bailon [mailto:abai...@baylibre.com]
>
> This series implements busfreq, a framework used in MXP's tree to scale the
> interconnect and dram frequencies.
> In the vendor tree, device's driver request for a performance level, which is
>
[...]
> >
> > > > As I replied in another mail, it actually does not depend on SCU.
> > > > Let's wait for Rob's comment on whether we could move watchdog Out
> > > > of SCU node.
> > >
> > > Per previous discussion, the dependency here is to prevent enabling
> > > this module for platform
[...]
> > As I replied in another mail, it actually does not depend on SCU.
> > Let's wait for Rob's comment on whether we could move watchdog Out of
> > SCU node.
>
> Per previous discussion, the dependency here is to prevent enabling this
> module for platform without IMX SCU, although it does
> From: Anson Huang
> Sent: Wednesday, March 6, 2019 9:06 AM
>
> i.MX8QXP is an ARMv8 SoC which has a Cortex-M4 system controller inside,
> the system controller is in charge of controlling power, clock and watchdog
> etc..
>
> This patch adds i.MX system controller watchdog driver support,
[...]
> > diff --git a/drivers/firmware/imx/imx-scu.c
> > b/drivers/firmware/imx/imx-scu.c index 2bb1a19..df75ead 100644
> > --- a/drivers/firmware/imx/imx-scu.c
> > +++ b/drivers/firmware/imx/imx-scu.c
...
> > + /* register SCU child devices which are NOT in device tree */
> > + child_pdev =
Hi Rob,
> > > I think Rob suggested that the SCU parent driver should instantiate
> > > the watchdog without explicit watchdog node. That would be possible,
> > > but it currently uses
> > > devm_of_platform_populate() to do the instantiation, and changing
> > > that would be a mess. Besides, it
[...]
> > > > > diff --git
> > > > > a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
> > > > > b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
> > > > > index 72d481c..855270b 100644
> > > > > ---
> > > > > a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
[...]
> > > Btw, I saw that imx7d-sdb.dts (and probably other i.MX 7 boards too)
> > > use three different settings for usdhc pinctrl: 0x59, 0x5a and 0x5b
> > > (for default, 100MHz and 200MHz respectively). One would expect that
> > > higher frequency use higher driver strength (and this is the
> From: Arnd Bergmann [mailto:a...@arndb.de]
> Sent: Tuesday, March 5, 2019 4:30 PM
> On Tue, Mar 5, 2019 at 4:00 AM Aisheng Dong
> wrote:
> >
> > Hi Arnd,
> >
> > > From: Arnd Bergmann [mailto:a...@arndb.de]
> > > Sent: Tuesday, March 5, 201
+ Haibo
> From: Stefan Agner [mailto:ste...@agner.ch]
> Sent: Tuesday, February 26, 2019 9:22 PM
>
> On 26.02.2019 13:21, Aisheng Dong wrote:
> >> From: Christina Quast [mailto:cqu...@hanoverdisplays.com]
> >> Sent: Saturday, February 23, 2019 1:01 AM
&g
Hi Arnd,
> From: Arnd Bergmann [mailto:a...@arndb.de]
> Sent: Tuesday, March 5, 2019 4:26 AM
>
> Submitted by Anders Roxell already
>
> Signed-off-by: Arnd Bergmann
How would suggest to handle this patch?
I've already given an Ack to Andres' v3 patch with a few additional comments,
but seems
> From: Christina Quast [mailto:cqu...@hanoverdisplays.com]
> Sent: Saturday, February 23, 2019 1:01 AM
>
> In the iMX7d datasheet, the PAD_CTL_DSE_X* values are different from the
> documentation.
>
It's a doc problem.
Latest RM seems got updated.
As here it's a reference definition in
> > Subject: [PATCH V4 1/2] dt-bindings: imx: remove unused resources from
> > scu resource table
> >
> > Removes below resources which were defined during pre-silicon phase
> > and the real silicons do NOT have them, they have never been used,
> > latest system controller firmware also removed
> From: Anson Huang
> Sent: Saturday, February 23, 2019 11:20 AM
>
> Add new resources as below according to latest system controller firmware for
> new features:
>
> IMX_SC_R_PERF
> IMX_SC_R_OCRAM
> IMX_SC_R_DMA_5_CH0
> IMX_SC_R_DMA_5_CH1
> IMX_SC_R_DMA_5_CH2
>
> From: Anson Huang
> Sent: Saturday, February 23, 2019 11:20 AM
> To: robh...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org;
> s.ha...@pengutronix.de; ker...@pengutronix.de; feste...@gmail.com;
> ulf.hans...@linaro.org; Aisheng Dong ;
> devicet...@vger.kernel.
[...]
> > On Thu, Feb 21, 2019 at 06:38:30AM +, Anson Huang wrote:
> > > NXP i.MX8QXP is an ARMv8 SoC with a Cortex-M4 core inside as system
> > > controller, the system controller is in charge of system power,
> > > clock and thermal sensors etc. management, Linux kernel has to
> > >
> From: Guenter Roeck [mailto:groe...@gmail.com] On Behalf Of Guenter
> Roeck>
> On 2/22/19 11:52 AM, Rob Herring wrote:
> > On Mon, Feb 18, 2019 at 06:53:48AM +, Anson Huang wrote:
> >> Add i.MX8QXP system controller watchdog binding.
> >>
> >> Signed-off-by: Anson Huang
> >> ---
> >>
[...]
> > > > > > Tested-by: Lucas Stach
> > > > > > Acked-by: Lucas Stach
> > > > >
> > > > > I suspect these tested by and acked tags should have been
> > > > > dropped, unless you discussed and tested off-list?
> > > > >
> > > >
> > > > Oups, I forgot to drop them.
> > >
> > > Ok. Can Lucas
> From: Stephen Boyd [mailto:sb...@kernel.org]
> Sent: Tuesday, February 26, 2019 1:23 AM>
> Quoting Abel Vesa (2019-02-23 02:58:14)
> > On 19-02-22 09:46:23, Stephen Boyd wrote:
> > > Quoting Abel Vesa (2019-02-22 09:07:32)
> > > > Make the entire combination of plls to be one single clock. The
Hi Anson,
> From: Anson Huang
> Sent: Friday, February 22, 2019 5:42 PM
>
> Currently on i.MX8MQ platform, clock driver is probed later than GPIO driver,
> and GPIO driver does NOT have defer probe mechanism since the GPIO clock is
> optional, some platforms have GPIO clocks and some are NOT. So
> From: Marco Felsch [mailto:m.fel...@pengutronix.de]
> Sent: Wednesday, February 20, 2019 9:53 PM
>
> On 19-02-20 13:11, Lucas Stach wrote:
> > Am Mittwoch, den 20.02.2019, 11:21 +0000 schrieb Aisheng Dong:
> > > Hi Marco,
> > >
> > > > Fr
> From: Lucas Stach [mailto:l.st...@pengutronix.de]
> Sent: Wednesday, February 20, 2019 8:11 PM
>
> Am Mittwoch, den 20.02.2019, 11:21 +0000 schrieb Aisheng Dong:
> > Hi Marco,
> >
> > > From: Marco Felsch [mailto:m.fel...@pengutronix.de]
> > >
One irqsteer channel can support up to 8 output interrupts.
Cc: Marc Zyngier
Cc: Lucas Stach
Cc: Shawn Guo
Reviewed-by: Lucas Stach
Signed-off-by: Dong Aisheng
---
ChangeLog:
v3->v4:
* no changes
v2->v3:
* add error check for imx_irqsteer_get_hwirq_base
* use DIV_ROUND_UP
* merge 'hwirq
Not all 64 interrupts may be used in one group. e.g. most irqsteer in
imx8qxp and imx8qm subsystems supports only 32 interrupts.
As the IP integration parameters are Channel number and interrupts number,
let's use fsl,irqs-num to represents how many interrupts supported
by this irqsteer channel.
One irqsteer channel can support up to 8 output interrupts.
Cc: Marc Zyngier
Cc: Rob Herring
Cc: Shawn Guo
Cc: devicet...@vger.kernel.org
Reviewed-by: Lucas Stach
Signed-off-by: Dong Aisheng
---
ChangeLog:
v3->v4:
* no changes
v2->v3:
* fix a typo
v1->v2:
* remove one unnecessary note.
Not all 64 interrupts may be used in one group. e.g. most irqsteer in
imx8qxp and imx8qm subsystems supports only 32 interrupts.
And one irqsteer channel can support up to 8 output interrupts.
This patch series aims to support 32 interrupts chan and multi output
interrupts.
Tested on:
iMX8QXP
One group can manage 64 interrupts by using two registers (e.g. STATUS/SET).
However, the integrated irqsteer may support only 32 interrupts which
needs only one register in a group. But the current driver assume there's
a mininum of two registers in a group which result in a wrong register map
Hi Marco,
> From: Marco Felsch [mailto:m.fel...@pengutronix.de]
> Sent: Wednesday, February 20, 2019 6:53 PM
>
> Hi Aisheng,
>
> On 19-02-20 09:49, Aisheng Dong wrote:
> > > From: Marco Felsch [mailto:m.fel...@pengutronix.de]
> > > Sent: Wednesday, Februar
> From: Marco Felsch [mailto:m.fel...@pengutronix.de]
> Sent: Wednesday, February 20, 2019 4:17 PM
> On 19-02-20 03:38, Aisheng Dong wrote:
> > [...]
> >
> > > > I don't like droping some ID's (e.g. IMX_SC_R_DC_0_CAPTURE0) by
> > > > mark them as u
> From: Anson Huang
> Sent: Wednesday, February 20, 2019 2:54 PM
>
> NXP i.MX8QXP is an ARMv8 SoC with a Cortex-M4 core inside as system
> controller, the system controller is in charge of system power, clock and
> thermal sensors etc. management, Linux kernel has to communicate with
> system
> From: Rob Herring [mailto:r...@kernel.org]
> Sent: Thursday, February 14, 2019 6:30 AM
> On Mon, Feb 11, 2019 at 03:34:23PM +, Marc Zyngier wrote:
> > On 31/01/2019 08:03, Aisheng Dong wrote:
> > > One irqsteer channel can support up to 8 output interrupts.
>
> From: Rob Herring [mailto:r...@kernel.org]
> Sent: Thursday, February 14, 2019 6:27 AM>
> On Mon, Feb 11, 2019 at 03:35:40PM +, Marc Zyngier wrote:
> > On 31/01/2019 08:03, Aisheng Dong wrote:
> > > Not all 64 interrupts may be used in one group. e.g. mos
> From: Anson Huang
> Sent: Tuesday, February 19, 2019 11:11 AM
>
> The System Controller Firmware (SCFW) controls RTC, thermal and WDOG etc.,
> these resources' interrupt function are managed by SCU. When any IRQ
> pending, SCU will notify Linux via MU general interrupt channel #3, and Linux
>
> From: Anson Huang
> Sent: Tuesday, February 19, 2019 11:11 AM
> Subject: [PATCH V3 1/4] dt-bindings: fsl: scu: add general interrupt support
>
> Add scu general interrupt function support.
>
> Signed-off-by: Anson Huang
> Reviewed-by: Rob Herring
> ---
> No change since V2.
> ---
>
> >
> > You need at least explain what changes made like what new features added?
> > What removed? Side affect if any?
>
> No new features added, looks like SCFW just remove some unused resources.
> No side-effect, as they are NOT used by anyone.
>
That seems not true.
I see some new IDs
[...]
> > I don't like droping some ID's (e.g. IMX_SC_R_DC_0_CAPTURE0) by mark
> > them as unused or even worse give them a other meaning. IMHO the
> > scu-api should be stable since day 1 and the ID's should only be extended.
> > Marking ID's as deprecated is much better than moving them around.
> From: Anson Huang
> Sent: Tuesday, February 19, 2019 5:01 PM
> Subject: [PATCH] dt-bindings: imx: update scu resource id headfile
>
> Update i.MX SCU resource ID table according to latest system controller
> firmware.
>
You need at least explain what changes made like
what new features added?
> From: Anson Huang
> Sent: Thursday, February 7, 2019 5:53 PM
[...]
>
> NXP i.MX8QXP is an ARMv8 SoC with a Cortex-M4 core inside as system
> controller, the system controller is in charge of system power, clock and
> thermal sensors etc. management, Linux kernel has to communicate with
> system
> -Original Message-
> From: Joakim Zhang
> Sent: Thursday, January 31, 2019 5:37 PM
> To: m...@pengutronix.de; linux-...@vger.kernel.org
> Cc: w...@grandegger.com; net...@vger.kernel.org;
> linux-kernel@vger.kernel.org; dl-linux-imx ; Joakim
> Zhang
> Subject: [PATCH] can: flexcan: fix
> From: Joakim Zhang
> Sent: Thursday, January 31, 2019 4:49 PM
[...]
> > > Current we can meet timeout issue when setting a small bitrate like
> > > 1 as follows:
> > > root@imx6qdlsolo:~# ip link set can0 up type can bitrate 1 A
> > > link change request failed with some changes
> -Original Message-
> From: Daniel Baluta
> Sent: Wednesday, January 30, 2019 9:30 PM
> To: shawn...@kernel.org
> Cc: s.ha...@pengutronix.de; ker...@pengutronix.de; feste...@gmail.com;
> dl-linux-imx ; daniel.bal...@gmail.com; Aisheng Dong
> ; linux-arm-ker...@lists.i
One irqsteer channel can support up to 8 output interrupts.
Cc: Marc Zyngier
Cc: Rob Herring
Cc: Lucas Stach
Cc: Shawn Guo
Cc: devicet...@vger.kernel.org
Signed-off-by: Dong Aisheng
---
ChangeLog:
v2->v3:
* fix a typo
v1->v2:
* remove one unnecessary note.
---
Not all 64 interrupts may be used in one group. e.g. most irqsteer in
imx8qxp and imx8qm subsystems supports only 32 interrupts.
And one irqsteer channel can support up to 8 output interrupts.
This patch series aims to support 32 interrupts chan and multi output
interrupts.
Tested on:
iMX8QXP
Not all 64 interrupts may be used in one group. e.g. most irqsteer in
imx8qxp and imx8qm subsystems supports only 32 interrupts.
As the IP integration parameters are Channel number and interrupts number,
let's use fsl,irqs-num to represents how many interrupts supported
by this irqsteer channel.
One group can manage 64 interrupts by using two registers (e.g. STATUS/SET).
However, the integrated irqsteer may support only 32 interrupts which
needs only one register in a group. But the current driver assume there's
a mininum of two registers in a group which result in a wrong register map
One irqsteer channel can support up to 8 output interrupts.
Cc: Marc Zyngier
Cc: Lucas Stach
Cc: Shawn Guo
Signed-off-by: Dong Aisheng
---
ChangeLog:
v2->v3:
* add error check for imx_irqsteer_get_hwirq_base
* use DIV_ROUND_UP
* merge 'hwirq +=32' into for loop
* common error path in
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