This patch adds support for optional vbus regulator.
It is managed on phy_power_on/off calls and may be needed for host mode.
Signed-off-by: Amelie Delaunay
---
No changes in v2.
---
drivers/phy/st/phy-stm32-usbphyc.c | 31 ++
1 file changed, 31 insertions(+)
diff
STM32 USBPHYC provides two USB High-Speed ports which are used by controllers
with Host capabilities. That's why vbus-supply has to be supported on each
phy node.
---
Changes in v2:
- use connector node vbus-supply property as suggested by Rob
---
Amelie Delaunay (2):
dt-bindings: phy: add vbus
This patch adds vbus-supply optional property to phy sub-nodes using
connector node.
A regulator for USB VBUS may be needed for host mode.
Signed-off-by: Amelie Delaunay
---
Changes in v2:
- add connector vbus-supply property as suggested by Rob
---
.../devicetree/bindings/phy/phy-stm32
Hi Rob,
On 3/26/21 1:28 AM, Rob Herring wrote:
On Wed, Mar 17, 2021 at 05:09:53PM +0100, Amelie Delaunay wrote:
This patch adds vbus-supply optional property to phy sub-nodes.
A regulator for USB VBUS may be needed for host mode.
Signed-off-by: Amelie Delaunay
---
Documentation/devicetree
This patch adds vbus-supply optional property to phy sub-nodes.
A regulator for USB VBUS may be needed for host mode.
Signed-off-by: Amelie Delaunay
---
Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree
STM32 USBPHYC provides two USB High-Speed ports which are used by controllers
with Host capabilities. That's why vbus-supply has to be supported on each
phy node.
Amelie Delaunay (2):
dt-bindings: phy: add vbus-supply optional property to
phy-stm32-usbphyc
phy: stm32: manage optional vbus
This patch adds support for optional vbus regulator.
It is managed on phy_power_on/off calls and may be needed for host mode.
Signed-off-by: Amelie Delaunay
---
drivers/phy/st/phy-stm32-usbphyc.c | 31 ++
1 file changed, 31 insertions(+)
diff --git a/drivers/phy/st
usbphyc provides a unique clock called ck_usbo_48m.
STM32 USB OTG needs a 48Mhz clock (utmifs_clk48) for Full-Speed operation.
ck_usbo_48m is a possible parent clock for USB OTG 48Mhz clock.
ck_usbo_48m is available as soon as the PLL is enabled.
Signed-off-by: Amelie Delaunay
Acked-by: Rob
Changes in v3:
- remove #clock-cells from required properties
Changes in v2:
- fix COMMON_CLK dependency issue reported by kernel test robot
---
Amelie Delaunay (2):
dt-bindings: phy: phy-stm32-usbphyc: add #clock-cells property
phy: stm32: register usbphyc as clock provider of ck_usbo_48m clock
ck_usbo_48m is generated by usbphyc PLL and used by OTG controller
for Full-Speed use cases with dedicated Full-Speed transceiver.
ck_usbo_48m is available as soon as the PLL is enabled.
Signed-off-by: Amelie Delaunay
---
No changes in v3.
Changes in v2:
- fix COMMON_CLK dependency issue
from required properties
Changes in v2:
- fix COMMON_CLK dependency issue reported by kernel test robot
---
Amelie Delaunay (2):
dt-bindings: phy: phy-stm32-usbphyc: add #clock-cells property
phy: stm32: register usbphyc as clock provider of ck_usbo_48m clock
.../bindings/phy/phy-stm32
usbphyc provides a unique clock called ck_usbo_48m.
STM32 USB OTG needs a 48Mhz clock (utmifs_clk48) for Full-Speed operation.
ck_usbo_48m is a possible parent clock for USB OTG 48Mhz clock.
ck_usbo_48m is available as soon as the PLL is enabled.
Signed-off-by: Amelie Delaunay
Acked-by: Rob
ck_usbo_48m is generated by usbphyc PLL and used by OTG controller
for Full-Speed use cases with dedicated Full-Speed transceiver.
ck_usbo_48m is available as soon as the PLL is enabled.
Signed-off-by: Amelie Delaunay
---
No changes in v3.
Changes in v2:
- fix COMMON_CLK dependency issue
from required properties
Changes in v2:
- fix COMMON_CLK dependency issue reported by kernel test robot
---
Amelie Delaunay (2):
dt-bindings: phy: phy-stm32-usbphyc: add #clock-cells property
phy: stm32: register usbphyc as clock provider of ck_usbo_48m clock
.../bindings/phy/phy-stm32
usbphyc provides a unique clock called ck_usbo_48m.
STM32 USB OTG needs a 48Mhz clock (utmifs_clk48) for Full-Speed operation.
ck_usbo_48m is a possible parent clock for USB OTG 48Mhz clock.
ck_usbo_48m is available as soon as the PLL is enabled.
Signed-off-by: Amelie Delaunay
---
Changes in v3
ck_usbo_48m is generated by usbphyc PLL and used by OTG controller
for Full-Speed use cases with dedicated Full-Speed transceiver.
ck_usbo_48m is available as soon as the PLL is enabled.
Signed-off-by: Amelie Delaunay
---
Changes in v2:
- fix COMMON_CLK dependency issue reported by kernel test
Hi Rob,
On 1/25/21 10:40 PM, Rob Herring wrote:
On Thu, Jan 14, 2021 at 06:13:13PM +0100, Amelie Delaunay wrote:
usbphyc provides a unique clock called ck_usbo_48m.
STM32 USB OTG needs a 48Mhz clock (utmifs_clk48) for Full-Speed operation.
ck_usbo_48m is a possible parent clock for USB OTG
dependency issue reported by kernel test robot
---
Amelie Delaunay (2):
dt-bindings: phy: phy-stm32-usbphyc: add #clock-cells required
property
phy: stm32: register usbphyc as clock provider of ck_usbo_48m clock
.../bindings/phy/phy-stm32-usbphyc.yaml | 6 ++
drivers/phy/st/Kconfig
ck_usbo_48m is generated by usbphyc PLL and used by OTG controller
for Full-Speed use cases with dedicated Full-Speed transceiver.
ck_usbo_48m is available as soon as the PLL is enabled.
Signed-off-by: Amelie Delaunay
---
Changes in v2:
- fix COMMON_CLK dependency issue reported by kernel test
usbphyc provides a unique clock called ck_usbo_48m.
STM32 USB OTG needs a 48Mhz clock (utmifs_clk48) for Full-Speed operation.
ck_usbo_48m is a possible parent clock for USB OTG 48Mhz clock.
ck_usbo_48m is available as soon as the PLL is enabled.
Signed-off-by: Amelie Delaunay
---
No change
vdda1v1 and vdda1v8 supplies are required by USB PLL. Add them in usbphyc
node.
Cc: Manivannan Sadhasivam
Signed-off-by: Amelie Delaunay
---
arch/arm/boot/dts/stm32mp151.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/stm32mp151.dtsi
b/arch/arm/boot/dts/stm32mp151
vdda1v1 and vdda1v8 supplies are required by USB PLL, not by the PHYs.
Remove them from usbphyc child phy nodes now that they are managed in
usbphyc parent node at SoC level.
Cc: Manivannan Sadhasivam
Signed-off-by: Amelie Delaunay
---
arch/arm/boot/dts/stm32mp157a-stinger96.dtsi | 4
usbphyc is a 48Mhz clock provider: the clock can be used as clock source
for USB OTG. Add #clock-cells property to usbphyc node to reflect this
capability.
Signed-off-by: Amelie Delaunay
---
arch/arm/boot/dts/stm32mp151.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts
This series updates usbphyc parent and child nodes to follow latest DT
bindings.
---
Changes in v2:
- squash all DT board patches in one patch
- update also non-ST DT
Amelie Delaunay (3):
ARM: dts: stm32: add usbphyc vdda1v1 and vdda1v8 supplies on
stm32mp151
ARM: dts: stm32: remove
vdda1v1 and vdda1v8 supplies are required by USB PLL, not by the PHYs.
Remove them from usbphyc child phy nodes now that they are managed in
usbphyc parent node at SoC level.
Signed-off-by: Amelie Delaunay
---
arch/arm/boot/dts/stm32mp157c-ed1.dts | 4
1 file changed, 4 deletions(-)
diff
vdda1v1 and vdda1v8 supplies are required by USB PLL. Add them in usbphyc
node.
Signed-off-by: Amelie Delaunay
---
arch/arm/boot/dts/stm32mp151.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/stm32mp151.dtsi
b/arch/arm/boot/dts/stm32mp151.dtsi
index 3c75abacb374
usbphyc is a 48Mhz clock provider: the clock can be used as clock source
for USB OTG. Add #clock-cells property to usbphyc node to reflect this
capability.
Signed-off-by: Amelie Delaunay
---
arch/arm/boot/dts/stm32mp151.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts
vdda1v1 and vdda1v8 supplies are required by USB PLL, not by the PHYs.
Remove them from usbphyc child phy nodes now that they are managed in
usbphyc parent node at SoC level.
Signed-off-by: Amelie Delaunay
---
arch/arm/boot/dts/stm32mp15xx-dkx.dtsi | 4
1 file changed, 4 deletions(-)
diff
This series updates usbphyc parent and child nodes to follow latest DT
bindings.
Amelie Delaunay (4):
ARM: dts: stm32: add usbphyc vdda1v1 and vdda1v8 supplies on
stm32mp151
ARM: dts: stm32: remove usbphyc ports vdda1v1-vdda1v8 on
stm32mp157c-ed1
ARM: dts: stm32: remove usbphyc
ck_usbo_48m is generated by usbphyc PLL and used by OTG controller
for Full-Speed use cases with dedicated Full-Speed transceiver.
ck_usbo_48m is available as soon as the PLL is enabled.
Signed-off-by: Amelie Delaunay
---
drivers/phy/st/phy-stm32-usbphyc.c | 66
usbphyc provides a unique clock called ck_usbo_48m.
STM32 USB OTG needs a 48Mhz clock (utmifs_clk48) for Full-Speed operation.
ck_usbo_48m is a possible parent clock for USB OTG 48Mhz clock.
ck_usbo_48m is available as soon as the PLL is enabled.
Signed-off-by: Amelie Delaunay
STM32 USBPHYC provides clocks to STM32 RCC pour STM32 USB controllers.
Specifically, ck_usbo_48m is a possible clock parent for USB OTG clock,
during OTG Full-Speed operation.
This series registers the usbphyc as clock provider of this ck_usbo_48m clock.
Amelie Delaunay (2):
dt-bindings: phy
Link Power Management on STM32MP15 HS OTG.
Signed-off-by: Amelie Delaunay
Acked-by: Minas Harutyunyan
---
drivers/usb/dwc2/params.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
index 9e5dd7f3f2f6..92df3d620f7d 100644
--- a/drivers/usb/dwc
controller performance.
[1] https://www.st.com/resource/en/reference_manual/dm00327659.pdf, p.3149
Signed-off-by: Amelie Delaunay
Acked-by: Minas Harutyunyan
---
drivers/usb/dwc2/params.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
When the core is in FS host mode, using the FS transceiver, and a Low-Speed
device is connected, transceiver clock is 6Mhz.
So, to support Low-Speed devices, enable support of FS/LS Low Power mode,
so that the PHY supplies a 6 MHz clock during Low-Speed mode.
Signed-off-by: Amelie Delaunay
Acked
' Reviewed-by on all patches
Amelie Delaunay (3):
usb: dwc2: set ahbcfg parameter for STM32MP15 OTG HS and FS
usb: dwc2: enable FS/LS PHY clock select on STM32MP15 FS OTG
usb: dwc2: disable Link Power Management on STM32MP15 HS OTG
drivers/usb/dwc2/params.c | 8
1 file changed, 8 insertions
Due to async_schedule_domain call in regulator_bulk_enable,
scheduling while atomic bug can raise if regulator_bulk_enable is called
under atomic context.
To avoid this issue, this patch replaces all regulator_bulk* by regulator_
per regulators.
Signed-off-by: Amelie Delaunay
---
drivers/phy/st
dependent.
To ensure a good behavior of the PLL, supplies have to be managed at PLL
activation/deactivation. That means the supplies need to be put in usbphyc
parent node and not in phy children nodes.
Signed-off-by: Amelie Delaunay
Reviewed-by: Rob Herring
---
Note that even with bindings change
:
- Move author mail address from @st.com to @foss.st.com
- Add Rob's Reviewed-by on bindings patch 1/6
Amelie Delaunay (6):
dt-bindings: phy: phy-stm32-usbphyc: move PLL supplies to parent node
phy: stm32: manage 1v1 and 1v8 supplies at pll activation/deactivation
phy: stm32: replace
To ensure a good balancing of regulators, force PLL disable either by
reset or by clearing the PLLEN bit.
If waiting the powerdown pulse delay isn't enough, return -EPROBE_DEFER
instead of polling the PLLEN bit, which will be low at the next probe.
Signed-off-by: Amelie Delaunay
---
drivers/phy
dependent.
To ensure a good behavior of the PLL, supplies have to be managed at PLL
activation/deactivation. That means the supplies need to be put in usbphyc
node and not in phy children nodes.
Signed-off-by: Amelie Delaunay
---
drivers/phy/st/phy-stm32-usbphyc.c | 102
if a phy_exit is required to properly disable the PLL.
Signed-off-by: Amelie Delaunay
---
drivers/phy/st/phy-stm32-usbphyc.c | 88 ++
1 file changed, 54 insertions(+), 34 deletions(-)
diff --git a/drivers/phy/st/phy-stm32-usbphyc.c
b/drivers/phy/st/phy-stm32-usbphyc.c
index
To ensure a good balancing of regulators, and allow PLL disabling when the
driver is removed, call stm32_usbphyc_phy_exit on each ports to set phys
inactive and disable PLL.
Signed-off-by: Amelie Delaunay
---
drivers/phy/st/phy-stm32-usbphyc.c | 6 ++
1 file changed, 6 insertions(+)
diff
]" won't appear anymore.
.of_compatible could be added as soon as idd or ts bindings are described
and drivers available.
Signed-off-by: Amelie Delaunay
---
drivers/mfd/stmfx.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/mfd/stmfx.c b/drivers/mfd/stmfx.c
index e095a3930142..b
STM32_MDMA_VERY_HIGH_PRIORITY is b11 not 0x11, so fix it with 0x3.
Signed-off-by: Amelie Delaunay
---
drivers/dma/stm32-mdma.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/dma/stm32-mdma.c b/drivers/dma/stm32-mdma.c
index e4637ec786d3..36ba8b43e78d 100644
On 11/27/20 2:45 PM, Greg Kroah-Hartman wrote:
On Fri, Nov 27, 2020 at 02:17:35PM +0100, Amelie Delaunay wrote:
Device tree property is named typec-power-opmode, not power-opmode.
Fixes: da0cb6310094 ("usb: typec: add support for STUSB160x Type-C controller
family")
Signed-off-
Device tree property is named typec-power-opmode, not power-opmode.
Fixes: da0cb6310094 ("usb: typec: add support for STUSB160x Type-C controller
family")
Signed-off-by: Amelie Delaunay
Reviewed-by: Heikki Krogerus
---
drivers/usb/typec/stusb160x.c | 2 +-
1 file changed, 1 inser
On 11/27/20 2:07 PM, Greg Kroah-Hartman wrote:
On Fri, Nov 27, 2020 at 02:01:29PM +0100, Amelie DELAUNAY wrote:
Hi Greg,
gentle reminder for this patch, lost in the middle of a DT series (DT part
already in stm32-next).
Odd, I don't see this anymore, can you resend just this one so I can
Hi Greg,
gentle reminder for this patch, lost in the middle of a DT series (DT
part already in stm32-next).
Thanks and regards,
Amelie
On 11/6/20 5:58 PM, Amelie Delaunay wrote:
Device tree property is named typec-power-opmode, not power-opmode.
Fixes: da0cb6310094 ("usb: typec
if a phy_exit is required to properly disable the PLL.
Signed-off-by: Amelie Delaunay
---
drivers/phy/st/phy-stm32-usbphyc.c | 88 ++
1 file changed, 54 insertions(+), 34 deletions(-)
diff --git a/drivers/phy/st/phy-stm32-usbphyc.c
b/drivers/phy/st/phy-stm32-usbphyc.c
index
dependent.
To ensure a good behavior of the PLL, supplies have to be managed at PLL
activation/deactivation. That means the supplies need to be put in usbphyc
parent node and not in phy children nodes.
Signed-off-by: Amelie Delaunay
---
Note that even with bindings change, it doesn't break
To ensure a good balancing of regulators, force PLL disable either by
reset or by clearing the PLLEN bit.
If waiting the powerdown pulse delay isn't enough, return -EPROBE_DEFER
instead of polling the PLLEN bit, which will be low at the next probe.
Signed-off-by: Amelie Delaunay
---
drivers/phy
To ensure a good balancing of regulators, and allow PLL disabling when the
driver is removed, call stm32_usbphyc_phy_exit on each ports to set phys
inactive and disable PLL.
Signed-off-by: Amelie Delaunay
---
drivers/phy/st/phy-stm32-usbphyc.c | 6 ++
1 file changed, 6 insertions(+)
diff
dependent.
To ensure a good behavior of the PLL, supplies have to be managed at PLL
activation/deactivation. That means the supplies need to be put in usbphyc
node and not in phy children nodes.
Signed-off-by: Amelie Delaunay
---
drivers/phy/st/phy-stm32-usbphyc.c | 102
Due to async_schedule_domain call in regulator_bulk_enable,
scheduling while atomic bug can raise if regulator_bulk_enable is called
under atomic context.
To avoid this issue, this patch replaces all regulator_bulk* by regulator_
per regulators.
Signed-off-by: Amelie Delaunay
---
drivers/phy/st
STM32 USBPHYC controls the USB PLL. PLL requires to be powered with 1v1 and 1v8
supplies. To ensure a good behavior of the PLL, during boot, runtime and
suspend/resume sequences, this series reworks its management to fix regulators
issues and improve PLL status reliability.
Amelie Delaunay (6
controller performance.
[1] https://www.st.com/resource/en/reference_manual/dm00327659.pdf, p.3149
Signed-off-by: Amelie Delaunay
---
drivers/usb/dwc2/params.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
index 267543c3dc38
Link Power Management on STM32MP15 HS OTG.
Signed-off-by: Amelie Delaunay
---
drivers/usb/dwc2/params.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
index 9e5dd7f3f2f6..92df3d620f7d 100644
--- a/drivers/usb/dwc2/params.c
+++ b/driver
), OTG doesn't
succeed to exit L1 state.
It also enables FS/LS PHY clock selection when the Core is in FS Host mode,
to have 6MHz PHY clock when the connected device is LS, and 48Mhz PHY clock
otherwise.
Amelie Delaunay (3):
usb: dwc2: set ahbcfg parameter for STM32MP15 OTG HS and FS
usb: dwc2
When the core is in FS host mode, using the FS transceiver, and a Low-Speed
device is connected, transceiver clock is 6Mhz.
So, to support Low-Speed devices, enable support of FS/LS Low Power mode,
so that the PHY supplies a 6 MHz clock during Low-Speed mode.
Signed-off-by: Amelie Delaunay
DMA_SxPAR or DMA_SxM0AR/M1AR registers have to be aligned on PSIZE or MSIZE
respectively. This means that bus width needs to be forced to 1 byte when
computed width is not aligned with address.
Signed-off-by: Amelie Delaunay
---
drivers/dma/stm32-dma.c | 19 ++-
1 file changed
To avoid multiple entries in MDMA interrupt handler for each flag
enable, manage all flags set at once.
Signed-off-by: Amelie Delaunay
---
drivers/dma/stm32-mdma.c | 64 +---
1 file changed, 34 insertions(+), 30 deletions(-)
diff --git a/drivers/dma/stm32
is set, we check if the channel is
disabled or not, and if a Transfer Complete flag is set, which means that
the channel is disabled because of the end of transfer.
Because channel is disabled by hardware either by a FIFO level error, or by
an end of transfer.
Signed-off-by: Amelie Delaunay
This series brings 3 patches for STM32 DMA and 1 for STM32 MDMA.
They increase the reliability and the efficiency of the transfers.
Amelie Delaunay (4):
dmaengine: stm32-dma: rework irq handler to manage error before xfer
events
dmaengine: stm32-dma: clean channel configuration when
When dma_channel_release is called, it means that the channel won't be used
anymore with the configuration it had. To ensure a future client can safely
use the channel after it has been released, clean the configuration done
when channel was requested.
Signed-off-by: Amelie Delaunay
---
drivers
Convert the STM32 USB PHY Controller (USBPHYC) bindings to DT schema format
using json-schema.
Signed-off-by: Amelie Delaunay
Reviewed-by: Rob Herring
---
v2: add additionalProperties also for child nodes and Rob's Reviewed-by
---
.../bindings/phy/phy-stm32-usbphyc.txt| 73
abled";
};
stmfx_ts: stmfx_ts {
status = "disabled";
};
Then, the warning "Failed to locate of_node [id: -1]" wont appear anymore.
.of_compatible could be added as soon as idd or ts bindings are described
and drivers available.
On 11/16/20 10:50 AM, Vinod Koul wrote:
On 16-11-20, 09:02, Amelie DELAUNAY wrote:
Hi Vinod,
On 11/16/20 8:37 AM, Vinod Koul wrote:
On 10-11-20, 11:23, Amelie Delaunay wrote:
Change stm32-usbphyc driver to not print an error message when the device
probe operation is deferred.
Applied all
Hi Vinod,
On 11/16/20 8:37 AM, Vinod Koul wrote:
On 10-11-20, 11:23, Amelie Delaunay wrote:
Change stm32-usbphyc driver to not print an error message when the device
probe operation is deferred.
Applied all, thanks
I'm sorry for the mess, I sent a v2 for the patch 1/2:
https
On 11/13/20 11:09 AM, Lee Jones wrote:
On Tue, 10 Nov 2020, Amelie Delaunay wrote:
ret may be 0 so, dev_err_probe should be called only when ret is an error
code.
Fixes: 41c9c06c491a ("mfd: stmfx: Simplify with dev_err_probe()")
Signed-off-by: Amelie Delaunay
---
drivers/mfd/s
ret may be 0 so, dev_err_probe should be called only when ret is an error
code.
Fixes: 41c9c06c491a ("mfd: stmfx: Simplify with dev_err_probe()")
Signed-off-by: Amelie Delaunay
---
v2: address Lee's comment about error handling area
---
drivers/mfd/stmfx.c | 10 +-
1 file
Update mdma1 clients channel priority level following stm32-mdma bindings.
Signed-off-by: Amelie Delaunay
---
arch/arm/boot/dts/stm32mp151.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/stm32mp151.dtsi
b/arch/arm/boot/dts/stm32mp151.dtsi
index
Reg property length should cover all DMAMUX_CxCR registers.
DMAMUX_CxCR Address offset: 0x000 + 0x04 * x (x = 0 to 15), so latest
offset is at 0x3c, so length should be 0x40.
Signed-off-by: Amelie Delaunay
---
arch/arm/boot/dts/stm32mp151.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion
Reg property length should cover all DMAMUX_CxCR registers.
DMAMUX_CxCR Address offset: 0x000 + 0x04 * x (x = 0 to 15), so latest
offset is at 0x3c, so length should be 0x40.
Signed-off-by: Amelie Delaunay
---
arch/arm/boot/dts/stm32h743.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion
Defaut use case on stm32mp151 USB OTG is ethernet gadget, using EP1 bulk
endpoint (MPS=512 bytes) and EP2 interrupt endpoint (MPS=16 bytes).
This patch optimizes USB OTG FIFO sizes accordingly.
Signed-off-by: Amelie Delaunay
---
arch/arm/boot/dts/stm32mp151.dtsi | 4 ++--
1 file changed, 2
Change stm32-usbphyc driver to not print an error message when the device
probe operation is deferred.
Signed-off-by: Etienne Carriere
Signed-off-by: Amelie Delaunay
---
v2: add missing return
---
drivers/phy/st/phy-stm32-usbphyc.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions
Convert the STM32 USB PHY Controller (USBPHYC) bindings to DT schema format
using json-schema.
Signed-off-by: Amelie Delaunay
---
.../bindings/phy/phy-stm32-usbphyc.txt| 73 --
.../bindings/phy/phy-stm32-usbphyc.yaml | 136 ++
2 files changed, 136
Change stm32-usbphyc driver to not print an error message when the device
probe operation is deferred.
Signed-off-by: Etienne Carriere
Signed-off-by: Amelie Delaunay
---
drivers/phy/st/phy-stm32-usbphyc.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/phy/st
Change stm32-usbphyc driver to defer its probe when the expected reset
control has its probe operation deferred.
Signed-off-by: Etienne Carriere
Signed-off-by: Amelie Delaunay
---
drivers/phy/st/phy-stm32-usbphyc.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/phy/st/phy
ret may be 0 so, dev_err_probe should be called only when ret is an error
code.
Fixes: 41c9c06c491a ("mfd: stmfx: Simplify with dev_err_probe()")
Signed-off-by: Amelie Delaunay
---
drivers/mfd/stmfx.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/mfd
On 11/9/20 5:02 PM, Rob Herring wrote:
On Mon, Nov 9, 2020 at 9:54 AM Amelie DELAUNAY wrote:
On 11/9/20 4:03 PM, Rob Herring wrote:
On Fri, Nov 6, 2020 at 10:58 AM Amelie Delaunay wrote:
Power operation mode may depends on hardware design, so, add the optional
property typec-power
On 11/9/20 4:03 PM, Rob Herring wrote:
On Fri, Nov 6, 2020 at 10:58 AM Amelie Delaunay wrote:
Power operation mode may depends on hardware design, so, add the optional
property typec-power-opmode for usb-c connector to select the power
operation mode capability.
Signed-off-by: Amelie
On 11/6/20 5:17 PM, Rob Herring wrote:
On Fri, 06 Nov 2020 10:18:51 +0100, Amelie Delaunay wrote:
Add binding documentation for the STMicroelectronics STUSB160x Type-C port
controller.
Signed-off-by: Amelie Delaunay
---
.../devicetree/bindings/usb/st,stusb160x.yaml | 85
Power operation mode may depends on hardware design, so, add the optional
property typec-power-opmode for usb-c connector to select the power
operation mode capability.
Signed-off-by: Amelie Delaunay
---
Hi Bahdri, Rob,
I've added the exlusion with FRS property, but new FRS property name
should
econnect the USB gadget:
echo connect >
/sys/devices/platform/soc/4900.usb-otg/udc/4900.usb-otg/soft_connect
With DWC2 usb-role-switch, USB gadget is dynamically disconnected or connected.
Signed-off-by: Amelie Delaunay
---
arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 7 ++
arc
/stm32mp157c-dk2.html
Amelie Delaunay (5):
dt-bindings: connector: add typec-power-opmode property to
usb-connector
dt-bindings: usb: Add DT bindings for STUSB160x Type-C controller
usb: typec: stusb160x: fix power-opmode property with
typec-power-opmode
ARM: dts: stm32: add
Add binding documentation for the STMicroelectronics STUSB160x Type-C port
controller.
Signed-off-by: Amelie Delaunay
---
.../devicetree/bindings/usb/st,stusb160x.yaml | 87 +++
1 file changed, 87 insertions(+)
create mode 100644 Documentation/devicetree/bindings/usb/st
Enable support for the STMicroelectronics STUSB160X USB Type-C port
controller driver by turning on CONFIG_TYPEC and CONFIG_TYPEC_STUSB160X as
modules.
Signed-off-by: Amelie Delaunay
---
arch/arm/configs/multi_v7_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/configs
Device tree property is named typec-power-opmode, not power-opmode.
Fixes: da0cb6310094 ("usb: typec: add support for STUSB160x Type-C controller
family")
Signed-off-by: Amelie Delaunay
Reviewed-by: Heikki Krogerus
---
drivers/usb/typec/stusb160x.c | 2 +-
1 file changed, 1 inser
econnect the USB gadget:
echo connect >
/sys/devices/platform/soc/4900.usb-otg/udc/4900.usb-otg/soft_connect
With DWC2 usb-role-switch, USB gadget is dynamically disconnected or connected.
Signed-off-by: Amelie Delaunay
---
arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 7 ++
arc
Enable support for the STMicroelectronics STUSB160X USB Type-C port
controller driver by turning on CONFIG_TYPEC and CONFIG_TYPEC_STUSB160X as
modules.
Signed-off-by: Amelie Delaunay
---
arch/arm/configs/multi_v7_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/configs
Add binding documentation for the STMicroelectronics STUSB160x Type-C port
controller.
Signed-off-by: Amelie Delaunay
---
.../devicetree/bindings/usb/st,stusb160x.yaml | 85 +++
1 file changed, 85 insertions(+)
create mode 100644 Documentation/devicetree/bindings/usb/st
Device tree property is named typec-power-opmode, not power-opmode.
Fixes: da0cb6310094 ("usb: typec: add support for STUSB160x Type-C controller
family")
Signed-off-by: Amelie Delaunay
---
drivers/usb/typec/stusb160x.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Power operation mode may depends on hardware design, so, add the optional
property typec-power-opmode for usb-c connector to select the power
operation mode capability.
Signed-off-by: Amelie Delaunay
---
Hi Bahdri, Rob,
I've added the exlusion with FRS property, but new FRS property name
should
/stm32mp157c-dk2.html
Amelie Delaunay (4):
dt-bindings: connector: add power-opmode optional property to
usb-connector
dt-bindings: usb: Add DT bindings for STUSB160x Type-C controller
usb: typec: stusb160x: fix power-opmode property with
typec-power-opmode
ARM: dts: stm32: add
Li wrote:
Amelie DELAUNAY 于2020年11月5日周四 下午7:36写道：
On 11/4/20 10:08 PM, Rob Herring wrote:
On Fri, Oct 30, 2020 at 04:27:14PM +0100, Amelie DELAUNAY wrote:
On 10/30/20 3:29 PM, Rob Herring wrote:
On Thu, Oct 29, 2020 at 11:49 AM Amelie DELAUNAY wrote:
On 10/29/20 4:40 PM, Rob Herring
On 11/5/20 1:23 PM, Jun Li wrote:
Amelie DELAUNAY 于2020年11月5日周四 下午7:36写道：
On 11/4/20 10:08 PM, Rob Herring wrote:
On Fri, Oct 30, 2020 at 04:27:14PM +0100, Amelie DELAUNAY wrote:
On 10/30/20 3:29 PM, Rob Herring wrote:
On Thu, Oct 29, 2020 at 11:49 AM Amelie DELAUNAY wrote:
On 10/29
On 11/4/20 10:08 PM, Rob Herring wrote:
On Fri, Oct 30, 2020 at 04:27:14PM +0100, Amelie DELAUNAY wrote:
On 10/30/20 3:29 PM, Rob Herring wrote:
On Thu, Oct 29, 2020 at 11:49 AM Amelie DELAUNAY wrote:
On 10/29/20 4:40 PM, Rob Herring wrote:
On Thu, Oct 29, 2020 at 10:58:03AM +0100
On 10/30/20 3:29 PM, Rob Herring wrote:
On Thu, Oct 29, 2020 at 11:49 AM Amelie DELAUNAY wrote:
On 10/29/20 4:40 PM, Rob Herring wrote:
On Thu, Oct 29, 2020 at 10:58:03AM +0100, Amelie Delaunay wrote:
Power operation mode may depends on hardware design, so, add the optional
property
On 10/29/20 4:40 PM, Rob Herring wrote:
On Thu, Oct 29, 2020 at 10:58:03AM +0100, Amelie Delaunay wrote:
Power operation mode may depends on hardware design, so, add the optional
property power-opmode for usb-c connector to select the power operation
mode capability.
Signed-off-by: Amelie
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