were only marked to provide pin-bank power.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun9i-a80-optimus.dts | 19 ---
1 file changed, 16 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts
b/arch/arm/boot/dts/sun9i-a80-optimus.dts
index 1e
The GMAC (gigabit ethernet controller) supports RGMII to connect to
the ethernet PHY, for gigabit network speeds.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun9i-a80.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot
The A80 has the same DWMAC hardware as on earlier Allwinner SoCs. The
accompanying GMAC clock register has been moved into the "System
Control" area.
Add a clock node for it.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun9i-a80.dtsi | 31 +++
1 fi
, it is omitted. It is however properly modeled for the PIO.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun9i-a80-cubieboard4.dts | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
The DC1SW output from the AXP809 is unused. Unused regulators should
still be listed so as to be considered to be fully constrained.
Fixes: aa4a27bc819e ("ARM: dts: sun9i: a80-optimus: Add AXP809 PMIC
device node and regulators")
Signed-off-by: Chen-Yu Tsai
---
, it is omitted. It is however properly modeled for the PIO.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun9i-a80-optimus.dts | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts
b/arch/arm/boot/dts/sun9i-a80-optimus.dts
index
to have a notifier on the regulator so that when
the voltage changes, the driver can update the setting, in practice no
board currently supports dynamic changing of the I/O voltages.
Signed-off-by: Chen-Yu Tsai
---
drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c | 1 +
drivers/pinctrl/sunxi/pinctrl
The A80 has the same GMAC found on the A31 SoC.
Add a device node, and an alias for it.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun9i-a80.dtsi | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80
were only marked to provide pin-bank power.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun9i-a80-cubieboard4.dts | 23 ++---
1 file changed, 20 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
b/arch/arm/boot/dts/sun9i-a80-cubieboard4
On Thu, Jan 31, 2019 at 4:25 PM Stefan Mavrodiev wrote:
>
> Add dt node for axp20x-led driver controlling CHGLED.
> Default status is disabled, since it may be not used.
>
> Signed-off-by: Stefan Mavrodiev
Please include a cover letter for such a patch series.
Also, do any boards actually use
have been parsed.
Cc:
Signed-off-by: Chen-Yu Tsai
---
This should be backported to stable kernels in case people try to run
new device trees (that declare newly supported modes) with old kernels.
---
drivers/mmc/host/sunxi-mmc.c | 15 +++
1 file changed, 15 insertions(+)
diff
to not enabling HS-DDR modes in
the driver, and expect the device tree to signal HS-DDR capability on
boards that work.
Reported-by: Chris Blake
Fixes: 07bafc1e3536 ("mmc: sunxi: Use new timing mode for A64 eMMC controller")
Cc:
Acked-by: Maxime Ripard
Signed-off-by: Chen-Yu Tsai
---
d
please merge all of them as fixes.
Regards
ChenYu
Chen-Yu Tsai (3):
mmc: sunxi: Disable HS-DDR mode for H5 eMMC controller by default
mmc: sunxi: Filter out unsupported modes declared in the device tree
arm64: dts: allwinner: h5: libretech-all-h3-cc: Mark eMMC HS-DDR 3.3V
capable
The Libre Computer ALL-H3-CC H5 is one of the few boards that can have
its eMMC run at HS-DDR speed mode. Mark it as such.
Signed-off-by: Chen-Yu Tsai
---
.../boot/dts/allwinner/sun50i-h5-libretech-all-h3-cc.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts
On Sun, Feb 3, 2019 at 8:07 AM Christopher Diaz Riveros
wrote:
>
> Use PTR_ERR_OR_ZERO rather than if(IS_ERR(...)) + PTR_ERR
Maxime's reply to the patch "drm/sun4i: hdmi: Use PTR_ERR_OR_ZERO
in sun4i_tmds_create()" [1] probably applies to this one as well:
"""
While this is technically correct
supplies in the device tree.
Signed-off-by: Chen-Yu Tsai
---
arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 8
arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts | 4
arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts| 8
arch/arm64/boot/dts
to the
ACIN pins, but there are no battery connectors.
Enable these power supplies in the device tree.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts | 4
arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts | 8
arch/arm/boot/dts/sun8i
On Tue, Feb 5, 2019 at 4:55 PM Sakari Ailus
wrote:
>
> Hi Chen-Yu,
>
> On Fri, Jan 18, 2019 at 04:52:06PM +0800, Chen-Yu Tsai wrote:
> > The register value lists for all the supported resolution settings all
> > include a register address/value pair for setting the J
On Tue, Feb 5, 2019 at 5:45 PM Maxime Ripard wrote:
>
> On Sat, Feb 02, 2019 at 05:52:09PM +0200, Priit Laes wrote:
> > Recent patch of improving MP clock rate calculations by taking
> > into account whether adjusting parent rate is allowed, have
> > unfortunately broken eMMC support on A20
On Mon, Feb 4, 2019 at 9:41 PM Maxime Ripard wrote:
>
> On Mon, Feb 04, 2019 at 06:16:24PM +0800, Chen-Yu Tsai wrote:
> > On Mon, Feb 4, 2019 at 5:34 PM Maxime Ripard
> > wrote:
> > >
> > > On Sun, Feb 03, 2019 at 11:56:27PM +0800, Chen-Yu Tsai wrote:
On Sat, Dec 22, 2018 at 7:32 PM Colin King wrote:
>
> From: Colin Ian King
>
> Currently rdev is dereferenced when assigning desc before rdev is null
> checked, hence there is a potential null pointer dereference on rdev.
> Fix this by null checking rdev first.
>
> Detected by CoverityScan,
On Mon, Feb 4, 2019 at 5:34 PM Maxime Ripard wrote:
>
> On Sun, Feb 03, 2019 at 11:56:27PM +0800, Chen-Yu Tsai wrote:
> > The MMC device tree bindings include properties used to signal various
> > signalling speed modes. Until now the sunxi driver was accepting them
>
The CSI controller can take raw data from the data bus and output RGB565
format. The controller does not distinguish between RGB565 LE and BE.
Instead this is determined by the media bus format, i.e. the format or
order the sensor is sending data in.
Signed-off-by: Chen-Yu Tsai
---
.../platform
orgetting to
send out this one.
Please have a look.
Regards
ChenYu
Chen-Yu Tsai (3):
media: sun6i: Fix CSI regmap's max_register
media: sun6i: Add support for RGB565 formats
media: sun6i: Add support for JPEG media bus format
.../platform/sunxi/sun6i-csi/sun6i_csi.c | 27 +++
to 0x9c, the last known
register on the V3s and H3.
On the A31, the register range is extended to support additional
capture channels. Since this is not yet supported, ignore it for now.
Fixes: 5cc7522d8965 ("media: sun6i: Add support for Allwinner CSI V3s")
Cc:
Signed-off-by: Ch
, even when the on-bus data is framed correctly, we have no way to
accertain the actual amount of data captured, unless we scan the buffer
for JPEG EOI markers, or sequential zeros. For now we leave bytesused
alone, and leave it up to userspace applications to parse the data.
Signed-off-by: Chen-Yu
modes the driver
doesn't support. In retrospect this should have been added a long time
ago.
Patch 3 enables HS-DDR for the Libre Computer ALL-H3-CC H5, which works
normally.
If possible please merge all of them as fixes.
Regards
ChenYu
Chen-Yu Tsai (3):
mmc: sunxi: Disable HS-DDR mode for H5
The Libre Computer ALL-H3-CC H5 is one of the few boards that can have
its eMMC run at HS-DDR speed mode. Mark it as such.
Signed-off-by: Chen-Yu Tsai
---
.../boot/dts/allwinner/sun50i-h5-libretech-all-h3-cc.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts
. In retrospect this should have been added a long time
ago.
Patch 3 enables HS-DDR for the Libre Computer ALL-H3-CC H5, which works
normally.
If possible please merge all of them as fixes.
Regards
ChenYu
Chen-Yu Tsai (3):
mmc: sunxi: Disable HS-DDR mode for H5 eMMC controller by default
mmc
have been parsed.
Cc:
Signed-off-by: Chen-Yu Tsai
---
This should be backported to stable kernels in case people try to run
new device trees (that declare newly supported modes) with old kernels.
---
drivers/mmc/host/sunxi-mmc.c | 16
1 file changed, 16 insertions(+)
diff
to not enabling HS-DDR modes in
the driver, and expect the device tree to signal HS-DDR capability on
boards that work.
Reported-by: Chris Blake
Fixes: 07bafc1e3536 ("mmc: sunxi: Use new timing mode for A64 eMMC controller")
Cc:
Signed-off-by: Chen-Yu Tsai
---
drivers/mmc/host/sunxi-
On Wed, Jan 30, 2019 at 5:41 PM Chen-Yu Tsai wrote:
>
> On Wed, Jan 30, 2019 at 5:29 PM Maxime Ripard
> wrote:
> >
> > On Wed, Jan 30, 2019 at 04:42:03PM +0800, Chen-Yu Tsai wrote:
> > > enable-method = "psci";
> &g
On Wed, Jan 30, 2019 at 5:29 PM Maxime Ripard wrote:
>
> On Wed, Jan 30, 2019 at 04:42:03PM +0800, Chen-Yu Tsai wrote:
> > enable-method = "psci";
> > clocks = < CLK_CPUX>;
> > clock
The ARM CPU cores are fed by the CPU clock from the CCU. Add a
reference to the clock for each CPU core, along with the clock
transition latency.
Signed-off-by: Chen-Yu Tsai
---
arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64
The Nanopi Neo 2 uses a fixed regulator to supply the CPU cores. The
feedback resistor network can be changed by toggling a GPIO line. This
is effectively a GPIO controlled regulator that can change between 1.1V
and 1.3V.
Cc: Icenowy Zheng
Signed-off-by: Chen-Yu Tsai
---
This patch is based
Zheng
Signed-off-by: Chen-Yu Tsai
---
This patch is based on the schematics and has not been tested on an
actual board.
---
.../allwinner/sun50i-h5-orangepi-prime.dts| 28 +++
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi
ibre Computer ALL-H3-CC-H5 and the Bananapi
M2+ v1.2 H5, both with adequate cooling. The former has a fixed 1.2V
regulator, while the latter has a GPIO controlled regulator switchable
between 1.1V and 1.3V.
Signed-off-by: Chen-Yu Tsai
---
arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
Przywara
Cc: Icenowy Zheng
Cc: Emmanuel Vadot
Signed-off-by: Chen-Yu Tsai
---
This patch is based on the schematics and has not been tested on an
actual board.
---
.../dts/allwinner/sun50i-h5-orangepi-pc2.dts | 28 +++
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot
Some of the device trees for H5 boards already have the CPU supply
regulator defined, but they are not referenced in the CPU node.
Add the reference, so CPU DVFS mechanisms can see them.
Signed-off-by: Chen-Yu Tsai
---
.../boot/dts/allwinner/sun50i-h5-emlid-neutis-n5-devboard.dts | 4
in the device tree description are based on calculations using the
resistor values from the schematics.
Cc: Hauke Mehrtens
Signed-off-by: Chen-Yu Tsai
---
This patch is based on the schematics and has not been tested on an
actual board.
---
.../sun50i-h5-orangepi-zero-plus.dts | 20
The original Bananapi M2+ uses a fixed regulator to supply the CPU
cores. According to Bananapi, the retail v1.1 version is designed to
supply 1.3V. Actual measurements show 1.310V. Earlier engineering
samples had it at 1.4V, but this is not covered here.
Signed-off-by: Chen-Yu Tsai
in the device tree description are based on calculations using the
resistor values from the schematics.
Cc: Jagan Teki
Cc: Sergey Matyukevich
Signed-off-by: Chen-Yu Tsai
---
This patch is based on the schematics and has not been tested on an
actual board.
---
.../sun50i-h5-orangepi-zero-plus2.dts
on calculations of the feedback resistor
network, and verified down to three decimal places with a multi-meter.
Fixes: 6eeb4180d4b9 ("ARM: dts: sunxi: h3-h5: Add Bananapi M2+ v1.2 device
trees")
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sunxi-bananapi-m2-plus-v1.2.dtsi | 8 +
the OPP table, based on the one from Armbian.
Please have a look and please help test this.
Regards
ChenYu
Chen-Yu Tsai (10):
ARM: dts: sunxi: bananapi-m2-plus-v1.2: Fix CPU supply voltages
ARM: dts: bananapi-m2-plus: Add CPU supply regulator
arm64: dts: allwinner: h5: Hook up cpu
The GIC device node was placed out of order in the initial device tree
submission. Move it so the nodes are correctly sorted by base address
again.
Fixes: e54be32d0273 ("arm64: allwinner: h6: add the basical Allwinner H6 DTSI
file")
Signed-off-by: Chen-Yu Tsai
---
arch/arm64/boot/dts
d_get_value_cansleep().
Fixes: 0c9501f823a4 ("backlight: pwm_bl: Handle gpio that can sleep")
Signed-off-by: Chen-Yu Tsai
---
drivers/video/backlight/pwm_bl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/video/backlight/pwm_bl.c b/drivers/video/backlig
in the device tree. Both are controlled with MOSFETs
by the enable GPIO added in the previous patch. The actual enable or
reset pin for the panel is tied directly to LCD-VCC after the MOSFET.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun5i-a13-q8-tablet.dts | 1 +
1 file changed, 1 insertion
The panel backlight and enable GPIO comments were incorrectly placed
in the input port, while it should have been in the panel node itself.
Move them to the correct position.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun5i-a13-q8-tablet.dts | 4 ++--
1 file changed, 2 insertions(+), 2
Now that we support the AXP209 GPIOs, we can toggle the LCD panel enable
line. Add the GPIO phandle to the panel.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun5i-a13-q8-tablet.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun5i-a13-q8
dimensions, and the timings have been shown to
work with the nameless panels, we can use that one instead.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun5i-a13-q8-tablet.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts
b/arch/arm
a look.
Regards
ChenYu
Chen-Yu Tsai (5):
ARM: dts: sun5i: Add backlight GPIO for reference design tablet
ARM: dts: sun5i: q8-tablet: Move panel properties to correct node
level
ARM: dts: sun5i: q8-tablet: Add LCD Panel enable GPIO
ARM: dts: sun5i: q8-tablet: Add LCD Panel power supply
Now that we support the GPIOs on the AXP209, we can control the LCD
backlight with them.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi
f7c4cf ("regulator: axp20x: use defines for masks")
> Signed-off-by: Vasily Khoruzhick
Reviewed-by: Chen-Yu Tsai
by this patch.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-a23.dtsi | 20
1 file changed, 20 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi
index d00055e9eef5..a5e884a8b2ae 100644
--- a/arch/arm/boot/dts/sun8i-a23.dtsi
be applied for -next
and then backported.
Also, the fixes tags are no longer line wrapped, unlike patches I've
sent in the past.
Regards
ChenYu
Chen-Yu Tsai (11):
clk: sunxi-ng: sun8i-a23: Enable PLL-MIPI LDOs when ungating it
dt-bindings: display: sun4i-drm: Add compatible strings for A23
.
As the MIPI DSI output device is not officially documented, and there
are no A23 reference devices to test it, it is not covered by this
patch.
Signed-off-by: Chen-Yu Tsai
---
.../devicetree/bindings/display/sunxi/sun4i-drm.txt | 5 +
1 file changed, 5 insertions(+)
diff --git
The PLL-MIPI clock is somewhat special as it has its own LDOs which
need to be turned on for this PLL to actually work and output a clock
signal.
Add the 2 LDO enable bits to the gate bits.
Fixes: 5690879d93e8 ("clk: sunxi-ng: Add A23 CCU")
Signed-off-by: Chen-Yu Tsai
---
drivers/cl
e BGRX from list of supported formats by the backend.
Fixes: 3d4265f89d06 ("drm/sun4i: backend: Add a helper and a list for supported
formats")
Signed-off-by: Chen-Yu Tsai
---
drivers/gpu/drm/sun4i/sun4i_backend.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/s
iled modifier support and helper")
Signed-off-by: Chen-Yu Tsai
---
drivers/gpu/drm/sun4i/sun4i_layer.c | 34 ++---
1 file changed, 31 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_layer.c
b/drivers/gpu/drm/sun4i/sun4i_layer.c
index 95d4aaa51a5
.
As the MIPI DSI output device is not officially documented, and there
are no A23 reference devices to test it, it is not covered by this
patch.
Signed-off-by: Chen-Yu Tsai
---
drivers/gpu/drm/sun4i/sun4i_backend.c | 4
drivers/gpu/drm/sun4i/sun4i_drv.c | 2 ++
drivers/gpu/drm/sun4i
the display pipeline.
The actual model or compatible string for the panel should be added in
the tablet device tree file.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-q8-common.dtsi | 37 ++
1 file changed, 37 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-q8
are close to what was provided in the vendor fex files.
Since there are also A33 Q8 tablets with 1024x600 panels, this patch
only sets the compatible string for A23 Q8 tablets.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-a23-q8-tablet.dts | 4
1 file changed, 4 insertions(+)
diff --
, and there
are no A23 reference devices to test it, it is not covered by this
patch.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-a23-a33.dtsi | 147
arch/arm/boot/dts/sun8i-a33.dtsi | 194 ++-
2 files changed, 185 insertions(+), 156 deletions
We might want to use the backend pointer from DRM callbacks that get
called within drm_universal_plane_init(), such as the
.format_mod_supported callback.
Move the assignment of the layer's backend pointer to right after the
structure is allocated.
Signed-off-by: Chen-Yu Tsai
---
drivers/gpu
3/A33")
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-a23-a33.dtsi | 28 +---
1 file changed, 13 insertions(+), 15 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
index a9c123de5d2c..97ec8b8cec09 100644
On Fri, Jan 25, 2019 at 2:57 AM Jernej Škrabec wrote:
>
> Dne ponedeljek, 21. januar 2019 ob 10:57:57 CET je Chen-Yu Tsai napisal(a):
> > On Mon, Jan 21, 2019 at 5:50 PM Maxime Ripard
> wrote:
> > > Hi,
> > >
> > > I'm a bit late to the party, sorry
On Tue, Jan 22, 2019 at 9:38 PM Rob Herring wrote:
>
> On Mon, Jan 21, 2019 at 8:16 PM Chen-Yu Tsai wrote:
> >
> > On Tue, Jan 22, 2019 at 8:19 AM Rob Herring wrote:
> > >
> > > On Mon, Jan 21, 2019 at 05:57:57PM +0800, Chen-Yu Tsai wrote:
> > > &g
On Mon, Dec 3, 2018 at 5:46 PM Jagan Teki wrote:
>
> On Fri, Nov 30, 2018 at 1:28 PM Chen-Yu Tsai wrote:
> >
> > Some camera modules have the SoC feeding a master clock to the sensor
> > instead of having a standalone crystal. This clock signal is generated
> &g
On Mon, Dec 3, 2018 at 5:44 PM Jagan Teki wrote:
>
> On Fri, Nov 30, 2018 at 1:29 PM Chen-Yu Tsai wrote:
> >
> > The CSI controller found on the H3 (and H5) is a reduced version of the
> > one found on the A31. It only has 1 channel, instead of 4 channels for
> >
On Sun, Jan 13, 2019 at 10:17 AM Samuel Holland wrote:
>
> As instability in the architectural timer has been observed on multiple
> devices using this SoC, inluding the Pine64 and the Orange Pi Win,
> enable the workaround in the SoC's device tree.
>
> Acked-by: Maxime Ripard
> Signed-off-by:
On Thu, Jan 24, 2019 at 5:39 PM Daniel Lezcano
wrote:
>
> On 24/01/2019 09:56, Chen-Yu Tsai wrote:
> > On Thu, Jan 10, 2019 at 5:19 PM Daniel Lezcano
> > wrote:
> >>
> >> On 10/01/2019 07:22, Chen-Yu Tsai wrote:
> >>> If the clock tree is no
On Thu, Jan 10, 2019 at 5:19 PM Daniel Lezcano
wrote:
>
> On 10/01/2019 07:22, Chen-Yu Tsai wrote:
> > If the clock tree is not fully populated when the timer-sun5i init code
> > is called, attempts to get the clock rate for the timer would fail and
> > return 0.
&g
Hi,
On Tue, Jan 22, 2019 at 6:42 AM Stephen Rothwell wrote:
>
> Hi Linus,
>
> In commit
>
> 15d90c339a7f ("pinctrl: sunxi: Correct number of IRQ banks on H6 main pin
> controller")
>
> Fixes tag
>
> Fixes: c8a830904991 ("pinctrl: sunxi: add support for the Allwinner H6
>
> has these
On Tue, Jan 22, 2019 at 8:19 AM Rob Herring wrote:
>
> On Mon, Jan 21, 2019 at 05:57:57PM +0800, Chen-Yu Tsai wrote:
> > On Mon, Jan 21, 2019 at 5:50 PM Maxime Ripard
> > wrote:
> > >
> > > Hi,
> > >
> > > I'm a bit late to the party, sor
On Tue, Jan 22, 2019 at 1:33 AM Jernej Škrabec wrote:
>
> Dne ponedeljek, 21. januar 2019 ob 10:57:57 CET je Chen-Yu Tsai napisal(a):
> > On Mon, Jan 21, 2019 at 5:50 PM Maxime Ripard
> wrote:
> > > Hi,
> > >
> > > I'm a bit late to the party, sorry
On Mon, Jan 21, 2019 at 5:50 PM Maxime Ripard wrote:
>
> Hi,
>
> I'm a bit late to the party, sorry for that.
>
> On Sat, Jan 12, 2019 at 09:56:11AM +0800, Chen-Yu Tsai wrote:
> > On Sat, Jan 12, 2019 at 1:30 AM Jernej Skrabec
> > wrote:
> > >
> >
place,
instead of being listed in the register dumps.
Please have a look.
Regards
ChenYu
Chen-Yu Tsai (6):
media: ov5640: Move test_pattern_menu before
ov5640_set_ctrl_test_pattern
media: ov5640: Add register definition for test pattern register
media: ov5640: Disable transparent fe
us to add a
matching list of values to program into the hardware, while keeping the
two lists together for ease of maintenance.
Signed-off-by: Chen-Yu Tsai
---
drivers/media/i2c/ov5640.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/media/i2c/ov5640.c b
The OV5640 can generate many types of test patterns, some with
additional modifiers, such as a rolling bar, or gamma gradients.
Add the bit definitions for all bits in the test pattern register,
and use them to compose the values to be written to the register.
Signed-off-by: Chen-Yu Tsai
gradient)
- static color squares
- color squares with a rolling bar
Signed-off-by: Chen-Yu Tsai
---
drivers/media/i2c/ov5640.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/media/i2c/ov5640.c b/drivers/media/i2c/ov5640.c
index a1fd69a21df1..13311483792c 100644
per line than expected, and having the extra data
dropped. This ultimately results in corrupted data.
Set the two values when the media bus is configured for JPEG data,
meaning the sensor would be in JPEG mode.
Signed-off-by: Chen-Yu Tsai
---
drivers/media/i2c/ov5640.c | 21
padding data on the last line, while mode 3 does not add padding data.
As these register values were from dumps of running systems, and the
difference between the modes is quite small, using mode 3 for all
configurations should be OK.
Signed-off-by: Chen-Yu Tsai
---
drivers/media/i2c/ov5640.c | 34
feature of the test pattern.
Signed-off-by: Chen-Yu Tsai
---
drivers/media/i2c/ov5640.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/media/i2c/ov5640.c b/drivers/media/i2c/ov5640.c
index 22d07b3cc8a2..a1fd69a21df1 100644
--- a/drivers/media/i2c/ov5640.c
+++ b
On Mon, Jan 14, 2019 at 8:57 PM Daniel Lezcano
wrote:
>
> On 13/01/2019 03:17, Samuel Holland wrote:
> > This is the third version of a patch series to fix system clock jumps
> > and other timer instability on the Allwinner A64 SoC. It has now been
> > tested for a week, and I've received no
for the Allwinner H6
main pin controller")
Cc:
Signed-off-by: Chen-Yu Tsai
---
drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c
b/drivers/pinctrl/sunxi/pinctrl-sun50i-
ators")
Acked-by: Maxime Ripard
Signed-off-by: Chen-Yu Tsai
---
Changes since v1:
- Moved before the other fix. Both fixes are needed, but having this
one first made reworking the other one easier.
---
drivers/pinctrl/sunxi/pinctrl-sunxi.c | 36 ---
1 file c
y to 9, just enough to cover
"PA" to "PI".
Fixes: 9a2a566adb00 ("pinctrl: sunxi: Deal with per-bank regulators")
Signed-off-by: Chen-Yu Tsai
---
Changes since v1:
- Take in to account pin_base when handling regulator array index
instead of enlarging the arra
On Sat, Jan 12, 2019 at 1:30 AM Jernej Skrabec wrote:
>
> A64 IR is compatible with A13, so add A64 compatible with A13 as a
> fallback.
We ask people to add the SoC-specific compatible as a contigency,
in case things turn out to be not so "compatible".
To be consistent with all the other SoCs
On Thu, Jan 10, 2019 at 11:26 PM Maxime Ripard
wrote:
>
> Hi,
>
> On Thu, Jan 10, 2019 at 04:26:32PM +0800, Chen-Yu Tsai wrote:
> > On the A80, the pin banks go up to PN, which translates to the 14th
> > entry in the regulator array. The array is only 12 entrie
based on the last pin of the pin controller, the size reduction probably
isn't worth the additional code complexity.
Fixes: 9a2a566adb00 ("pinctrl: sunxi: Deal with per-bank regulators")
Signed-off-by: Chen-Yu Tsai
---
This fixes a crash due to an invalid pointer on the A80.
---
drive
ators")
Signed-off-by: Chen-Yu Tsai
---
I'm getting the feeling that the current code is prone to race
conditions when pinctrl sets are actively switched during runtime, or
gpios are requested and freed from userspace.
Any ideas?
---
drivers/pinctrl/sunxi/pinctrl-su
of
causing a divide by 0 exception later on.
Fixes: 4a59058f0b09 ("clocksource/drivers/sun5i: Refactor the current code")
Signed-off-by: Chen-Yu Tsai
---
drivers/clocksource/timer-sun5i.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/clocksource/timer-sun5i.c
.
And any other devices that use muxed pins are guaranteed to be
initialized after the pin controller. Thus having the CLK_OUT_A pinmux
reference be in the pin controller node is a good choice without having
to deal with implementation issues.
Signed-off-by: Chen-Yu Tsai
---
.../boot/dts/sun8i
bound together". The name and constraints
of DLDO2 are also added.
Fixes: da7ac948fa93 ("ARM: dts: sun8i: Add board dts file for Banana Pi M2
Ultra")
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 15 +++
1 file ch
, but this is not covered here.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi
b/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi
index
reference either
just the RX/TX pinmux setting or both, depending on the application.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-r40.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
index
CLK_OUT_A, an external clock output function driven from the clock
control unit, on the R40 is sometimes used to provide a low rate low
power clock to a WiFi or Bluetooth controller.
This patch adds a pinmux setting for it.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-r40.dtsi | 5
are the A80-based boards, which I haven't gotten
working yet.
Chen-Yu Tsai (5):
ARM: dts: sun8i: r40: Add pinmux settings for UART3 on PG pingroup
ARM: dts: sun8i: r40: Add pinmux setting for CLK_OUT_A
ARM: dts: sun8i: r40: bananapi-m2-ultra: Fix WiFi regulator
definitions
ARM: dts: sun8i
On Wed, Jan 9, 2019 at 6:12 PM Maxime Ripard wrote:
>
> On Tue, Jan 08, 2019 at 08:18:40PM +0100, Jernej Skrabec wrote:
> > Because "ethernet0" alias is missing, U-Boot doesn't generate board
> > specific MAC address. Effect of this is random MAC address every boot
> > and thus new IP address is
unxi-ng
clock driver implicitly depends on the external clock being named
"osc24M".
Add a "clock-output-names" property to restore the previous behavior.
Fixes: acfd5bbe2641 ("ARM: dts: sun6i: Change clock node names to avoid
warnings")
Signe
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