On Fri, Mar 08, 2024 at 05:18:21PM +0800, Andy Chiu wrote:
> Hi Puranjay,
>
> On Fri, Mar 8, 2024 at 3:53 AM Puranjay Mohan wrote:
> >
> > Hi Björn,
> >
> > On Thu, Mar 7, 2024 at 8:27 PM Björn Töpel wrote:
> > >
> > > Puranjay!
> > >
> > > Puranjay Mohan writes:
> > >
> > > > This patch
h/csky/include/asm/page.h
> @@ -84,7 +84,7 @@ static inline unsigned long virt_to_pfn(const void *kaddr)
>
> static inline void * pfn_to_virt(unsigned long pfn)
> {
> - return (void *)((unsigned long)__va(pfn) << PAGE_SHIFT);
> + return __va(pfn << PAGE_
;< PAGE_SHIFT);
Oh, that's a terrible bug; Thx for fixing it.
Reviewed-by: Guo Ren
> }
> #define pfn_to_virt pfn_to_virt
>
> --
> 2.17.1
>
--
Best Regards
Guo Ren
CPU out of idle, as opposed to setting TIF_NEED_RESCHED previously. This
> avoids spurious calls to schedule_idle() in cases where an IPI does not
> necessarily wake up a task on the idle CPU.
>
> Cc: Guo Ren
> Cc: "Rafael J. Wysocki"
> Cc: Daniel Lezcano
> Cc: Ingo Molnar
On Mon, Feb 19, 2024 at 11:40 PM Anna-Maria Behnsen
wrote:
>
> There is already a generic union definition for vdso_data_store in vdso
> datapage header.
>
> Use this definition to prevent code duplication.
>
> Signed-off-by: Anna-Maria Behnsen
> Cc: Guo Ren
> Cc:
On Mon, Feb 19, 2024 at 11:40 PM Anna-Maria Behnsen
wrote:
>
> CSKY selects GENERIC_TIME_VSYSCALL. GENERIC_TIME_VSYSCALL dependent
> ifdeffery is superfluous. Clean it up.
>
> Signed-off-by: Anna-Maria Behnsen
> Cc: Guo Ren
> Cc: linux-c...@vger.kernel.org
> ---
> a
Sorry, I missed people on the list.
F.Y.I
Waiman Long
Boqun Feng
Here is Link:
https://lore.kernel.org/linux-riscv/20231225125847.2778638-1-guo...@kernel.org/
On Mon, Dec 25, 2023 at 8:59 PM wrote:
>
> From: Guo Ren
>
> patch[1 - 8]: Native qspinlock
> patch[9 -14]: Par
On Mon, Oct 16, 2023 at 2:00 AM Alejandro Colomar wrote:
>
> Hi Guo,
>
> On Sun, Oct 15, 2023 at 11:07:32AM -0400, guo...@kernel.org wrote:
> > From: Guo Ren
> >
> > C-SKY only needs set_thread_area, no need for get_thread_area, the
> > same as MIPS.
> &
On Sun, Oct 15, 2023 at 01:20:42AM +0200, Alejandro Colomar wrote:
> Hi Guo,
>
> On Tue, Nov 24, 2020 at 08:07:07PM +0800, Guo Ren wrote:
>
> Huh, 3 years already! I've had this in my head for all this time; just
> didn't find the energy to act on it.
>
> &
On Wed, Oct 11, 2023 at 8:53 PM Masahiro Yamada wrote:
>
> On Wed, Oct 11, 2023 at 11:24 AM Guo Ren wrote:
> >
> > On Mon, Oct 9, 2023 at 8:42 PM Masahiro Yamada wrote:
>
> > > --- a/arch/riscv/Makefile
> > > +++ b/arch/riscv/Makefile
> > > @@ -13
LIB)/vdso
> - $(call cmd,vdso_install)
> -
> -PHONY += vdso_install $(vdso_img_insttargets)
> -vdso_install: $(vdso_img_insttargets)
> -
> clean-files := vdso32.so vdso32.so.dbg vdso64* vdso-image-*.c vdsox32.so*
> diff --git a/scripts/Makefile.vdsoinst b/scripts/Makefile.vdsoinst
> new file mode 100644
> index ..1022d9fdd976
> --- /dev/null
> +++ b/scripts/Makefile.vdsoinst
> @@ -0,0 +1,45 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +# ==
> +# Install unstripped copies of vDSO
> +# ==
> +
> +PHONY := __default
> +__default:
> + @:
> +
> +include $(srctree)/scripts/Kbuild.include
> +
> +install-dir := $(MODLIB)/vdso
> +
> +define gen_install_rules
> +
> +src := $$(firstword $$(subst :,$(space),$(1)))
> +dest := $(install-dir)/$$(or $$(word 2,$$(subst
> :,$(space),$(1))),$$(patsubst %.dbg,%,$$(notdir $(1
> +
> +__default: $$(dest)
> +$$(dest): $$(src) FORCE
> + $$(call cmd,install)
> +
> +# Some architectures create .build-id symlinks
> +ifneq ($(filter arm sparc x86, $(SRCARCH)),)
> +link := $(install-dir)/.build-id/$$(shell $(READELF) -n $$(src) | sed -n
> 's@^.*Build ID: \(..\)\(.*\)@\1/\2@p')
> +
> +__default: $$(link)
> +$$(link): $$(dest) FORCE
> + $$(call cmd,symlink)
> +endif
> +
> +endef
> +
> +$(foreach x, $(sort $(INSTALL_FILES)), $(eval $(call
> gen_install_rules,$(x
> +
> +quiet_cmd_install = INSTALL $@
> + cmd_install = mkdir -p $(dir $@); cp $< $@
> +
> +quiet_cmd_symlink = SYMLINK $@
> + cmd_symlink = mkdir -p $(dir $@); ln -sf --relative $< $@
> +
> +PHONY += FORCE
> +FORCE:
> +
> +.PHONY: $(PHONY)
> --
> 2.39.2
>
--
Best Regards
Guo Ren
On Mon, Oct 9, 2023 at 8:42 PM Masahiro Yamada wrote:
>
> You cannot run this code because arch/csky/Makefile does not define the
> vdso_install target.
>
> It appears that this code was blindly copied from another architecture.
Yes, I do that. Thx for pointing it out.
Ac
a separate patch.
>
> x86 uses an inline function here instead of the macro. This would also
> be my preference, but it may add complexity to avoid circular header
> dependencies.
>
> The rest of this patch looks good to me.
>
> Arnd
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
Abandoned, it has duplicated definition export in gen-atomic-instrumented.sh
On Sat, Apr 17, 2021 at 10:57 AM wrote:
>
> From: Guo Ren
>
> Current GENERIC_ATOMIC64 in atomic-arch-fallback.h is broken. When a 32-bit
> arch use atomic-arch-fallback.h will cause compile error.
>
or, i)
> > ATOMIC_OPS(xor, xor, i)
> > +ATOMIC_OPS(andnot, and, -i)
>
> ~i, surely.
Thx for correct me. I'll fix it in the next version patch.
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
t; ATOMIC_OPS(and, and, i)
> > ATOMIC_OPS( or, or, i)
> > ATOMIC_OPS(xor, xor, i)
> > +ATOMIC_OPS(andnot, and, -i)
>
> ~i, surely.
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
__always_inline int ticket_is_contended(arch_spinlock_t *lock)
> +{
> + u32 val = atomic_read(lock);
> +
> + return (s16)((val >> 16) - (val & 0x)) > 1;
How big-endian ?
return (tickets.next - tickets.owner) > 1;
> +}
> +
> +static __always_inline int ticket_value_unlocked(arch_spinlock_t lock)
> +{
> + return !ticket_is_locked();
Are you sure to let ticket_is_locked->atomic_read(lock) again, the
lock has contained all information?
return lock.tickets.owner == lock.tickets.next;
> +}
> +
> +#define arch_spin_lock(l) ticket_lock(l)
> +#define arch_spin_trylock(l) ticket_trylock(l)
> +#define arch_spin_unlock(l)ticket_unlock(l)
> +#define arch_spin_is_locked(l) ticket_is_locked(l)
> +#define arch_spin_is_contended(l) ticket_is_contended(l)
> +#define arch_spin_value_unlocked(l)ticket_value_unlocked(l)
> +
> +#endif /* __ASM_GENERIC_TICKET_LOCK_H */
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
d
>
> -
> Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1
> 1PT, UK
> Registration No: 1397386 (Wales)
>
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
gt; void unlock(atomic_t *lock)
> > {
> > u16 *ptr = (u16 *)lock + (!!__BIG_ENDIAN__);
> > u32 val = atomic_read(lock);
> >
> > smp_store_release(ptr, (u16)val + 1);
> > }
> >
> > That's _almost_ as simple as a test-and-set :-) It isn't
etry the transaction.
This patch prefixes our {spin,read,write}_[try]lock implementations with
pldw instructions (on CPUs which support them) to try and grab the line
in exclusive state from the start. arch_rwlock_t is changed to avoid
using a volatile member, since this generates compiler warnings when
falling back on the __builtin_prefetch intrinsic which expects a const
void * argument.
Acked-by: Nicolas Pitre
Signed-off-by: Will Deacon
In the end, I want to conclude my suggestions here:
- Using ticket-lock as default
- Using ARCH_USE_QUEUED_SPINLOCKS_XCHG32 for riscv qspinlock
- Disable xhg16/cmxchg16 and any sub-word atomic primitive in riscv
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
equal to the resource means that
> the '(void *)0' start is correct.
>
> As this leaves only two others, I checked those as well:
>
> csky does not actually have a PCI host bridge driver at the moment, so
> we don't care about breaking port access on it it, and I would suggest
>
eserved(lock);
> if (l.owner != l.next)
> return 0;
> l.next++;
> success = __smp_store_release_conditional(lock, l.v32);
It's a new semantics v.s cmpxchg, and cmpxchg is come from CAS
instruction to solve some complex scenario.
The primitive of cmpxchg has been w
Acked-by: Guo Ren
It's a fallthrough is for BCACHE, but affects ICACHE with more
expensive. I'll fix up it later.
}
On Mon, Apr 12, 2021 at 12:41 AM Randy Dunlap wrote:
>
> This case of the switch statement falls through to the following case.
> This appears to be on pu
On Mon, Apr 12, 2021 at 12:02 AM Guo Ren wrote:
>
> On Wed, Mar 31, 2021 at 10:32 PM wrote:
> >
> > From: Guo Ren
> >
> > This patch introduces a ticket lock implementation for riscv, along the
> > same lines as the implementation for arch/arm & a
On Wed, Mar 31, 2021 at 10:32 PM wrote:
>
> From: Guo Ren
>
> This patch introduces a ticket lock implementation for riscv, along the
> same lines as the implementation for arch/arm & arch/csky.
>
> We still use qspinlock as default.
>
> Signed-off-by: Guo Ren
&
On Wed, Mar 31, 2021 at 10:32 PM wrote:
>
> From: Guo Ren
>
> - Using smp_cond_load_acquire in arch_spin_lock by Peter's
>advice.
> - Using __smp_acquire_fence in arch_spin_trylock
> - Using smp_store_release in arch_spin_unlock
>
> All above are just coding c
> wrapper around those (or alternatively we can decide to have them
> only deal with fixed-32-bit and long/pointer sized atomics).
I think these emulation codes are suitable for some architectures but not riscv.
We shouldn't export xchg16/cmpxchg16(emulated by lr.w/sc.w) in riscv,
We should forbi
dma-mapping.c b/arch/csky/mm/dma-mapping.c
> index c3a775a..8244702 100644
> --- a/arch/csky/mm/dma-mapping.c
> +++ b/arch/csky/mm/dma-mapping.c
> @@ -9,7 +9,6 @@
> #include
> #include
> #include
> -#include
> #include
>
> static inline void cache_op(phys_addr_t paddr, size_t size,
> --
> 1.8.3.1
>
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
On Tue, Mar 30, 2021 at 10:09 PM Waiman Long wrote:
>
> On 3/29/21 11:13 PM, Guo Ren wrote:
> > On Mon, Mar 29, 2021 at 8:50 PM Peter Zijlstra wrote:
> >> On Mon, Mar 29, 2021 at 08:01:41PM +0800, Guo Ren wrote:
> >>> u32 a = 0x55aa66bb;
&
On Wed, Mar 31, 2021 at 12:08 AM Peter Zijlstra wrote:
>
> On Tue, Mar 30, 2021 at 11:13:55AM +0800, Guo Ren wrote:
> > On Mon, Mar 29, 2021 at 8:50 PM Peter Zijlstra wrote:
> > >
> > > On Mon, Mar 29, 2021 at 08:01:41PM +0800, Guo Ren wrote:
> > >
Hi Paul,
Thx for the explanation, here is my comment.
On Wed, Mar 31, 2021 at 1:33 PM Paul Campbell wrote:
>
> On Wednesday, 31 March 2021 5:18:56 PM NZDT Guo Ren wrote:
> > > > [1]
> > > > https://github.com/c-sky/csky-linux/commit/e837aad231485427717
On Wed, Mar 31, 2021 at 10:32 PM wrote:
>
> From: Guo Ren
>
> This patch introduces a ticket lock implementation for riscv, along the
> same lines as the implementation for arch/arm & arch/csky.
>
> We still use qspinlock as default.
>
> Signed-off-by: Guo Ren
&
On Mon, Mar 29, 2021 at 8:50 PM Peter Zijlstra wrote:
>
> On Mon, Mar 29, 2021 at 08:01:41PM +0800, Guo Ren wrote:
> > u32 a = 0x55aa66bb;
> > u16 *ptr =
> >
> > CPU0 CPU1
> > = ==
;
> > The common code can then build cmpxchg16()/xchg16() on top of
> > either the 16-bit or the 32-bit primitives, and build the cmpxchg()/xchg()
> > wrapper around those (or alternatively we can decide to have them
> > only deal with fixed-32-bit and long/pointer sized atomics).
>
> Yeah, that was the idea.
>
> -Stafford
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
On Tue, Mar 30, 2021 at 10:09 PM Waiman Long wrote:
>
> On 3/29/21 11:13 PM, Guo Ren wrote:
> > On Mon, Mar 29, 2021 at 8:50 PM Peter Zijlstra wrote:
> >> On Mon, Mar 29, 2021 at 08:01:41PM +0800, Guo Ren wrote:
> >>> u32 a = 0x55aa66bb;
&
Hi Arnd
On Wed, Mar 31, 2021 at 12:18 PM Guo Ren wrote:
>
> On Tue, Mar 30, 2021 at 3:12 PM Arnd Bergmann wrote:
> >
> > On Tue, Mar 30, 2021 at 4:26 AM Guo Ren wrote:
> > > On Mon, Mar 29, 2021 at 9:56 PM Arnd Bergmann wrote:
> > > > On Mon,
On Tue, Mar 30, 2021 at 3:12 PM Arnd Bergmann wrote:
>
> On Tue, Mar 30, 2021 at 4:26 AM Guo Ren wrote:
> > On Mon, Mar 29, 2021 at 9:56 PM Arnd Bergmann wrote:
> > > On Mon, Mar 29, 2021 at 2:52 PM Guo Ren wrote:
> > > > On Mon, Mar 29, 2021 at 7:31
On Tue, Mar 30, 2021 at 12:54 PM Anup Patel wrote:
>
>
>
> > -Original Message-----
> > From: Guo Ren
> > Sent: 30 March 2021 08:44
> > To: Peter Zijlstra
> > Cc: linux-riscv ; Linux Kernel Mailing List
> > ; linux-c...@vger.kernel.org; linu
On Tue, Mar 30, 2021 at 1:51 PM Anup Patel wrote:
>
> On Tue, Mar 30, 2021 at 7:56 AM Guo Ren wrote:
> >
> > On Mon, Mar 29, 2021 at 9:56 PM Arnd Bergmann wrote:
> > >
> > > On Mon, Mar 29, 2021 at 2:52 PM Guo Ren wrote:
> > > >
> &
On Mon, Mar 29, 2021 at 8:50 PM Peter Zijlstra wrote:
>
> On Mon, Mar 29, 2021 at 08:01:41PM +0800, Guo Ren wrote:
> > u32 a = 0x55aa66bb;
> > u16 *ptr =
> >
> > CPU0 CPU1
> > = ==
On Mon, Mar 29, 2021 at 9:56 PM Arnd Bergmann wrote:
>
> On Mon, Mar 29, 2021 at 2:52 PM Guo Ren wrote:
> >
> > On Mon, Mar 29, 2021 at 7:31 PM Peter Zijlstra wrote:
> > >
> > > On Mon, Mar 29, 2021 at 01:16:53PM +0200, Peter Zijlstra wrote:
> > &
success or failure, executing an SC.W instruction
*invalidates any reservation held by this hart*.
More details, ref:
https://github.com/riscv/riscv-isa-manual
> And what if you double loop it like cmpxchg() ?
Can you give a code snippet?
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
On Mon, Mar 29, 2021 at 7:26 PM Peter Zijlstra wrote:
>
> On Mon, Mar 29, 2021 at 07:19:29PM +0800, Guo Ren wrote:
> > On Mon, Mar 29, 2021 at 3:50 PM Peter Zijlstra wrote:
> > >
> > > On Sat, Mar 27, 2021 at 06:06:38PM +, guo...@kernel.org wrote:
> > >
On Mon, Mar 29, 2021 at 3:50 PM Peter Zijlstra wrote:
>
> On Sat, Mar 27, 2021 at 06:06:38PM +, guo...@kernel.org wrote:
> > From: Guo Ren
> >
> > Some architectures don't have sub-word swap atomic instruction,
> > they only have the full word's one.
> >
On Sun, Mar 28, 2021 at 7:14 PM Christophe Leroy
wrote:
>
>
>
> Le 28/03/2021 à 08:30, guo...@kernel.org a écrit :
> > From: Guo Ren
> >
> > We don't have native hw xchg16 instruction, so let qspinlock
> > generic code to deal with it.
>
> We have lh
Thx Arnd,
On Sun, Mar 28, 2021 at 5:25 AM Arnd Bergmann wrote:
>
> On Sat, Mar 27, 2021 at 7:06 PM wrote:
> >
> > From: Guo Ren
> >
> > To reduce assembly codes, let's merge duplicate codes into one
> > (xchg_acquire, xchg_release, cmpxchg_rele
On Sun, Mar 28, 2021 at 2:43 AM Waiman Long wrote:
>
> On 3/27/21 2:06 PM, guo...@kernel.org wrote:
> > From: Guo Ren
> >
> > Some architectures don't have sub-word swap atomic instruction,
> > they only have the full word's one.
> >
> > The sub-w
%0, %0, 16 \n" \
- " srliw %0, %0, 16 \n" \
+ __ASM_SLLIW"%0, %0, 16 \n" \
+ __ASM_SRLIW"%0, %0, 16 \n" \
2018-04-26 195 {
> 59fb586b4a07b4 Will Deacon2018-04-26 196
> atomic_andnot(_Q_PENDING_VAL, >val);
> 59fb586b4a07b4 Will Deacon 2018-04-26 197 }
> 59fb586b4a07b4 Will Deacon2018-04-26 198
>
> ---
> 0-DAY CI Kernel Test Service, Intel Corporation
> https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
On Wed, Mar 24, 2021 at 7:16 PM Vitaly Wool wrote:
>
>
>
> On Wed, Mar 24, 2021, 11:16 AM wrote:
>>
>> From: Guo Ren
>>
>> This patch introduces a ticket lock implementation for riscv, along the
>> same lines as the implementation for arch/arm &
ock_t *lock)
> > {
> > + smp_store_release(>tickets.owner, lock->tickets.owner + 1);
> > + /* FIXME - we need ipi/sev here to notify above */
> > }
>
> Urgh, are you saying your WFE requires an explicit SEV like on ARM ? The
Yes, I'm considering that kind of code.
> ARM64 model is far superious IMO, and then you can use
> smp_cond_load_acquire() in arch_spin_lock() and call it a day.
Great tip, thx. I'll follow that.
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
suggests those low addresses would not
> - * otherwise be availiable.
> + * otherwise be available.
> */
> #define VDSO_SYMBOL(base, name)
> \
> ({
> \
> --
> 1.9.1
>
>
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
>
> diff --git a/arch/csky/kernel/entry.S b/arch/csky/kernel/entry.S
> index c1bd7a6b4ab6..00e3c8ebf9b8 100644
> --- a/arch/csky/kernel/entry.S
> +++ b/arch/csky/kernel/entry.S
> @@ -9,7 +9,6 @@
> #include
> #include
> #include
> -#include
> #include
> #in
otplug.h
+++ b/include/linux/cpuhotplug.h
@@ -134,7 +134,6 @@ enum cpuhp_state {
CPUHP_AP_ARC_TIMER_STARTING,
CPUHP_AP_RISCV_TIMER_STARTING,
CPUHP_AP_CLINT_TIMER_STARTING,
- CPUHP_AP_CSKY_TIMER_STARTING,
CPUHP_AP_HYPERV_TIMER_STARTING,
CPUHP_AP_KVM_STARTING,
CPUHP_AP_KVM_ARM_VGIC_INIT_STARTING,
@@ -186,7 +185,6 @@ enum cpuhp_state {
CPUHP_AP_PERF_POWERPC_TRACE_IMC_ONLINE,
CPUHP_AP_PERF_POWERPC_HV_24x7_ONLINE,
CPUHP_AP_PERF_POWERPC_HV_GPCI_ONLINE,
- CPUHP_AP_PERF_CSKY_ONLINE,
CPUHP_AP_WATCHDOG_ONLINE,
CPUHP_AP_WORKQUEUE_ONLINE,
CPUHP_AP_RCUTREE_ONLINE,
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
Thx Arnd,
I'm very glad to see C-SKY & RISC-V features updated.
Signed-off-by: Guo Ren
On Thu, Feb 25, 2021 at 10:29 PM Arnd Bergmann wrote:
>
> From: Arnd Bergmann
>
> Run the update script to document the recent feature additions
> on riscv, mips and csky.
>
> F
Hi Daniel,
On Wed, Feb 10, 2021 at 4:26 AM Daniel Lezcano
wrote:
>
> On 09/02/2021 17:02, Guo Ren wrote:
> > Hi Daniel,
> >
> > On Sun, Feb 7, 2021 at 5:29 PM Daniel Lezcano
> > wrote:
> >>
> >> On 07/02/2021 04:31, Guo Ren wrote:
> >&g
Hi Daniel,
On Sun, Feb 7, 2021 at 5:29 PM Daniel Lezcano wrote:
>
> On 07/02/2021 04:31, Guo Ren wrote:
> > Hi Daniel,
> >
> > On Thu, Feb 4, 2021 at 4:48 PM Daniel Lezcano
> > wrote:
> >>
> >> On 04/02/2021 08:46, guo...@kernel.org wrote:
>
q == 0)
> - return 0;
> + return false;
>
> handle_domain_irq(root_domain, irq_base + __fls(hwirq), regs);
>
> - return 1;
> + return true;
> }
>
> /* gx6605s 64 irqs interrupt controller */
> --
> 1.8.3.1
>
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
The same way in IRQ chip:
Link:
https://lore.kernel.org/lkml/161245410060.1472442.13488057609914274236.b4...@kernel.org/
On Sun, Feb 7, 2021 at 11:31 AM Guo Ren wrote:
>
> Hi Daniel,
>
> On Thu, Feb 4, 2021 at 4:48 PM Daniel Lezcano
> wrote:
> >
> > On 04/02/20
Hi Daniel,
On Thu, Feb 4, 2021 at 4:48 PM Daniel Lezcano wrote:
>
> On 04/02/2021 08:46, guo...@kernel.org wrote:
> > From: Guo Ren
> >
> > The timer-mp-csky.c only could support CPU_CK860 and it will
> > compile error with CPU_CK610.
> >
> >
The following commit has been merged into the irq/irqchip-next branch of
irqchip:
Commit-ID: be1abc5ba4d2082df6749ab95ec6f87c4d3dbb23
Gitweb:
https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/be1abc5ba4d2082df6749ab95ec6f87c4d3dbb23
Author:Guo Ren
AuthorDate
Thx Marc,
On Wed, Feb 3, 2021 at 11:44 PM Marc Zyngier wrote:
>
> On 2021-02-03 13:48, guo...@kernel.org wrote:
> > From: Guo Ren
> >
> > The irq-csky-mpintc.c only could support CPU_CK860 and it will
> > compile error with CPU_CK610.
> >
> > Si
ve the conflict.
> (although e1000 is also a 2-line change)
>
> Not tested: I don't have a build toolchain for CSKY.
>
> Signed-off-by: Randy Dunlap
> Reported-by: kernel test robot
> Cc: Jesse Brandeburg
> Cc: Tony Nguyen
> Cc: intel-wired-...@lists.osuosl.org
&
Hi David,
> 在 2021年1月27日，下午4:49，David Hildenbrand 写道：
>
> On 27.01.21 08:52, Guo Ren wrote:
>> Thx Mike,
>
> Thanks for triggering a build/test! I'd be curious if there is an easy way to
> trigger this myself (I assume, fork csky buildroot on gitlab, reroute CSK
nbrand wrote:
> > The existing code is essentially
> > free_initmem_default()->free_reserved_area() without poisoning.
> >
> > Note that existing code missed to update the managed page count of the
> > zone.
> >
> > Cc: Andrew Morton
> > Cc: Guo R
Acked-by: Guo Ren
On 2021/1/23 上午11:34, Palmer Dabbelt wrote:
From: Palmer Dabbelt
Neither of these are actually correct: the instruction stream is defined
(for versions of the ISA manual newer than 2.2) as a stream of 16-bit
little-endian parcels, which is different than just being little
Hi Peter,
On Thu, Jan 7, 2021 at 7:19 PM Peter Zijlstra wrote:
>
> On Sun, Dec 20, 2020 at 03:39:19PM +, guo...@kernel.org wrote:
> > From: Guo Ren
> >
> > Use generic atomic implementation based on cmpxchg. So remove csky
> > asm/atomic.h.
>
> Clarificat
struction.
arw means after read and write would happen after the instruction
So it also could be bar.brarw / bar.arw / bar.brw / bar.braw
sync means we need to wait until all instructions complete in the CPU
pipeline and then issue the next instructions.
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
On Tue, Jan 12, 2021 at 4:18 PM Atish Patra wrote:
>
> On Mon, Jan 11, 2021 at 6:38 PM wrote:
> >
> > From: Guo Ren
> >
> > PAGE_KERNEL_EXEC has been defined above.
> >
> > Signed-off-by: Guo Ren
> > Cc: Palmer Dabbelt
> > Cc: Pekka Enb
instruction_pointer_set(regs,
> addr + sign_extend32((opcode & 0x) >> 15,
> 15));
> } else
> --
> 2.17.1
>
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
odes could be
> > re-used directly.
> >
> > if HAVE_TCM
> >
>
> LGTM. Thanks.
> Reviewed-by: Randy Dunlap
>
> --
> ~Randy
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
Hi Zhengzhong,
I'll take it, thx.
On Wed, Dec 23, 2020 at 10:31 AM Zhenzhong Duan
wrote:
>
> On Wed, Sep 23, 2020 at 12:52 PM Al Viro wrote:
> >
> > On Wed, Sep 23, 2020 at 10:37:31AM +0800, Guo Ren wrote:
> >
> > > > What's going on there? The mapping is
Hi Arnd,
On Mon, Dec 21, 2020 at 1:49 AM Arnd Bergmann wrote:
>
> On Sun, Dec 20, 2020 at 4:46 PM Guo Ren wrote:
> > On Tue, Dec 15, 2020 at 7:26 PM Arnd Bergmann wrote:
> > >
> > > On Tue, Dec 15, 2020 at 7:09 AM Guo Ren wrote:
> > > > On Mon, De
Hi Arnd,
On Tue, Dec 15, 2020 at 7:26 PM Arnd Bergmann wrote:
>
> On Tue, Dec 15, 2020 at 7:09 AM Guo Ren wrote:
> > On Mon, Dec 14, 2020 at 9:15 PM Arnd Bergmann wrote:
> > > I had a look at what other architectures always implement
> > > futex_atomic_cmpxchg
inline int
+arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *uaddr)
+{
+ int oldval = 0, ret = 0;
+
+ if (!access_ok(uaddr, sizeof(u32)))
+ return -EFAULT;
+
+ <...>
+
+ return ret;
+}
+
+static inline int
+futex_atomic_cmpxchg_inatomic(u32 *uval, u32
ing in
> it over tickets for <= 16 CPUs.
NUMA is on the way:
https://lore.kernel.org/linux-riscv/20201119003829.1282810-1-atish.pa...@wdc.com/
With your advice, I think we could using tickets lock when <= 16 CPUs
and using qspinlock when > 16 CPUs.
Is that right?
The next patchset plan is:
- Using tickets & qspinlock together in riscv. Abandon 16bits
xchg/cmpxchg implementation.
- Abanden qspinlock in csky, because it only could 4 CPUs' SMP.
>
> Will
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
On Tue, Nov 24, 2020 at 10:29 PM Peter Zijlstra wrote:
>
> On Tue, Nov 24, 2020 at 01:43:53PM +, guo...@kernel.org wrote:
> > From: Guo Ren
> >
> > This is prepare for QUEUED_SPINLOCKS which need xchg support short
> > type value.
> > - Remove unu
* tail.
*/
old = atomic_cmpxchg_relaxed(>val, val, new);
if (old == val)
break;
val = old;
}
return old;
}
#endif /* _Q_PENDING_BITS == 8 */
>
> If nothing else needs xchg() on a 16-bit val
> case 4: \
> > __asm__ __volatile__ ( \
> > " amoswap.w %0, %2, %1\n" \
>
> I'm pretty sure there's a handfull of implementations like this out
> there... if only we could share.
Michael has sent qspinlock before, ref to Link below. He reused mips' code.
Link:
https://lore.kernel.org/linux-riscv/20190211043829.30096-1-michaeljcl...@mac.com/
Which short xchg implementation do you prefer (Mine or his)?
>
> Anyway, this too should be an independent patch.
Ok, I'll separate it into two patches,
1. implement short xchg
2. qspinlock enabled based on Michael's patch
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
__mips__
> > + #elif defined(__mips__ || __csky__)
> >
> > and then change the rest of the text to add csky when appropriate.
> > Am I correct?
>
> AFAICT, you are correct. I think the reason that csky is missing is
> that the architecture was added after this manual pages was added.
>
> Thanks,
>
> Michael
>
>
> --
> Michael Kerrisk
> Linux man-pages maintainer; http://www.kernel.org/doc/man-pages/
> Linux/UNIX System Programming Training: http://man7.org/training/
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
Hi Palmer,
Could you help move the patch into your next-tree with Kees' review added?
On Sat, Nov 14, 2020 at 6:57 AM Kees Cook wrote:
>
> On Sun, Oct 18, 2020 at 12:38:17PM +, guo...@kernel.org wrote:
> > From: Guo Ren
> >
> > This enables the use of per-task st
On Fri, Nov 6, 2020 at 9:02 AM Palmer Dabbelt wrote:
>
> On Sat, 17 Oct 2020 00:06:13 PDT (-0700), guo...@kernel.org wrote:
> > From: Guo Ren
> >
> > This patch enables "kprobe & kretprobe" to work with ftrace
> > interface. It utilized soft
On Fri, Nov 6, 2020 at 9:03 AM Palmer Dabbelt wrote:
>
> On Sat, 17 Oct 2020 00:06:09 PDT (-0700), guo...@kernel.org wrote:
> > From: Patrick Stählin
> >
> > Needed for kprobes support. Copied and adapted from arm64 code.
> >
> > Guo Ren fixup pt_regs type f
On Tue, Nov 3, 2020 at 11:33 PM Atish Patra wrote:
>
> On Sat, Oct 31, 2020 at 12:42 AM Guo Ren wrote:
> >
> > On Sat, Oct 31, 2020 at 8:28 AM Steven Rostedt wrote:
> > >
> > > On Fri, 30 Oct 2020 14:47:56 -0700
> > > Atish Patra wrote:
> > &
Sorry, the patch is deprecated. I’ll remove it
Best Regards
Guo Ren
> 在 2020年11月5日，上午4:22，Stephen Rothwell 写道：
>
> Hi all,
>
> Commit
>
> 6257c1904d00 ("drivers/net: Add dwmac-thead added.")
>
> is missing a Signed-off-by from its author.
>
> --
> Cheers,
> Stephen Rothwell
Hi Kees,
Ping? Any feedback?
On Sun, Oct 18, 2020 at 8:39 PM wrote:
>
> From: Guo Ren
>
> This enables the use of per-task stack canary values if GCC has
> support for emitting the stack canary reference relative to the
> value of tp, which holds the task struct pointer in
m ftrace. My patch just use
notrace flag setting on some functions.
@Atish How do think:
CFLAGS_REMOVE_cacheflush.o = $(CC_FLAGS_FTRACE)
CFLAGS_REMOVE_sbi.o = $(CC_FLAGS_FTRACE)
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
On Fri, Oct 30, 2020 at 2:46 AM Atish Patra wrote:
>
> On Thu, Oct 29, 2020 at 9:06 AM Guo Ren wrote:
> >
> > On Thu, Oct 29, 2020 at 10:34 AM Zong Li wrote:
> > >
> > > On Thu, Oct 29, 2020 at 8:23 AM Atish Patra wrote:
> > > >
> &
On Thu, Oct 29, 2020 at 10:34 AM Zong Li wrote:
>
> On Thu, Oct 29, 2020 at 8:23 AM Atish Patra wrote:
> >
> > On Wed, Oct 28, 2020 at 8:44 AM Guo Ren wrote:
> > >
> > > Hi Zong & Atish,
> > >
> > > In our 2 harts c910 chip, we fo
On Thu, Oct 29, 2020 at 8:23 AM Atish Patra wrote:
>
> On Wed, Oct 28, 2020 at 8:44 AM Guo Ren wrote:
> >
> > Hi Zong & Atish,
> >
> > In our 2 harts c910 chip, we found:
> >
> > echo function > /sys/kernel/debug/tracing/current_tracer
&g
__asm__ __volatile__ ("div %0, %0, zero" : "=r" (dummy));
With your patch, it's solved. For this patch, I'll give:
Tested by: Guo Ren
But that's not enough, we still need:
diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
index 226ccce..12b8808 100644
--- a
Hi Anup,
On Sun, Oct 25, 2020 at 5:18 PM Anup Patel wrote:
>
> On Sat, Oct 24, 2020 at 8:40 AM Guo Ren wrote:
> >
> > On Fri, Oct 23, 2020 at 8:31 PM Anup Patel wrote:
> > >
> > > On Fri, Oct 23, 2020 at 3:48 PM wrote:
> > > >
> >
On Fri, Oct 23, 2020 at 8:17 PM Anup Patel wrote:
>
> On Fri, Oct 23, 2020 at 3:48 PM wrote:
> >
> > From: Guo Ren
> >
> > If "echo 3 > /proc/irq/1/smp_affinity", we want irq 1 could be
> > broadcast to CPU0 & CPU1 and one of them w
On Fri, Oct 23, 2020 at 8:31 PM Anup Patel wrote:
>
> On Fri, Oct 23, 2020 at 3:48 PM wrote:
> >
> > From: Guo Ren
> >
> > ENABLE and CONTEXT registers contain M & S status for per-hart, so
> > ref to the specification the correct definition is double to
ken.
On Wed, Oct 21, 2020 at 4:41 AM Steven Rostedt wrote:
>
> On Tue, 20 Oct 2020 19:18:01 +0800
> Guo Ren wrote:
>
> > > What platform are you testing ? We are seeing a crash while enabling
> > > any of the tracers multiple times
> > > on Qemu/HiFive Unleashed
On Tue, Oct 20, 2020 at 2:54 AM Atish Patra wrote:
>
> On Sat, Oct 17, 2020 at 12:07 AM wrote:
> >
> > From: Guo Ren
> >
> > It will cause warning messages:
> > echo function_graph > /sys/kernel/debug/tracing/current_tracer
&g
On Mon, Oct 19, 2020 at 4:36 PM Masami Hiramatsu wrote:
>
> On Sat, 17 Oct 2020 07:06:17 +
> guo...@kernel.org wrote:
>
> > From: Guo Ren
> >
> > It will cause warning messages:
> > echo function_graph > /sys/kernel/debug/tracing/current_tracer
&g
Good Idea! I'll try :P
On Mon, Oct 19, 2020 at 4:36 PM Masami Hiramatsu wrote:
>
> On Sat, 17 Oct 2020 07:06:17 +
> guo...@kernel.org wrote:
>
> > From: Guo Ren
> >
> > It will cause warning messages:
> > echo function_graph > /sys/kernel/debug/t
On Thu, Oct 8, 2020 at 11:54 AM Palmer Dabbelt wrote:
>
> On Wed, 07 Oct 2020 08:08:33 PDT (-0700), guo...@kernel.org wrote:
> > From: Guo Ren
> >
> > v1 is commit: 6184358da0004c8fd940afda6c0a0fa4027dc911 which has
> > been reverted.
> >
> > When ena
On Thu, Oct 8, 2020 at 3:46 AM Atish Patra wrote:
>
> On Wed, Oct 7, 2020 at 8:09 AM wrote:
> >
> > From: Guo Ren
> >
> > v1 is commit: 6184358da0004c8fd940afda6c0a0fa4027dc911 which has
> > been reverted.
> >
> > When enable LOCKDEP, static_obj
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