registering mipi_dsi device, but indeed it can extendable
for RGB if any requirement trigger in future.
Signed-off-by: Jagan Teki
---
Changes for v6:
- use sleep delay value as per datasheet
- add panel_sleep_delay variable for panel specific delay
- use command sequnce display on and off instead panel
Feiyang FY07024DI26A30-D is 1024x600, 4-lane MIPI-DSI LCD panel.
Add panel driver for it.
Signed-off-by: Jagan Teki
---
Changes for v2:
- use simple structure for command init
- update proper comments on power, reset delay sequnce
- fix to use set_display_off in disable function
- move mode
Feiyang FY07024DI26A30-D is 1024x600, 4-lane MIPI-DSI LCD panel.
Add dt-bingings for it.
Signed-off-by: Jagan Teki
Reviewed-by: Rob Herring
---
Changes for v2:
- none
.../display/panel/feiyang,fy07024di26a30d.txt | 20 +++
1 file changed, 20 insertions(+)
create mode 100644
On Fri, Dec 14, 2018 at 1:25 AM Sean Paul wrote:
>
> On Fri, Dec 14, 2018 at 12:56:03AM +0530, Jagan Teki wrote:
> > On Thu, Dec 13, 2018 at 8:37 PM Sean Paul wrote:
> > >
> > > On Fri, Nov 16, 2018 at 10:09:15PM +0530, Jagan Teki wrote:
> > > > Feiyang
On Thu, Dec 13, 2018 at 8:37 PM Sean Paul wrote:
>
> On Fri, Nov 16, 2018 at 10:09:15PM +0530, Jagan Teki wrote:
> > Feiyang FY07024DI26A30-D is 1024x600, 4-lane MIPI-DSI LCD panel.
> >
> > Add panel driver for it.
> >
> > Signed-off-by:
Hi Maxime,
On Tue, Dec 11, 2018 at 10:30 PM Jagan Teki wrote:
>
> On Tue, Dec 11, 2018 at 10:19 PM Maxime Ripard
> wrote:
> >
> > On Mon, Dec 10, 2018 at 09:47:19PM +0530, Jagan Teki wrote:
> > > Video start delay can be computed by subtracting total vertical
On Tue, Dec 11, 2018 at 10:19 PM Maxime Ripard
wrote:
>
> On Mon, Dec 10, 2018 at 09:47:19PM +0530, Jagan Teki wrote:
> > Video start delay can be computed by subtracting total vertical
> > timing with front porch timing and with adding 1 delay line for TCON.
> >
>
On 11/12/18 10:02 PM, Maxime Ripard wrote:
On Mon, Dec 10, 2018 at 09:47:27PM +0530, Jagan Teki wrote:
Minimum PLL used for MIPI is 500MHz, as per manual, but
lowering the min rate by 300MHz can result proper working
nkms divider with the help of desired dclock rate from
panel driver
Techstar TS8550B MIPI DSI panel is 480x854, 2-lane MIPI DSI LCD panel
with inbuilt ST7701 chip.
The default regulator names in ST7701 chip is renamed in Techstar TS8550B
so, add specific binding names for them.
Signed-off-by: Jagan Teki
---
Changes for v5:
- found the chip from vendor, so added
registering mipi_dsi device, but indeed it can extendable
for RGB if any requirement trigger in future.
Signed-off-by: Jagan Teki
---
Changes for v5:
- found the chip from vendor, so added new panel driver
- here is v4: https://patchwork.kernel.org/patch/10680335/
MAINTAINERS
On Tue, Dec 11, 2018 at 9:14 PM Maxime Ripard wrote:
>
> On Mon, Dec 10, 2018 at 05:22:43PM +0530, Jagan Teki wrote:
> > The default CSI_SCLK seems unable to drive the sensor to capture
> > the image, so update it to working clock rate 300MHz for A64.
> >
>
The MIPI DSI controller on Allwinner A64 is similar to
Allwinner A31 without support of DSI mod clock(CLK_DSI_SCLK)
So, alter has_mod_clk bool via driver data for respective
SoC's compatible.
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 7 +++
1 file changed, 7
Mod clock is not mandatory for all Allwinner MIPI DSI
controllers, it is connected as CLK_DSI_SCLK for A31
and not available in A64.
So add has_mod_clk quirk and process the clk accordingly.
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 39
lcd_ht -panel->lcd_x - panel->lcd_hbp
=> (timmings->hor_front_porch + panel->lcd_hbp + panel->lcd_x)
- panel->lcd_x - panel->hbp
=> timmings->hor_front_porch
=> mode->hsync_start - mode->hdisplay
So, update the DRQ set bits accordingly.
Signed-o
ngs->hor_sync_time)
=> timmings->hor_back_porch
=> mode->htotal - mode->hsync_end
So, update the MIPI-DSI hbp value accordingly.
Tested on 2-lane, 4-lane DSI LCD panels.
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 2 +-
1 file changed, 1 insertion(+),
Most of the Allwinner MIPI DSI controllers are supply with
VCC-DSI pin. which need to supply for some of the boards to
trigger the power.
So, document the supply property so-that the required board
can eable it via device tree.
Signed-off-by: Jagan Teki
Reviewed-by: Rob Herring
The A64 has a MIPI-DSI block which is similar to A31
without mod clock.
So, add dsi node with A64 compatible, dphy node with
A31 compatible and finally connect dsi to tcon0 to
make proper DSI pipeline.
Signed-off-by: Jagan Teki
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 45
Some boards have VCC-DSI pin connected to voltage regulator which may
not be turned on by default.
Add support for such boards by adding voltage regulator handling code to
MIPI DSI driver.
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 14 ++
drivers/gpu/drm
;htotal - (mode->hsync_end - mode->hsync_start))
So, update the DSI hblk timing accordingly.
Tested on 2-lane, 4-lane MIPI-DSI LCD panels.
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/sun4
Short transfer write support for DCS and Generic transfer types
share similar way to process command sequence in DSI block so
add generic write 2 param transfer type macro so-that the panels
which are requesting similar transfer type may process properly.
Signed-off-by: Jagan Teki
---
drivers
The MIPI DSI controller on Allwinner A64 is similar to
Allwinner A31 without support of DSI mod clock.
Signed-off-by: Jagan Teki
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation
t;lcd_y
- panel->lcd_y - panel->lcd_vbp
=> timmings->ver_front_porch
So, update the start delay computation accordingly.
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
dif
t_porch - x)
* fmt - 16
=> (timmings->hor_total_time - x - timmings->hor_total_time +
timmings->hor_front_porch + x) * fmt - 16
=> timmings->hor_front_porch * fmt - 16
So, update the DSI hfp timing accordingly.
Tested on 2-lane, 4-lane MIPI-DSI LCD panels.
Signed-off-by: Ja
]/8-(4+4+2);
So, add 10 bytes packet overhead for DSI hblk.
Tested on 2-lane, 4-lane MIPI-DSI LCD panels.
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
b
Minimum PLL used for MIPI is 500MHz, as per manual, but
lowering the min rate by 300MHz can result proper working
nkms divider with the help of desired dclock rate from
panel driver.
Signed-off-by: Jagan Teki
Acked-by: Stephen Boyd
---
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 1 +
1 file
The MIPI DSI PHY HDMI controller on Allwinner A64 is similar
on the one on A31.
Add A64 compatible and append A31 compatible as fallback.
Signed-off-by: Jagan Teki
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt | 1 +
1 file changed, 1 insertion
*dsi_pixel_bits[format]/8)*vt-(4+dsi_hblk+2);
dsi_vblk = (lane-tmp%lane);
So, update the vblk timing calculation accordingly.
Tested on 2-lane, 4-lane MIPI-DSI LCD panels.
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 29 +++---
1 file changed, 22
es
- fixed checkpatch warnings/errors
[3] https://patchwork.kernel.org/cover/10680247/
[2] https://patchwork.kernel.org/patch/10657541/
[1] https://patchwork.kernel.org/patch/10657619/
Note: the respetive dts consumer for dsi will send once the panel
driver finalized or in burst mode patch seri
Some NKM PLLs doesn't work well when their output clock rate is set below
certain rate.
So, add support for minimal rate for relevant PLLs.
Signed-off-by: Jagan Teki
Acked-by: Stephen Boyd
---
drivers/clk/sunxi-ng/ccu_nkm.c | 5 +
drivers/clk/sunxi-ng/ccu_nkm.h | 1 +
2 files changed, 6
Hi Thierry and David,
On Fri, Nov 16, 2018 at 10:10 PM Jagan Teki wrote:
>
> Feiyang FY07024DI26A30-D is 1024x600, 4-lane MIPI-DSI LCD panel.
>
> Add panel driver for it.
>
> Signed-off-by: Jagan Teki
> ---
> MAINTAINERS | 6 +
On Fri, Dec 7, 2018 at 6:51 PM Maxime Ripard wrote:
>
> On Tue, Nov 27, 2018 at 04:34:35PM +0530, Jagan Teki wrote:
> > On Tue, Nov 27, 2018 at 3:55 PM Maxime Ripard
> > wrote:
> > >
> > > On Tue, Nov 20, 2018 at 09:55:42PM +0530, Jagan Teki wrote:
> >
Allwinner A64 CSI has single channel time-multiplexed BT.656
CMOS sensor interface like H3 but work by lowering clock than
default mod clock.
Add a compatible string for it.
Signed-off-by: Jagan Teki
---
Documentation/devicetree/bindings/media/sun6i-csi.txt | 1 +
1 file changed, 1 insertion
-by: Jagan Teki
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 89a0deb3fe6a..dd5740bc3fc9 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64
Allwinner A64 CSI has single channel time-multiplexed BT.656
CMOS sensor interface like H3 but work by lowering clock than
default mod clock.
So use separate compatibe to support it.
Signed-off-by: Jagan Teki
---
drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c | 1 +
1 file changed, 1
- remove i2c-gpio opendrian
- fix avdd and dovdd supplies
- remove vcc-csi pin group supply
Note: This series created on top of H3 changes [1]
[1] https://patchwork.kernel.org/cover/10705905/
Any inputs,
Jagan.
Jagan Teki (6):
dt-bindings: media: sun6i: Add A64 CSI compatible
media: sun6i: Add
Allwinner A64 CSI controller has similar features as like in
H3, but work by lowering clock than default mod clock.
Signed-off-by: Jagan Teki
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 20 +++
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner
The default CSI_SCLK seems unable to drive the sensor to capture
the image, so update it to working clock rate 300MHz for A64.
Signed-off-by: Jagan Teki
---
drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/media/platform/sunxi
for reset pin
- PE15 gpio for powerdown pin
Signed-off-by: Jagan Teki
---
.../allwinner/sun50i-a64-amarula-relic.dts| 53 +++
1 file changed, 53 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts
b/arch/arm64/boot/dts/allwinner/sun50i-a64
On Fri, Dec 7, 2018 at 1:17 PM Maxime Ripard wrote:
>
> On Thu, Dec 06, 2018 at 06:07:59PM +0100, Michael Nazzareno Trimarchi wrote:
> > On Thu, Dec 6, 2018 at 4:34 PM Maxime Ripard
> > wrote:
> > > On Thu, Dec 06, 2018 at 06:53:05PM +0530, Jagan Teki wrote:
> >
On Fri, Dec 7, 2018 at 1:17 PM Maxime Ripard wrote:
>
> On Thu, Dec 06, 2018 at 06:07:59PM +0100, Michael Nazzareno Trimarchi wrote:
> > On Thu, Dec 6, 2018 at 4:34 PM Maxime Ripard
> > wrote:
> > > On Thu, Dec 06, 2018 at 06:53:05PM +0530, Jagan Teki wrote:
> >
885 seems
not possible, If I'm not mistaken.
I tried to look for similar design in mainline, but I couldn't find
it. is there any design similar to this in mainline?
Please let us know if anyone has any suggestions on this.
Jagan.
--
Jagan Teki
Senior Linux Kernel Engineer | Amarula Solutions
U-Bo
On Thu, Dec 6, 2018 at 9:05 PM Maxime Ripard wrote:
>
> On Thu, Dec 06, 2018 at 06:53:06PM +0530, Jagan Teki wrote:
> > Some camera modules have the SoC feeding a master clock to the sensor
> > instead of having a standalone crystal. This clock signal is generated
> > fro
On Thu, Dec 6, 2018 at 9:05 PM Maxime Ripard wrote:
>
> On Thu, Dec 06, 2018 at 06:53:06PM +0530, Jagan Teki wrote:
> > Some camera modules have the SoC feeding a master clock to the sensor
> > instead of having a standalone crystal. This clock signal is generated
> > fro
-by: Jagan Teki
---
Changes for v2:
- new patch
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index d7ab0006ebce..902b5238f1dd 100644
--- a/arch/arm64
Allwinner A64 CSI has single channel time-multiplexed BT.656
CMOS sensor interface like H3.
Add a compatible string for it with H3 fallback compatible string,
in this case the H3 driver can be used.
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
Documentation/devicetree/bindings/media
-by: Jagan Teki
---
Changes for v2:
- new patch
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index d7ab0006ebce..902b5238f1dd 100644
--- a/arch/arm64
Allwinner A64 CSI has single channel time-multiplexed BT.656
CMOS sensor interface like H3.
Add a compatible string for it with H3 fallback compatible string,
in this case the H3 driver can be used.
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
Documentation/devicetree/bindings/media
Allwinner A64 CSI controller has similar features as like in
H3, So add support for A64 via H3 fallback.
Also updated CSI_SCLK to use 300MHz via assigned-clocks, since
the default clock 600MHz seems unable to drive the sensor(ov5640)
to capture the image.
Signed-off-by: Jagan Teki
---
Changes
Allwinner A64 CSI controller has similar features as like in
H3, So add support for A64 via H3 fallback.
Also updated CSI_SCLK to use 300MHz via assigned-clocks, since
the default clock 600MHz seems unable to drive the sensor(ov5640)
to capture the image.
Signed-off-by: Jagan Teki
---
Changes
On Thu, Dec 6, 2018 at 5:22 AM Jagan Teki wrote:
>
> Goodix CTP controllers have AVDD28 pin connected to voltage
> regulator which may not be turned on by default, like for GT5663.
>
> Add support for such ctp used boards by adding voltage regulator
> handling code to goodix ctp
On Thu, Dec 6, 2018 at 5:22 AM Jagan Teki wrote:
>
> Goodix CTP controllers have AVDD28 pin connected to voltage
> regulator which may not be turned on by default, like for GT5663.
>
> Add support for such ctp used boards by adding voltage regulator
> handling code to goodix ctp
GT5663 is capacitive touch controller with customized smart
wakeup gestures, it support chipdata which is similar to
existing GT1151 and require AVDD28 supply for some boards.
Document the compatible for the same.
Signed-off-by: Jagan Teki
---
Changes for v2:
- drop example node
GT5663 is capacitive touch controller with customized smart
wakeup gestures, it support chipdata which is similar to
existing GT1151 and require AVDD28 supply for some boards.
Document the compatible for the same.
Signed-off-by: Jagan Teki
---
Changes for v2:
- drop example node
Most of the Goodix CTP controllers are supply with AVDD28 pin.
which need to supply for controllers like GT5663 on some boards
to trigger the power.
So, document the supply property so-that the required board
that used on GT5663 can enable it via device tree.
Signed-off-by: Jagan Teki
Most of the Goodix CTP controllers are supply with AVDD28 pin.
which need to supply for controllers like GT5663 on some boards
to trigger the power.
So, document the supply property so-that the required board
that used on GT5663 can enable it via device tree.
Signed-off-by: Jagan Teki
Goodix CTP controllers have AVDD28 pin connected to voltage
regulator which may not be turned on by default, like for GT5663.
Add support for such ctp used boards by adding voltage regulator
handling code to goodix ctp driver.
Signed-off-by: Jagan Teki
---
Changes for v2:
- disable regulator
has 16-bit
Signed-off-by: Jagan Teki
---
Changes for v2:
- add chipdata
drivers/input/touchscreen/goodix.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/input/touchscreen/goodix.c
b/drivers/input/touchscreen/goodix.c
index 7371f6946098..735ab8e246b6 100644
--- a/drivers/input
Goodix CTP controllers have AVDD28 pin connected to voltage
regulator which may not be turned on by default, like for GT5663.
Add support for such ctp used boards by adding voltage regulator
handling code to goodix ctp driver.
Signed-off-by: Jagan Teki
---
Changes for v2:
- disable regulator
has 16-bit
Signed-off-by: Jagan Teki
---
Changes for v2:
- add chipdata
drivers/input/touchscreen/goodix.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/input/touchscreen/goodix.c
b/drivers/input/touchscreen/goodix.c
index 7371f6946098..735ab8e246b6 100644
--- a/drivers/input
On Mon, Dec 3, 2018 at 3:44 PM Chen-Yu Tsai wrote:
>
> On Mon, Dec 3, 2018 at 6:07 PM Jagan Teki wrote:
> >
> > This series support CSI on Allwinner A64.
> >
> > The CSI controller seems similar to that of in H3, so fallback
> > compatible is used to load th
On Mon, Dec 3, 2018 at 3:44 PM Chen-Yu Tsai wrote:
>
> On Mon, Dec 3, 2018 at 6:07 PM Jagan Teki wrote:
> >
> > This series support CSI on Allwinner A64.
> >
> > The CSI controller seems similar to that of in H3, so fallback
> > compatible is used to load th
GPIO0, GPIO1 can be used as LDO like ldo_io0, ldo_io1 in
AXP803.
So, attach the LDO GPIO pins along with pinctrl properties.
Signed-off-by: Jagan Teki
---
arch/arm64/boot/dts/allwinner/axp803.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner
GT5663 is capacitive touch controller with customized smart wakeup gestures,
the existing goodix driver will work by phandle vcc-supply regulator.
So, document compatible and example node for the same.
Signed-off-by: Jagan Teki
---
.../bindings/input/touchscreen/goodix.txt | 13
GPIO0, GPIO1 can be used as LDO like ldo_io0, ldo_io1 in
AXP803.
So, attach the LDO GPIO pins along with pinctrl properties.
Signed-off-by: Jagan Teki
---
arch/arm64/boot/dts/allwinner/axp803.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner
GT5663 is capacitive touch controller with customized smart wakeup gestures,
the existing goodix driver will work by phandle vcc-supply regulator.
So, document compatible and example node for the same.
Signed-off-by: Jagan Teki
---
.../bindings/input/touchscreen/goodix.txt | 13
Allwinner A64 CSI has single channel time-multiplexed BT.656
CMOS sensor interface like H3.
Add a compatible string for it with H3 fallback compatible string,
in this case the H3 driver can be used.
Signed-off-by: Jagan Teki
---
Documentation/devicetree/bindings/media/sun6i-csi.txt | 1 +
1
convention
wrt other controller pin supplies.
Signed-off-by: Jagan Teki
---
Documentation/devicetree/bindings/media/sun6i-csi.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/sun6i-csi.txt
b/Documentation/devicetree/bindings/media/sun6i-csi.txt
index
Allwinner A64 CSI has single channel time-multiplexed BT.656
CMOS sensor interface like H3.
Add a compatible string for it with H3 fallback compatible string,
in this case the H3 driver can be used.
Signed-off-by: Jagan Teki
---
Documentation/devicetree/bindings/media/sun6i-csi.txt | 1 +
1
convention
wrt other controller pin supplies.
Signed-off-by: Jagan Teki
---
Documentation/devicetree/bindings/media/sun6i-csi.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/sun6i-csi.txt
b/Documentation/devicetree/bindings/media/sun6i-csi.txt
index
as DVDD supply
- PE14 gpio for reset pin
- PE15 gpio for powerdown pin
Signed-off-by: Jagan Teki
---
.../allwinner/sun50i-a64-amarula-relic.dts| 54 +++
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 5 ++
2 files changed, 59 insertions(+)
diff --git a/arch/arm64/boot/dts
supplies.
Signed-off-by: Jagan Teki
---
.../media/platform/sunxi/sun6i-csi/sun6i_csi.c| 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
index 6950585edb5a..5836fa5e6b01 100644
as DVDD supply
- PE14 gpio for reset pin
- PE15 gpio for powerdown pin
Signed-off-by: Jagan Teki
---
.../allwinner/sun50i-a64-amarula-relic.dts| 54 +++
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 5 ++
2 files changed, 59 insertions(+)
diff --git a/arch/arm64/boot/dts
supplies.
Signed-off-by: Jagan Teki
---
.../media/platform/sunxi/sun6i-csi/sun6i_csi.c| 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
index 6950585edb5a..5836fa5e6b01 100644
On Fri, Nov 30, 2018 at 1:29 PM Chen-Yu Tsai wrote:
>
> The Bananapi M2+ comes with an optional sensor based on the ov5640 from
> Omnivision. Enable the support for it in the DT.
>
> Signed-off-by: Chen-Yu Tsai
> ---
> arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi | 87 +++
> 1
On Fri, Nov 30, 2018 at 1:29 PM Chen-Yu Tsai wrote:
>
> The Bananapi M2+ comes with an optional sensor based on the ov5640 from
> Omnivision. Enable the support for it in the DT.
>
> Signed-off-by: Chen-Yu Tsai
> ---
> arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi | 87 +++
> 1
> "fallback" to a compatible that implements more features than it
> supports.
>
> Drop the A31 fallback compatible.
>
> Fixes: f89120b6f554 ("ARM: dts: sun8i: Add the H3/H5 CSI controller")
> Signed-off-by: Chen-Yu Tsai
> ---
Reviewed-by: Jagan Teki
> "fallback" to a compatible that implements more features than it
> supports.
>
> Drop the A31 fallback compatible.
>
> Fixes: f89120b6f554 ("ARM: dts: sun8i: Add the H3/H5 CSI controller")
> Signed-off-by: Chen-Yu Tsai
> ---
Reviewed-by: Jagan Teki
> "fallback" to a compatible that implements more features than it
> supports.
>
> Add a compatible string entry for the H3.
>
> Signed-off-by: Chen-Yu Tsai
> ---
Reviewed-by: Jagan Teki
> "fallback" to a compatible that implements more features than it
> supports.
>
> Add a compatible string entry for the H3.
>
> Signed-off-by: Chen-Yu Tsai
> ---
Reviewed-by: Jagan Teki
On Tue, Oct 30, 2018 at 1:49 PM Yong Deng wrote:
>
> Allwinner V3s SoC features a CSI module with parallel interface.
>
> This patch implement a v4l2 framework driver for it.
>
> Reviewed-by: Hans Verkuil
> Reviewed-by: Maxime Ripard
> Tested-by: Maxime Ripard
> Signed-off-by: Yong Deng
> ---
On Tue, Oct 30, 2018 at 1:49 PM Yong Deng wrote:
>
> Allwinner V3s SoC features a CSI module with parallel interface.
>
> This patch implement a v4l2 framework driver for it.
>
> Reviewed-by: Hans Verkuil
> Reviewed-by: Maxime Ripard
> Tested-by: Maxime Ripard
> Signed-off-by: Yong Deng
> ---
On Mon, Nov 19, 2018 at 2:08 PM Maxime Ripard wrote:
>
> On Fri, Nov 16, 2018 at 10:09:10PM +0530, Jagan Teki wrote:
> > Probe tcon0 during dsi_bind, so-that the tcon attributes like
> > divider value, clock rate can get whenever it need.
> >
> > Signed-off-by: Ja
On Mon, Nov 19, 2018 at 2:08 PM Maxime Ripard wrote:
>
> On Fri, Nov 16, 2018 at 10:09:10PM +0530, Jagan Teki wrote:
> > Probe tcon0 during dsi_bind, so-that the tcon attributes like
> > divider value, clock rate can get whenever it need.
> >
> > Signed-off-by: Ja
On Mon, Nov 19, 2018 at 2:02 PM Maxime Ripard wrote:
>
> On Fri, Nov 16, 2018 at 10:09:08PM +0530, Jagan Teki wrote:
> > Allwinner MIPI DSI DRQ set value can be varied with respective
> > video modes.
> > - burst mode the set value is always 0
> > - video modes who
On Mon, Nov 19, 2018 at 2:02 PM Maxime Ripard wrote:
>
> On Fri, Nov 16, 2018 at 10:09:08PM +0530, Jagan Teki wrote:
> > Allwinner MIPI DSI DRQ set value can be varied with respective
> > video modes.
> > - burst mode the set value is always 0
> > - video modes who
On Mon, Nov 19, 2018 at 2:00 PM Maxime Ripard wrote:
>
> On Fri, Nov 16, 2018 at 10:09:07PM +0530, Jagan Teki wrote:
> > Burst mode display timings are different from convectional
> > video mode so update the horizontal and vertical timings.
> >
> > Reference code ta
On Mon, Nov 19, 2018 at 2:00 PM Maxime Ripard wrote:
>
> On Fri, Nov 16, 2018 at 10:09:07PM +0530, Jagan Teki wrote:
> > Burst mode display timings are different from convectional
> > video mode so update the horizontal and vertical timings.
> >
> > Reference code ta
On Mon, Nov 19, 2018 at 1:57 PM Maxime Ripard wrote:
>
> On Fri, Nov 16, 2018 at 10:09:05PM +0530, Jagan Teki wrote:
> > Loop N1 instruction delay for burst mode lcd panel are
> > computed as per BSP code.
> >
> > Reference code is available in BSP (from linux-sunxi
On Mon, Nov 19, 2018 at 1:57 PM Maxime Ripard wrote:
>
> On Fri, Nov 16, 2018 at 10:09:05PM +0530, Jagan Teki wrote:
> > Loop N1 instruction delay for burst mode lcd panel are
> > computed as per BSP code.
> >
> > Reference code is available in BSP (from linux-sunxi
for backlight enable pin
Signed-off-by: Jagan Teki
---
.../dts/allwinner/sun50i-a64-pine64-lts.dts | 37 +++
1 file changed, 37 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-lts.dts
b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-lts.dts
index 72d6961dc312
for backlight enable pin
Signed-off-by: Jagan Teki
---
.../dts/allwinner/sun50i-a64-pine64-lts.dts | 37 +++
1 file changed, 37 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-lts.dts
b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-lts.dts
index 72d6961dc312
me in SUN6I_DSI_BASIC_SIZE0_VBP
On the information note, existing SUN6I_DSI_BASIC_SIZE0_VSA is proper
value.
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
b/drivers/gpu/
lcd_ht -panel->lcd_x - panel->lcd_hbp
=> (timmings->hor_front_porch + panel->lcd_hbp + panel->lcd_x)
- panel->lcd_x - panel->hbp
=> timmings->hor_front_porch
=> mode->hsync_start - mode->hdisplay
So, update the DRQ set bits accordingly.
Signed-o
me in SUN6I_DSI_BASIC_SIZE0_VBP
On the information note, existing SUN6I_DSI_BASIC_SIZE0_VSA is proper
value.
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
b/drivers/gpu/
lcd_ht -panel->lcd_x - panel->lcd_hbp
=> (timmings->hor_front_porch + panel->lcd_hbp + panel->lcd_x)
- panel->lcd_x - panel->hbp
=> timmings->hor_front_porch
=> mode->hsync_start - mode->hdisplay
So, update the DRQ set bits accordingly.
Signed-o
DSI DPHY gate bit on MIPI DSI clock register is bit 15
not bit 30.
Signed-off-by: Jagan Teki
Acked-by: Stephen Boyd
---
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
b/drivers/clk/sunxi-ng/ccu
DSI DPHY gate bit on MIPI DSI clock register is bit 15
not bit 30.
Signed-off-by: Jagan Teki
Acked-by: Stephen Boyd
---
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
b/drivers/clk/sunxi-ng/ccu
On Wed, Oct 31, 2018 at 2:45 PM Andrzej Hajda wrote:
>
> On 31.10.2018 09:58, Chen-Yu Tsai wrote:
> > On Wed, Oct 31, 2018 at 4:53 PM Andrzej Hajda wrote:
> >> On 26.10.2018 16:43, Jagan Teki wrote:
> >>> Bananapi S070WV20-CT16 ICN6211 is 800x480, 4-lane MIPI-DSI
On Wed, Oct 31, 2018 at 2:45 PM Andrzej Hajda wrote:
>
> On 31.10.2018 09:58, Chen-Yu Tsai wrote:
> > On Wed, Oct 31, 2018 at 4:53 PM Andrzej Hajda wrote:
> >> On 26.10.2018 16:43, Jagan Teki wrote:
> >>> Bananapi S070WV20-CT16 ICN6211 is 800x480, 4-lane MIPI-DSI
From: Jagan Teki
OrangePi Lite2 is Allwinner H6 based open-source SBC,
which support:
- Allwinner H6 Quad-core 64-bit ARM Cortex-A53
- GPU Mali-T720
- 1GB LPDDR3 RAM
- AXP805 PMIC
- AP6356S Wifi/BT
- USB 2.0, USB 3.0 Host, OTG
- HDMI port
- 5V/2A DC power supply
Signed-off-by: Jagan Teki
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