Re: [1/2] dt-bindings: phy: Add stingray usb phy documentation

Hi Srinath, Ray, On Fri, Jul 07, 2017 at 06:37:04PM +0530, Srinath Mannam wrote: > Add DT binding document for stingray usb phy driver. > > Signed-off-by: Srinath Mannam > Reviewed-by: Ray Jui > Acked-by: Rob Herring The Broadcom Vulcan chip (now Cavium ThunderX2) uses the same USB PHY from

Re: [1/2] dt-bindings: phy: Add stingray usb phy documentation

Hi Srinath, Ray, On Fri, Jul 07, 2017 at 06:37:04PM +0530, Srinath Mannam wrote: > Add DT binding document for stingray usb phy driver. > > Signed-off-by: Srinath Mannam > Reviewed-by: Ray Jui > Acked-by: Rob Herring The Broadcom Vulcan chip (now Cavium ThunderX2) uses the same USB PHY from

Re: [v2] cpufreq / CPPC: Add cpuinfo_cur_freq support for CPPC

Hi George, Few comments on your patch: On Fri, Jun 15, 2018 at 03:03:15AM -0700, George Cherian wrote: > Per Section 8.4.7.1.3 of ACPI 6.2, The platform provides performance > feedback via set of performance counters. To determine the actual > performance level delivered over time, OSPM may read

Re: [v2] cpufreq / CPPC: Add cpuinfo_cur_freq support for CPPC

Hi George, Few comments on your patch: On Fri, Jun 15, 2018 at 03:03:15AM -0700, George Cherian wrote: > Per Section 8.4.7.1.3 of ACPI 6.2, The platform provides performance > feedback via set of performance counters. To determine the actual > performance level delivered over time, OSPM may read

[PATCH] watchdog: sbsa: use 32-bit read for WCV

readq to read the watchdog compare register which does a 64-bit access. This fails on ThunderX2 which does not implement 64-bit access to this register. Fix this by using lo_hi_readq() that does two 32-bit reads. Signed-off-by: Jayachandran C <jn...@caviumnetworks.com> --- drivers/wa

[PATCH] watchdog: sbsa: use 32-bit read for WCV

readq to read the watchdog compare register which does a 64-bit access. This fails on ThunderX2 which does not implement 64-bit access to this register. Fix this by using lo_hi_readq() that does two 32-bit reads. Signed-off-by: Jayachandran C --- drivers/watchdog/sbsa_gwdt.c | 3 ++- 1 file

Re: [PATCH v2] irqchip/gic-v3-its: Add workaround for ThunderX2 erratum #174

On Sun, Jan 21, 2018 at 11:35:34AM +, Marc Zyngier wrote: > On Sun, 21 Jan 2018 07:00:48 +, > Jayachandran C wrote: > > > > On Thu, Jan 18, 2018 at 10:58:20AM +0530, Ganapatrao Kulkarni wrote: > > > This erratum is observed on the ThunderX2 GICv3 ITS. When a

Re: [PATCH v2] irqchip/gic-v3-its: Add workaround for ThunderX2 erratum #174

On Sun, Jan 21, 2018 at 11:35:34AM +, Marc Zyngier wrote: > On Sun, 21 Jan 2018 07:00:48 +, > Jayachandran C wrote: > > > > On Thu, Jan 18, 2018 at 10:58:20AM +0530, Ganapatrao Kulkarni wrote: > > > This erratum is observed on the ThunderX2 GICv3 ITS. When a

Re: [PATCH] PCI: Add quirk for Cavium Thunder-X2 PCIe erratum #173

D3 > + */ This comment can be fixed up a bit. > + > +static void quirk_no_rootport_d3(struct pci_dev *pdev) > +{ > + pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; > +} > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 0x9084, > quirk_no_rootport_d3); > +DEC

Re: [PATCH] PCI: Add quirk for Cavium Thunder-X2 PCIe erratum #173

be fixed up a bit. > + > +static void quirk_no_rootport_d3(struct pci_dev *pdev) > +{ > + pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; > +} > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 0x9084, > quirk_no_rootport_d3); > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_C

Re: [PATCH v2] irqchip/gic-v3-its: Add workaround for ThunderX2 erratum #174

On Thu, Jan 18, 2018 at 10:58:20AM +0530, Ganapatrao Kulkarni wrote: > This erratum is observed on the ThunderX2 GICv3 ITS. When a > MOVI command is used to change affinity of a LPI to a collection/cpu > on another node, the LPI is not delivered to the cpu. > An additional INV command is required

Re: [PATCH v2] irqchip/gic-v3-its: Add workaround for ThunderX2 erratum #174

On Thu, Jan 18, 2018 at 10:58:20AM +0530, Ganapatrao Kulkarni wrote: > This erratum is observed on the ThunderX2 GICv3 ITS. When a > MOVI command is used to change affinity of a LPI to a collection/cpu > on another node, the LPI is not delivered to the cpu. > An additional INV command is required

[PATCH v3 2/2] arm64: Turn on KPTI only on CPUs that need it

Whitelist Broadcom Vulcan/Cavium ThunderX2 processors in unmap_kernel_at_el0(). These CPUs are not vulnerable to CVE-2017-5754 and do not need KPTI when KASLR is off. Signed-off-by: Jayachandran C <jn...@caviumnetworks.com> --- arch/arm64/kernel/cpufeature.c | 7 +++ 1 file chan

[PATCH v3 2/2] arm64: Turn on KPTI only on CPUs that need it

Whitelist Broadcom Vulcan/Cavium ThunderX2 processors in unmap_kernel_at_el0(). These CPUs are not vulnerable to CVE-2017-5754 and do not need KPTI when KASLR is off. Signed-off-by: Jayachandran C --- arch/arm64/kernel/cpufeature.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/arch

[PATCH v3 1/2] arm64: Branch predictor hardening for Cavium ThunderX2

Use PSCI based mitigation for speculative execution attacks targeting the branch predictor. We use the same mechanism as the one used for Cortex-A CPUs, we expect the PSCI version call to have a side effect of clearing the BTBs. Signed-off-by: Jayachandran C <jn...@caviumnetworks.com> ---

[PATCH v3 1/2] arm64: Branch predictor hardening for Cavium ThunderX2

Use PSCI based mitigation for speculative execution attacks targeting the branch predictor. We use the same mechanism as the one used for Cortex-A CPUs, we expect the PSCI version call to have a side effect of clearing the BTBs. Signed-off-by: Jayachandran C --- arch/arm64/kernel/cpu_errata.c

Re: [PATCH v2] arm64: Branch predictor hardening for Cavium ThunderX2

Hi Jon, On Thu, Jan 18, 2018 at 01:27:15PM -0500, Jon Masters wrote: > On 01/18/2018 12:56 PM, Jayachandran C wrote: > > On Thu, Jan 18, 2018 at 01:53:55PM +, Will Deacon wrote: > >> Hi JC, > >> > >> On Tue, Jan 16, 2018 at 03:45:54PM -0800, Jayachandran

Re: [PATCH v2] arm64: Branch predictor hardening for Cavium ThunderX2

Hi Jon, On Thu, Jan 18, 2018 at 01:27:15PM -0500, Jon Masters wrote: > On 01/18/2018 12:56 PM, Jayachandran C wrote: > > On Thu, Jan 18, 2018 at 01:53:55PM +, Will Deacon wrote: > >> Hi JC, > >> > >> On Tue, Jan 16, 2018 at 03:45:54PM -0800, Jayachandran

Re: [PATCH v2] arm64: Branch predictor hardening for Cavium ThunderX2

On Thu, Jan 18, 2018 at 01:53:55PM +, Will Deacon wrote: > Hi JC, > > On Tue, Jan 16, 2018 at 03:45:54PM -0800, Jayachandran C wrote: > > On Tue, Jan 16, 2018 at 04:52:53PM -0500, Jon Masters wrote: > > > On 01/09/2018 07:47 AM, Jayachandran C wrote: > > >

Re: [PATCH v2] arm64: Branch predictor hardening for Cavium ThunderX2

On Thu, Jan 18, 2018 at 01:53:55PM +, Will Deacon wrote: > Hi JC, > > On Tue, Jan 16, 2018 at 03:45:54PM -0800, Jayachandran C wrote: > > On Tue, Jan 16, 2018 at 04:52:53PM -0500, Jon Masters wrote: > > > On 01/09/2018 07:47 AM, Jayachandran C wrote: > > >

Re: [PATCH v2] arm64: Branch predictor hardening for Cavium ThunderX2

On Tue, Jan 16, 2018 at 04:52:53PM -0500, Jon Masters wrote: > On 01/09/2018 07:47 AM, Jayachandran C wrote: > > > Use PSCI based mitigation for speculative execution attacks targeting > > the branch predictor. The approach is similar to the one used for > > Co

Re: [PATCH v2] arm64: Branch predictor hardening for Cavium ThunderX2

On Tue, Jan 16, 2018 at 04:52:53PM -0500, Jon Masters wrote: > On 01/09/2018 07:47 AM, Jayachandran C wrote: > > > Use PSCI based mitigation for speculative execution attacks targeting > > the branch predictor. The approach is similar to the one used for > > Co

[PATCH v2] arm64: Branch predictor hardening for Cavium ThunderX2

with the mitigation code to invalidate the branch target buffer, we use the PSCI version call to invoke it. Signed-off-by: Jayachandran C <jn...@caviumnetworks.com> --- v2: - rebased on top of the latest kpti branch - use pr_info_once/pr_warn_once to avoid excessive prints - using .desc generat

[PATCH v2] arm64: Branch predictor hardening for Cavium ThunderX2

with the mitigation code to invalidate the branch target buffer, we use the PSCI version call to invoke it. Signed-off-by: Jayachandran C --- v2: - rebased on top of the latest kpti branch - use pr_info_once/pr_warn_once to avoid excessive prints - using .desc generated too many prints, dropped plan

Re: [v2,03/11] arm64: Take into account ID_AA64PFR0_EL1.CSV3

On Mon, Jan 08, 2018 at 05:51:00PM +, Will Deacon wrote: > On Mon, Jan 08, 2018 at 09:40:17AM -0800, Jayachandran C wrote: > > On Mon, Jan 08, 2018 at 09:20:09AM +, Marc Zyngier wrote: > > > On 08/01/18 07:24, Jayachandran C wrote: > > > > diff --git a/

Re: [v2,03/11] arm64: Take into account ID_AA64PFR0_EL1.CSV3

On Mon, Jan 08, 2018 at 05:51:00PM +, Will Deacon wrote: > On Mon, Jan 08, 2018 at 09:40:17AM -0800, Jayachandran C wrote: > > On Mon, Jan 08, 2018 at 09:20:09AM +, Marc Zyngier wrote: > > > On 08/01/18 07:24, Jayachandran C wrote: > > > > diff --git a/

Re: [PATCH 2/2] arm64: Branch predictor hardening for Cavium ThunderX2

On Mon, Jan 08, 2018 at 05:23:41PM +, Will Deacon wrote: > On Mon, Jan 08, 2018 at 09:19:43AM -0800, Jayachandran C wrote: > > On Mon, Jan 08, 2018 at 04:46:52PM +, Will Deacon wrote: > > > On Sun, Jan 07, 2018 at 10:53:36PM -0800, Jayachandran C wrote: > > >

Re: [PATCH 2/2] arm64: Branch predictor hardening for Cavium ThunderX2

On Mon, Jan 08, 2018 at 05:23:41PM +, Will Deacon wrote: > On Mon, Jan 08, 2018 at 09:19:43AM -0800, Jayachandran C wrote: > > On Mon, Jan 08, 2018 at 04:46:52PM +, Will Deacon wrote: > > > On Sun, Jan 07, 2018 at 10:53:36PM -0800, Jayachandran C wrote: > > >

Re: [v2,03/11] arm64: Take into account ID_AA64PFR0_EL1.CSV3

On Mon, Jan 08, 2018 at 05:06:24PM +, Will Deacon wrote: > On Sun, Jan 07, 2018 at 11:24:02PM -0800, Jayachandran C wrote: > > On Fri, Jan 05, 2018 at 01:12:33PM +, Will Deacon wrote: > > > For non-KASLR kernels where the KPTI behaviour has not been overridden > >

Re: [v2,03/11] arm64: Take into account ID_AA64PFR0_EL1.CSV3

On Mon, Jan 08, 2018 at 05:06:24PM +, Will Deacon wrote: > On Sun, Jan 07, 2018 at 11:24:02PM -0800, Jayachandran C wrote: > > On Fri, Jan 05, 2018 at 01:12:33PM +, Will Deacon wrote: > > > For non-KASLR kernels where the KPTI behaviour has not been overridden > >

Re: [v2,03/11] arm64: Take into account ID_AA64PFR0_EL1.CSV3

On Mon, Jan 08, 2018 at 09:20:09AM +, Marc Zyngier wrote: > On 08/01/18 07:24, Jayachandran C wrote: > > On Fri, Jan 05, 2018 at 01:12:33PM +, Will Deacon wrote: > >> For non-KASLR kernels where the KPTI behaviour has not been overridden > >> on the command line

Re: [v2,03/11] arm64: Take into account ID_AA64PFR0_EL1.CSV3

On Mon, Jan 08, 2018 at 09:20:09AM +, Marc Zyngier wrote: > On 08/01/18 07:24, Jayachandran C wrote: > > On Fri, Jan 05, 2018 at 01:12:33PM +, Will Deacon wrote: > >> For non-KASLR kernels where the KPTI behaviour has not been overridden > >> on the command line

Re: [PATCH 2/2] arm64: Branch predictor hardening for Cavium ThunderX2

On Mon, Jan 08, 2018 at 04:46:52PM +, Will Deacon wrote: > On Sun, Jan 07, 2018 at 10:53:36PM -0800, Jayachandran C wrote: > > Use PSCI based mitigation for speculative execution attacks targeting > > the branch predictor. The approach is similar to the one used for &g

Re: [PATCH 2/2] arm64: Branch predictor hardening for Cavium ThunderX2

On Mon, Jan 08, 2018 at 04:46:52PM +, Will Deacon wrote: > On Sun, Jan 07, 2018 at 10:53:36PM -0800, Jayachandran C wrote: > > Use PSCI based mitigation for speculative execution attacks targeting > > the branch predictor. The approach is similar to the one used for &g

Re: [v2,03/11] arm64: Take into account ID_AA64PFR0_EL1.CSV3

On Fri, Jan 05, 2018 at 01:12:33PM +, Will Deacon wrote: > For non-KASLR kernels where the KPTI behaviour has not been overridden > on the command line we can use ID_AA64PFR0_EL1.CSV3 to determine whether > or not we should unmap the kernel whilst running at EL0. > > Reviewed-by: Suzuki K

Re: [v2,03/11] arm64: Take into account ID_AA64PFR0_EL1.CSV3

On Fri, Jan 05, 2018 at 01:12:33PM +, Will Deacon wrote: > For non-KASLR kernels where the KPTI behaviour has not been overridden > on the command line we can use ID_AA64PFR0_EL1.CSV3 to determine whether > or not we should unmap the kernel whilst running at EL0. > > Reviewed-by: Suzuki K

[PATCH 2/2] arm64: Branch predictor hardening for Cavium ThunderX2

with the mitigation code to invalidate the branch target buffer, we use the PSCI version call to invoke it. Signed-off-by: Jayachandran C <jn...@caviumnetworks.com> --- arch/arm64/kernel/cpu_errata.c | 38 ++ 1 file changed, 38 insertions(+) diff --git a/arch

[PATCH 2/2] arm64: Branch predictor hardening for Cavium ThunderX2

with the mitigation code to invalidate the branch target buffer, we use the PSCI version call to invoke it. Signed-off-by: Jayachandran C --- arch/arm64/kernel/cpu_errata.c | 38 ++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/kernel/cpu_errata.c b/arch

[PATCH 1/2] arm64: cputype: Add MIDR values for Cavium ThunderX2 CPUs

Add the older Broadcom ID as well as the new Cavium ID for ThunderX2 CPUs. Signed-off-by: Jayachandran C <jn...@caviumnetworks.com> --- arch/arm64/include/asm/cputype.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cpu

[PATCH 1/2] arm64: cputype: Add MIDR values for Cavium ThunderX2 CPUs

Add the older Broadcom ID as well as the new Cavium ID for ThunderX2 CPUs. Signed-off-by: Jayachandran C --- arch/arm64/include/asm/cputype.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 84385b9..cce5735 100644

Re: [v2, 11/11] arm64: Implement branch predictor hardening for affected Cortex-A CPUs

On Fri, Jan 05, 2018 at 01:12:41PM +, Will Deacon wrote: > Cortex-A57, A72, A73 and A75 are susceptible to branch predictor aliasing > and can theoretically be attacked by malicious code. > > This patch implements a PSCI-based mitigation for these CPUs when available. > The call into firmware

Re: [v2, 11/11] arm64: Implement branch predictor hardening for affected Cortex-A CPUs

On Fri, Jan 05, 2018 at 01:12:41PM +, Will Deacon wrote: > Cortex-A57, A72, A73 and A75 are susceptible to branch predictor aliasing > and can theoretically be attacked by malicious code. > > This patch implements a PSCI-based mitigation for these CPUs when available. > The call into firmware

Re: [PATCH V1 0/1] Fix kernel panic caused by device ID duplication presented to the IOMMU

end up with duplicated IDs */ > + for (j = 0; j < i; j++) > + if (fwspec->ids[j] == sid) > + break; > + if (j < i) > + continue; > + > arm_smmu_write_strtab_ent(

Re: [PATCH V1 0/1] Fix kernel panic caused by device ID duplication presented to the IOMMU

end up with duplicated IDs */ > + for (j = 0; j < i; j++) > + if (fwspec->ids[j] == sid) > + break; > + if (j < i) > + continue; > + > arm_smmu_write_strtab_en

[PATCH] MAINTAINERS: Update Cavium ThunderX2 entry

Add Robert Richter as the primary maintainer for this platform. Signed-off-by: Jayachandran C <jn...@caviumnetworks.com> --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 44cb004..f2d8963 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -

[PATCH] MAINTAINERS: Update Cavium ThunderX2 entry

Add Robert Richter as the primary maintainer for this platform. Signed-off-by: Jayachandran C --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 44cb004..f2d8963 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3155,6 +3155,7 @@ S:Supported

Re: [PATCH] irqchip: gicv3-its: Use NUMA aware memory allocation for ITS tables

Hi Marc, On Mon, Jul 10, 2017 at 04:15:28PM +0100, Marc Zyngier wrote: > On 10/07/17 15:57, Shanker Donthineni wrote: > > Hi Marc, > > > > On 07/10/2017 08:50 AM, Marc Zyngier wrote: > >> On 10/07/17 11:21, Ganapatrao Kulkarni wrote: > >>> Hi Marc, > >>> > >>> On Mon, Jul 10, 2017 at 2:53 PM,

Re: [PATCH] irqchip: gicv3-its: Use NUMA aware memory allocation for ITS tables

Hi Marc, On Mon, Jul 10, 2017 at 04:15:28PM +0100, Marc Zyngier wrote: > On 10/07/17 15:57, Shanker Donthineni wrote: > > Hi Marc, > > > > On 07/10/2017 08:50 AM, Marc Zyngier wrote: > >> On 10/07/17 11:21, Ganapatrao Kulkarni wrote: > >>> Hi Marc, > >>> > >>> On Mon, Jul 10, 2017 at 2:53 PM,

Re: [PATCH v3 2/2] acpi, gicv3-its, numa: Adding numa node mapping for gic-its units

On Wed, Jun 21, 2017 at 09:44:58AM +0100, Marc Zyngier wrote: > On 21/06/17 08:09, Jayachandran C wrote: > > On Wed, Jun 21, 2017 at 11:45:43AM +0530, Ganapatrao Kulkarni wrote: > >> Add code to parse SRAT ITS Affinity sub table as defined in ACPI 6.2 > >> Later in pe

Re: [PATCH v3 2/2] acpi, gicv3-its, numa: Adding numa node mapping for gic-its units

On Wed, Jun 21, 2017 at 09:44:58AM +0100, Marc Zyngier wrote: > On 21/06/17 08:09, Jayachandran C wrote: > > On Wed, Jun 21, 2017 at 11:45:43AM +0530, Ganapatrao Kulkarni wrote: > >> Add code to parse SRAT ITS Affinity sub table as defined in ACPI 6.2 > >> Later in pe

Re: [PATCH v3 2/2] acpi, gicv3-its, numa: Adding numa node mapping for gic-its units

On Wed, Jun 21, 2017 at 11:45:43AM +0530, Ganapatrao Kulkarni wrote: > Add code to parse SRAT ITS Affinity sub table as defined in ACPI 6.2 > Later in per device probe, ITS devices are mapped to > numa node using ITS id to proximity domain mapping. > > Signed-off-by: Ganapatrao Kulkarni

Re: [PATCH v3 2/2] acpi, gicv3-its, numa: Adding numa node mapping for gic-its units

On Wed, Jun 21, 2017 at 11:45:43AM +0530, Ganapatrao Kulkarni wrote: > Add code to parse SRAT ITS Affinity sub table as defined in ACPI 6.2 > Later in per device probe, ITS devices are mapped to > numa node using ITS id to proximity domain mapping. > > Signed-off-by: Ganapatrao Kulkarni > --- >

Re: Fwd: [PATCH v7 2/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74

On Fri, Jun 09, 2017 at 04:43:07PM +0100, Robin Murphy wrote: > On 09/06/17 12:38, Jayachandran C wrote: > > On Fri, Jun 09, 2017 Robin Murphy wrote: > >> > >> On 30/05/17 13:03, Geetha sowjanya wrote: > >>> From: Linu Cherian <linu.cher...@cav

Re: Fwd: [PATCH v7 2/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74

On Fri, Jun 09, 2017 at 04:43:07PM +0100, Robin Murphy wrote: > On 09/06/17 12:38, Jayachandran C wrote: > > On Fri, Jun 09, 2017 Robin Murphy wrote: > >> > >> On 30/05/17 13:03, Geetha sowjanya wrote: > >>> From: Linu Cherian > >>> > >>

Re: Fwd: [PATCH v7 2/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74

On Fri, Jun 09, 2017 Robin Murphy wrote: > > On 30/05/17 13:03, Geetha sowjanya wrote: > > From: Linu Cherian > > > > Cavium ThunderX2 SMMU implementation doesn't support page 1 register space > > and PAGE0_REGS_ONLY option is enabled as an errata workaround. > > This

Re: Fwd: [PATCH v7 2/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74

On Fri, Jun 09, 2017 Robin Murphy wrote: > > On 30/05/17 13:03, Geetha sowjanya wrote: > > From: Linu Cherian > > > > Cavium ThunderX2 SMMU implementation doesn't support page 1 register space > > and PAGE0_REGS_ONLY option is enabled as an errata workaround. > > This option when turned on,

Re: [PATCH v2] arm64: perf: Use only exclude_kernel attribute when kernel is running in HYP

On Fri, Apr 28, 2017 at 05:38:23PM +0100, Will Deacon wrote: > Hi guys, > > On Fri, Apr 28, 2017 at 01:46:24PM +, Jayachandran C wrote: > > On Thu, Apr 27, 2017 at 06:37:59PM +0100, Will Deacon wrote: > > > > If my understanding is correct, the sysfs suggestion ab

Re: [PATCH v2] arm64: perf: Use only exclude_kernel attribute when kernel is running in HYP

On Fri, Apr 28, 2017 at 05:38:23PM +0100, Will Deacon wrote: > Hi guys, > > On Fri, Apr 28, 2017 at 01:46:24PM +, Jayachandran C wrote: > > On Thu, Apr 27, 2017 at 06:37:59PM +0100, Will Deacon wrote: > > > > If my understanding is correct, the sysfs suggestion ab

Re: [PATCH v2] arm64: perf: Use only exclude_kernel attribute when kernel is running in HYP

On Thu, Apr 27, 2017 at 06:37:59PM +0100, Will Deacon wrote: > On Wed, Apr 26, 2017 at 01:41:42PM +0000, Jayachandran C wrote: > > On Wed, Apr 26, 2017 at 11:10:21AM +0100, Will Deacon wrote: > > > On Wed, Apr 26, 2017 at 07:22:46AM +, Pinski, Andrew wrote: > > &

Re: [PATCH v2] arm64: perf: Use only exclude_kernel attribute when kernel is running in HYP

On Thu, Apr 27, 2017 at 06:37:59PM +0100, Will Deacon wrote: > On Wed, Apr 26, 2017 at 01:41:42PM +0000, Jayachandran C wrote: > > On Wed, Apr 26, 2017 at 11:10:21AM +0100, Will Deacon wrote: > > > On Wed, Apr 26, 2017 at 07:22:46AM +, Pinski, Andrew wrote: > > &

Re: [PATCH v2 1/4] perf utils: passing pmu as a parameter to function get_cpuid_str

On Fri, Apr 28, 2017 at 10:23:44AM +0530, Ganapatrao Kulkarni wrote: > cpuid string will not be same on all CPUs on heterogeneous > platforms like ARM's big.LITTLE, adding provision(using pmu->cpus) > to find cpuid string from associated CPUs of PMU CORE device. > > Signed-off-by: Ganapatrao

Re: [PATCH v2 1/4] perf utils: passing pmu as a parameter to function get_cpuid_str

On Fri, Apr 28, 2017 at 10:23:44AM +0530, Ganapatrao Kulkarni wrote: > cpuid string will not be same on all CPUs on heterogeneous > platforms like ARM's big.LITTLE, adding provision(using pmu->cpus) > to find cpuid string from associated CPUs of PMU CORE device. > > Signed-off-by: Ganapatrao

Re: [PATCH 1/3] arm64: Add MIDR values for Cavium cn99xx SoCs

On Thu, Apr 27, 2017 at 5:16 PM, Geetha sowjanya wrote: > From: Geetha > > Add MIDR values for Cavium cn99xx SoCs > > Signed-off-by: Geetha > --- > arch/arm64/include/asm/cputype.h | 3 +++ > 1 file changed, 3 insertions(+) > >

Re: [PATCH 1/3] arm64: Add MIDR values for Cavium cn99xx SoCs

On Thu, Apr 27, 2017 at 5:16 PM, Geetha sowjanya wrote: > From: Geetha > > Add MIDR values for Cavium cn99xx SoCs > > Signed-off-by: Geetha > --- > arch/arm64/include/asm/cputype.h | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/arch/arm64/include/asm/cputype.h >

Re: [PATCH v2] arm64: perf: Use only exclude_kernel attribute when kernel is running in HYP

On Wed, Apr 26, 2017 at 11:10:21AM +0100, Will Deacon wrote: > On Wed, Apr 26, 2017 at 07:22:46AM +, Pinski, Andrew wrote: > > On 4/25/2017 11:53 PM, Jayachandran C. wrote: > > > On Tue, Apr 25, 2017 at 10:23 PM, Will Deacon <will.dea...@arm.com> wrote: > > &g

Re: [PATCH v2] arm64: perf: Use only exclude_kernel attribute when kernel is running in HYP

On Wed, Apr 26, 2017 at 11:10:21AM +0100, Will Deacon wrote: > On Wed, Apr 26, 2017 at 07:22:46AM +, Pinski, Andrew wrote: > > On 4/25/2017 11:53 PM, Jayachandran C. wrote: > > > On Tue, Apr 25, 2017 at 10:23 PM, Will Deacon wrote: > > >> On Tue, Apr 25, 2017 a

Re: [PATCH v2] arm64: perf: Use only exclude_kernel attribute when kernel is running in HYP

Hi Will, On Tue, Apr 25, 2017 at 10:23 PM, Will Deacon wrote: > On Tue, Apr 25, 2017 at 09:13:40AM +0530, Ganapatrao Kulkarni wrote: >> On Mon, Apr 24, 2017 at 9:15 PM, Will Deacon wrote: >> > On Thu, Apr 20, 2017 at 02:56:50PM +0530, Ganapatrao

Re: [PATCH v2] arm64: perf: Use only exclude_kernel attribute when kernel is running in HYP

Hi Will, On Tue, Apr 25, 2017 at 10:23 PM, Will Deacon wrote: > On Tue, Apr 25, 2017 at 09:13:40AM +0530, Ganapatrao Kulkarni wrote: >> On Mon, Apr 24, 2017 at 9:15 PM, Will Deacon wrote: >> > On Thu, Apr 20, 2017 at 02:56:50PM +0530, Ganapatrao Kulkarni wrote: >> >> On Thu, Apr 20, 2017 at

Re: [PATCH v3] Revert "tty: serial: pl011: add ttyAMA for matching pl011 console"

0ba98a0c9b4de88850260e9fbdcc98360b. >> > > Sorry for that, I will test your patches and respond to that. For this > patch: > > Acked-by: Sudeep Holla <sudeep.ho...@arm.com> > This fixes a regression I see in v4.11-rc2 Tested-by: Jayachandran C <jn...@caviumnetworks.com> I don't see it in the tty/serial tree yet JC.

Re: [PATCH v3] Revert "tty: serial: pl011: add ttyAMA for matching pl011 console"

260e9fbdcc98360b. >> > > Sorry for that, I will test your patches and respond to that. For this > patch: > > Acked-by: Sudeep Holla > This fixes a regression I see in v4.11-rc2 Tested-by: Jayachandran C I don't see it in the tty/serial tree yet JC.

[PATCH 3/3] arm64: add ARCH_THUNDER2 to defconfig

This will allow the default kernel build to boot on Cavium ThunderX2 CN99XX processors. Signed-off-by: Jayachandran C <jn...@caviumnetworks.com> --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig

[PATCH 3/3] arm64: add ARCH_THUNDER2 to defconfig

This will allow the default kernel build to boot on Cavium ThunderX2 CN99XX processors. Signed-off-by: Jayachandran C --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 33b744d..7a9c262 100644

[PATCH 2/3] dt-bindings: arm64 ARCH_THUNDER2 platform documentation

Add documentation for Cavium ThunderX2 CN99XX ARM64 processor family. The processor core will use cavium,thunder2 as ID and the SoC will use cavium,thunder-99xx Signed-off-by: Jayachandran C <jn...@caviumnetworks.com> --- Documentation/devicetree/bindings/arm/cavium-thunder2.t

[PATCH 1/3] arm64: add THUNDER2 processor family

-by: Jayachandran C <jn...@caviumnetworks.com> --- arch/arm64/Kconfig.platforms | 7 ++ arch/arm64/boot/dts/cavium/Makefile | 1 + arch/arm64/boot/dts/cavium/thunder-99xx.dts | 34 +++ arch/arm64/boot/dts/cavium/thunder-99xx.dtsi | 147 +++ 4

[PATCH 2/3] dt-bindings: arm64 ARCH_THUNDER2 platform documentation

Add documentation for Cavium ThunderX2 CN99XX ARM64 processor family. The processor core will use cavium,thunder2 as ID and the SoC will use cavium,thunder-99xx Signed-off-by: Jayachandran C --- Documentation/devicetree/bindings/arm/cavium-thunder2.txt | 5 + Documentation/devicetree

[PATCH 1/3] arm64: add THUNDER2 processor family

-by: Jayachandran C --- arch/arm64/Kconfig.platforms | 7 ++ arch/arm64/boot/dts/cavium/Makefile | 1 + arch/arm64/boot/dts/cavium/thunder-99xx.dts | 34 +++ arch/arm64/boot/dts/cavium/thunder-99xx.dtsi | 147 +++ 4 files changed, 189 insertions

[PATCH 0/3] arm64: Add ARCH_THUNDER2

This patchset adds support for the new ThunderX2 CN99XX processor family. Changes are to add the config option, the required device tree files, the device tree bindings documentation and the defconfig entry. JC. Jayachandran C (3): arm64: add THUNDER2 processor family dt-bindings: arm64

[PATCH 0/3] arm64: Add ARCH_THUNDER2

This patchset adds support for the new ThunderX2 CN99XX processor family. Changes are to add the config option, the required device tree files, the device tree bindings documentation and the defconfig entry. JC. Jayachandran C (3): arm64: add THUNDER2 processor family dt-bindings: arm64

Re: [PATCH 04/14] PCI: generic: make it explicitly non-modular

On Wed, Jul 6, 2016 at 1:49 AM, David Daney wrote: > > On 07/04/2016 10:37 AM, Will Deacon wrote: >> >> On Sat, Jul 02, 2016 at 07:13:24PM -0400, Paul Gortmaker wrote: >>> >>> The Kconfig currently controlling compilation of this code is: >>> >>>

Re: [PATCH 04/14] PCI: generic: make it explicitly non-modular

On Wed, Jul 6, 2016 at 1:49 AM, David Daney wrote: > > On 07/04/2016 10:37 AM, Will Deacon wrote: >> >> On Sat, Jul 02, 2016 at 07:13:24PM -0400, Paul Gortmaker wrote: >>> >>> The Kconfig currently controlling compilation of this code is: >>> >>> drivers/pci/host/Kconfig:config PCI_HOST_GENERIC

Re: [PATCH V8 9/9] pci, acpi: ARM64 support for ACPI based generic PCI host controller

On Mon, May 30, 2016 at 9:08 PM, Arnd Bergmann wrote: > On Monday, May 30, 2016 5:14:22 PM CEST Tomasz Nowicki wrote: >> + bsz = 1 << pci_generic_ecam_ops.bus_shift; >> + cfgres.start = root->mcfg_addr + bus_res->start * bsz; >> + cfgres.end = cfgres.start +

Re: [PATCH V8 9/9] pci, acpi: ARM64 support for ACPI based generic PCI host controller

On Mon, May 30, 2016 at 9:08 PM, Arnd Bergmann wrote: > On Monday, May 30, 2016 5:14:22 PM CEST Tomasz Nowicki wrote: >> + bsz = 1 << pci_generic_ecam_ops.bus_shift; >> + cfgres.start = root->mcfg_addr + bus_res->start * bsz; >> + cfgres.end = cfgres.start +

Re: [PATCH V7 04/11] pci: Add new function to unmap IO resources.

On Tue, May 10, 2016 at 8:49 PM, Tomasz Nowicki wrote: > It is very useful to release I/O resources so that the same I/O resources > can be allocated again (pci_remap_iospace), like in PCI hotplug removal > scenario. Therefore this patch implements new pci_unmap_iospace call

Re: [PATCH V7 04/11] pci: Add new function to unmap IO resources.

On Tue, May 10, 2016 at 8:49 PM, Tomasz Nowicki wrote: > It is very useful to release I/O resources so that the same I/O resources > can be allocated again (pci_remap_iospace), like in PCI hotplug removal > scenario. Therefore this patch implements new pci_unmap_iospace call which > unmaps I/O

Re: [PATCH V7 08/11] pci, acpi: Support for ACPI based generic PCI host controller

to create and access ECAM mappings. > > As mentioned in Kconfig help section, ACPI_PCI_HOST_GENERIC choice > should be made on a per-architecture basis. Looking thru the new code, I see a few issues, please see below > Signed-off-by: Tomasz Nowicki <t...@semihalf.com> >

Re: [PATCH V7 08/11] pci, acpi: Support for ACPI based generic PCI host controller

s ECAM mappings. > > As mentioned in Kconfig help section, ACPI_PCI_HOST_GENERIC choice > should be made on a per-architecture basis. Looking thru the new code, I see a few issues, please see below > Signed-off-by: Tomasz Nowicki > Signed-off-by: Jayachandran C > --- > driv

Re: [PATCH V7 08/11] pci, acpi: Support for ACPI based generic PCI host controller

to create and access ECAM mappings. > > As mentioned in Kconfig help section, ACPI_PCI_HOST_GENERIC choice > should be made on a per-architecture basis. > > Signed-off-by: Tomasz Nowicki <t...@semihalf.com> > Signed-off-by: Jayachandran C <jchan...@broadcom.com> > --

Re: [PATCH V7 08/11] pci, acpi: Support for ACPI based generic PCI host controller

s ECAM mappings. > > As mentioned in Kconfig help section, ACPI_PCI_HOST_GENERIC choice > should be made on a per-architecture basis. > > Signed-off-by: Tomasz Nowicki > Signed-off-by: Jayachandran C > --- [] > diff --git a/drivers/pci/ecam.h b/drivers/pci/ecam.h >

Re: [PATCH V7 07/11] pci, acpi: Handle ACPI companion assignment.

set the ACPI companion pointer and >> >> > call it from PCI core code. The function is stub for now. >> >> > >> >> > Signed-off-by: Jayachandran C <jchan...@broadcom.com> >> >> > Signed-off-by: Tomasz Nowicki <t...@semihalf.com> &g

Re: [PATCH V7 07/11] pci, acpi: Handle ACPI companion assignment.

gt;> On Tue, May 10, 2016 at 5:19 PM, Tomasz Nowicki wrote: >> >> > This patch provides a way to set the ACPI companion in PCI code. >> >> > We define acpi_pci_set_companion() to set the ACPI companion pointer and >> >> > call it from PCI core

Re: [PATCH V6 07/13] PCI: Provide common functions for ECAM mapping

On Fri, Apr 29, 2016 at 1:31 PM, Jayachandran C <jchan...@broadcom.com> wrote: > On Fri, Apr 29, 2016 at 3:17 AM, Bjorn Helgaas <helg...@kernel.org> wrote: >> On Fri, Apr 15, 2016 at 07:06:42PM +0200, Tomasz Nowicki wrote: >>> From: Jayachandran C <jchan...@broadc

Re: [PATCH V6 07/13] PCI: Provide common functions for ECAM mapping

On Fri, Apr 29, 2016 at 1:31 PM, Jayachandran C wrote: > On Fri, Apr 29, 2016 at 3:17 AM, Bjorn Helgaas wrote: >> On Fri, Apr 15, 2016 at 07:06:42PM +0200, Tomasz Nowicki wrote: >>> From: Jayachandran C >>> >>> Add config option PCI_GENERIC_ECAM and fi

Re: [PATCH V6 02/13] pci, acpi: Provide generic way to assign bus domain number.

On Tue, May 3, 2016 at 4:32 PM, Lorenzo Pieralisi <lorenzo.pieral...@arm.com> wrote: > On Mon, May 02, 2016 at 06:56:13PM +0530, Jayachandran C wrote: >> On Mon, May 2, 2016 at 6:13 PM, Tomasz Nowicki <t...@semihalf.com> wrote: >> > On 04/27/2016 01:

Re: [PATCH V6 02/13] pci, acpi: Provide generic way to assign bus domain number.

On Tue, May 3, 2016 at 4:32 PM, Lorenzo Pieralisi wrote: > On Mon, May 02, 2016 at 06:56:13PM +0530, Jayachandran C wrote: >> On Mon, May 2, 2016 at 6:13 PM, Tomasz Nowicki wrote: >> > On 04/27/2016 01:17 PM, Lorenzo Pieralisi wrote: >> >> >> >> On Tu

Re: [PATCH V6 02/13] pci, acpi: Provide generic way to assign bus domain number.

On Mon, May 2, 2016 at 6:13 PM, Tomasz Nowicki wrote: > On 04/27/2016 01:17 PM, Lorenzo Pieralisi wrote: >> >> On Tue, Apr 26, 2016 at 09:26:49PM -0500, Bjorn Helgaas wrote: >>> >>> On Fri, Apr 15, 2016 at 07:06:37PM +0200, Tomasz Nowicki wrote: > > [...] > >>> +int

Re: [PATCH V6 02/13] pci, acpi: Provide generic way to assign bus domain number.

On Mon, May 2, 2016 at 6:13 PM, Tomasz Nowicki wrote: > On 04/27/2016 01:17 PM, Lorenzo Pieralisi wrote: >> >> On Tue, Apr 26, 2016 at 09:26:49PM -0500, Bjorn Helgaas wrote: >>> >>> On Fri, Apr 15, 2016 at 07:06:37PM +0200, Tomasz Nowicki wrote: > > [...] > >>> +int

Re: [PATCH V6 09/13] pci, acpi: Support for ACPI based generic PCI host controller

On Fri, Apr 29, 2016 at 2:07 PM, Lorenzo Pieralisi wrote: > On Thu, Apr 28, 2016 at 04:48:00PM -0500, Bjorn Helgaas wrote: > > [...] > >> > +static int pci_acpi_setup_ecam_mapping(struct acpi_pci_root *root, >> > + struct

Re: [PATCH V6 09/13] pci, acpi: Support for ACPI based generic PCI host controller

On Fri, Apr 29, 2016 at 2:07 PM, Lorenzo Pieralisi wrote: > On Thu, Apr 28, 2016 at 04:48:00PM -0500, Bjorn Helgaas wrote: > > [...] > >> > +static int pci_acpi_setup_ecam_mapping(struct acpi_pci_root *root, >> > + struct acpi_pci_generic_root_info *ri) >> > +{ >>

Re: [PATCH V6 07/13] PCI: Provide common functions for ECAM mapping

On Fri, Apr 29, 2016 at 3:17 AM, Bjorn Helgaas <helg...@kernel.org> wrote: > On Fri, Apr 15, 2016 at 07:06:42PM +0200, Tomasz Nowicki wrote: >> From: Jayachandran C <jchan...@broadcom.com> >> >> Add config option PCI_GENERIC_ECAM and file drivers/pci/ecam.

Re: [PATCH V6 07/13] PCI: Provide common functions for ECAM mapping

On Fri, Apr 29, 2016 at 3:17 AM, Bjorn Helgaas wrote: > On Fri, Apr 15, 2016 at 07:06:42PM +0200, Tomasz Nowicki wrote: >> From: Jayachandran C >> >> Add config option PCI_GENERIC_ECAM and file drivers/pci/ecam.c to >> provide generic functions for accessing mem

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