ctx->mb_err_cnt_ctrl could be NULL in case of failed initialization
(on decoders), and encoders don't use it at all.
Fixes: b2d3bef1aa78 ("media: coda: Add a V4L2 user for control error
macroblocks count")
Signed-off-by: Krzysztof Halasa
Cc: sta...@vger.kernel.org # 5.11+
diff --
sky2.c driver uses netdev_warn() before the net device is initialized.
Fix it by using dev_warn() instead.
Signed-off-by: Krzysztof Halasa
--- a/drivers/net/ethernet/marvell/sky2.c
+++ b/drivers/net/ethernet/marvell/sky2.c
@@ -4806,12 +4806,11 @@ static struct net_device *sky2_init_netdev
ader, nothing depends on it (nor the other way around), it's just
(with the rest of the wanXL code) an old piece of a driver for an old
card.
The question is, what do we gain by messing with it?
--
Krzysztof Halasa
it (nor the other way around), it's just
(with the rest of the wanXL code) an old piece of a driver for an old
card.
The question is, what do we gain by messing with it?
--
Krzysztof Halasa
68360
(the original QUICC) processor. Maximum bit rate of 2 Mb/s on each sync
serial port.
It's more about delivering the .S source for the firmware, I guess.
Nobody is expected to build it. The fw is about 2.5 KB and is directly
linked with the driver.
--
Krzysztof Halasa
rocessor. Maximum bit rate of 2 Mb/s on each sync
serial port.
It's more about delivering the .S source for the firmware, I guess.
Nobody is expected to build it. The fw is about 2.5 KB and is directly
linked with the driver.
--
Krzysztof Halasa
point,
I don't know.
Perhaps I could look at this later, but no promises (this requires
pulling on and setting up some legacy hardware).
Anyway, since the patch is safe and can solve an existing problem:
Acked-by: Krzysztof Halasa <k...@pm.waw.pl>
--
Krzysztof Halasa
Perhaps I could look at this later, but no promises (this requires
pulling on and setting up some legacy hardware).
Anyway, since the patch is safe and can solve an existing problem:
Acked-by: Krzysztof Halasa
--
Krzysztof Halasa
Kees Cook <keesc...@chromium.org> writes:
> Several timer users needlessly reset their .function/.data fields during
> their timer callback, but nothing else changes them. Some users do not
> use their .data field at all. Each instance is removed here.
For *wan/hdlc*
Acked-by: K
Kees Cook writes:
> Several timer users needlessly reset their .function/.data fields during
> their timer callback, but nothing else changes them. Some users do not
> use their .data field at all. Each instance is removed here.
For *wan/hdlc*
Acked-by: Krzysztof Halasa
> --- a
I think this bug needs to be fixed, this way or another.
The platform in question is Cavium CNS3xxx, ARMv6.
A recent patch by Arnd Bergmann (498a92d42596 "ARM: cns3xxx: pci: avoid
potential stack overflow") converted an explicit setting of
PCI_EXP_DEVCTL_READRQ = 0 (i.e., max 128 bytes for
I think this bug needs to be fixed, this way or another.
The platform in question is Cavium CNS3xxx, ARMv6.
A recent patch by Arnd Bergmann (498a92d42596 "ARM: cns3xxx: pci: avoid
potential stack overflow") converted an explicit setting of
PCI_EXP_DEVCTL_READRQ = 0 (i.e., max 128 bytes for
The platform in question is Cavium CNS3xxx, ARMv6.
A recent patch by Arnd Bergmann (498a92d42596 "ARM: cns3xxx: pci: avoid
potential stack overflow") converted an explicit setting of
PCI_EXP_DEVCTL_READRQ = 0 (i.e., max 128 bytes for bus-mastering PCIe DMA
read request) to:
+pcie_bus_config =
The platform in question is Cavium CNS3xxx, ARMv6.
A recent patch by Arnd Bergmann (498a92d42596 "ARM: cns3xxx: pci: avoid
potential stack overflow") converted an explicit setting of
PCI_EXP_DEVCTL_READRQ = 0 (i.e., max 128 bytes for bus-mastering PCIe DMA
read request) to:
+pcie_bus_config =
t & PACKET_PORT_MASK) > card->n_ports)
> pr_crit("%s: received packet for nonexistent port\n",
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Mo
)
pr_crit(%s: received packet for nonexistent port\n,
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Stephen Boyd writes:
> The 32 bit sched_clock interface now supports 64 bits. Upgrade to
> the 64 bit function to allow us to remove the 32 bit registration
> interface.
Don't find anything wrong in this.
Acked-by: Krzysztof Halasa
> +++ b/arch/arm/mach-ixp4xx/common.c
> @
Stephen Boyd sb...@codeaurora.org writes:
The 32 bit sched_clock interface now supports 64 bits. Upgrade to
the 64 bit function to allow us to remove the 32 bit registration
interface.
Don't find anything wrong in this.
Acked-by: Krzysztof Halasa k...@pm.waw.pl
+++ b/arch/arm/mach-ixp4xx
tform device with the correct
> DMA mask etc.
That's also my idea. Will look at this.
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the platform device with the correct
DMA mask etc.
That's also my idea. Will look at this.
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s in one place, in
Ethernet driver code) was better, though not perfect.
My fault is I haven't fixed it yet. Will try to invent something.
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More ma
) was better, though not perfect.
My fault is I haven't fixed it yet. Will try to invent something.
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xx/include/mach/timex.h | 2 +-
Acked-by: Krzysztof Halasa
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Please read the F
/mach/timex.h | 2 +-
Acked-by: Krzysztof Halasa k...@pm.waw.pl
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the call to dma_set_coherent_mask() from within the
> driver also seems to be questionable as it bypasses the "check if the
> mask is possible" part of the DMA API.
I thought about this for a second but the situation is the mask
is guaranteed to be valid (these are on-chip devices).
--
Krz
to be questionable as it bypasses the check if the
mask is possible part of the DMA API.
I thought about this for a second but the situation is the mask
is guaranteed to be valid (these are on-chip devices).
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;dev = >dev;
port->plat = pdev->dev.platform_data;
+ dma_set_coherent_mask(>dev, DMA_BIT_MASK(32));
netif_napi_add(dev, >napi, hss_hdlc_poll, NAPI_WEIGHT);
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what do you think?
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?
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;
+ dma_set_coherent_mask(dev-dev, DMA_BIT_MASK(32));
netif_napi_add(dev, port-napi, hss_hdlc_poll, NAPI_WEIGHT);
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4xx arch part makes
IXP4xx's dma_set_coherent_mask() compliant with DMA API, and the actual
dma_set_coherent_mask() calls in drivers are both valid and I guess
recommended by the API.
The patch doesn't touch the core ARM issue, that's right.
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IXP4xx's dma_set_coherent_mask() compliant with DMA API, and the actual
dma_set_coherent_mask() calls in drivers are both valid and I guess
recommended by the API.
The patch doesn't touch the core ARM issue, that's right.
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ARM core code currently requires coherent DMA mask to be set. Make sure
we limit PCI devices to 64 MiB while allowing on-chip devices to access
the whole 4 GiB address space.
This fixes a v3.7+ regression which broke IXP4xx built-in network devices.
Signed-off-by: Krzysztof Hałasa
Cc:
diff
ARM core code currently requires coherent DMA mask to be set. Make sure
we limit PCI devices to 64 MiB while allowing on-chip devices to access
the whole 4 GiB address space.
This fixes a v3.7+ regression which broke IXP4xx built-in network devices.
Signed-off-by: Krzysztof Hałasa k...@pm.waw.pl
't).
What the driver should use is:
err = dma_set_coherent_mask(xxx);
(but the subsystem have to be fixed first).
Also, according to DMA-API, 32-bit is the default.
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);
(but the subsystem have to be fixed first).
Also, according to DMA-API, 32-bit is the default.
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drivers/net/wan/hdlc.c| 9 -
> drivers/net/wan/x25_asy.c | 1 -
> 4 files changed, 10 insertions(+), 15 deletions(-)
Good to see.
Acked-by: Krzysztof Halasa
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| 9 -
drivers/net/wan/x25_asy.c | 1 -
4 files changed, 10 insertions(+), 15 deletions(-)
Good to see.
Acked-by: Krzysztof Halasa k...@pm.waw.pl
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ners, I have to quit doing this.
BTW since Imre has probably even much less time, it would be a good time
to find someone to maintain IXP4xx code. I will be publishing (from time
to time) my tree (I'm using the hw myself), so even simple
cherry-picking would probably make some sense.
--
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probably even much less time, it would be a good time
to find someone to maintain IXP4xx code. I will be publishing (from time
to time) my tree (I'm using the hw myself), so even simple
cherry-picking would probably make some sense.
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ers/crypto/Kconfig | 2 +-
drivers/crypto/ixp4xx_crypto.c | 12 ++--
drivers/net/wan/ixp4xx_hss.c| 2 +-
13 files changed, 59 insertions(+), 68 deletions(-)
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/Kconfig | 2 +-
drivers/crypto/ixp4xx_crypto.c | 12 ++--
drivers/net/wan/ixp4xx_hss.c| 2 +-
13 files changed, 59 insertions(+), 68 deletions(-)
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ntually submit a) upstream, then arm-soc and Linus' trees
would work for me. I know it's a mess, but for now I have no options.
BTW the situation with hardware supported only by OpenWRT is a part of
the equation.
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, then arm-soc and Linus' trees
would work for me. I know it's a mess, but for now I have no options.
BTW the situation with hardware supported only by OpenWRT is a part of
the equation.
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better way (given the limitations), I'm open.
BTW I still think I'm a part of the community, even if I don't submit
code through arm-soc :-)
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for
additional months? Doesn't "release early, release often" make sense
anymore?
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ding through intermediate trees. In
fact, now that I have at last a bit of spare time to work on IXP4xx
again (acquired some IXP435 devices), such requirement would only mean
extra workload to me.
Could you please point me to a statement requiring eg. my changes to go
through arm-soc?
Thanks.
--
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intermediate trees. In
fact, now that I have at last a bit of spare time to work on IXP4xx
again (acquired some IXP435 devices), such requirement would only mean
extra workload to me.
Could you please point me to a statement requiring eg. my changes to go
through arm-soc?
Thanks.
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. What's the _real_ reason for asking me to push my changes
indirectly?
Also, not that it's the most important, but how is it better for anyone
to delay changes - which are completely orthogonal to arm-soc - for
additional months? Doesn't release early, release often make sense
anymore?
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of the community, even if I don't submit
code through arm-soc :-)
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XX_EXP_CFG2 = ~value;
> + __raw_writel(~cpu_to_le32(value), IXP4XX_EXP_CFG2);
> }
The EXP_CFG2 register is already in host order, no need for
cpu_to_le32() as the replaced code clearly shows.
Can you merge both IXP4xx parts (in the two patches) and fix the above,
please? Thanks.
--
Krzyszt
Krzysztof Halasa writes:
>> At the moment, this patch conflicts with other patches in linux-next,
>> need to sort this out.
>
> Very nice, I will take care of these 3 patches.
I mean, just this one IXP4xx patch :-)
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Stephen Rothwell writes:
>> >>> git://git.kernel.org/pub/scm/linux/kernel/git/chris/linux.git branch:
>> >>> next
> OK, I have added your tree from today.
Thanks a lot.
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Arnd Bergmann writes:
> ARM is moving to stricter checks on readl/write functions,
> so we need to use the correct types everywhere.
>
> At the moment, this patch conflicts with other patches in linux-next,
> need to sort this out.
Very nice, I will take care of these 3 patches
.
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Stephen Rothwell s...@canb.auug.org.au writes:
git://git.kernel.org/pub/scm/linux/kernel/git/chris/linux.git branch:
next
OK, I have added your tree from today.
Thanks a lot.
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Krzysztof Halasa k...@pm.waw.pl writes:
At the moment, this patch conflicts with other patches in linux-next,
need to sort this out.
Very nice, I will take care of these 3 patches.
I mean, just this one IXP4xx patch :-)
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(~cpu_to_le32(value), IXP4XX_EXP_CFG2);
}
The EXP_CFG2 register is already in host order, no need for
cpu_to_le32() as the replaced code clearly shows.
Can you merge both IXP4xx parts (in the two patches) and fix the above,
please? Thanks.
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your side.
Not sure about these other people/lists, added lkml.
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.
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ing work
> is merged.
I see. Thanks.
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11 pts/4Ss 0:00 \_ -sh
413 pts/4D+ 0:00 \_ [microcom]
415 pts/0D 0:00 iru
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Ss 0:00 \_ -sh
413 pts/4D+ 0:00 \_ [microcom]
415 pts/0D 0:00 iru
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is merged.
I see. Thanks.
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> \
> printk(pri "%s: " fmt, npe_name(npe), ## __VA_ARGS__)
> @@ -724,6 +728,9 @@ module_exit(npe_cleanup_module);
>
> MODULE_AUTHOR("Krzysztof Halasa");
> MODULE_LICENSE("GPL v2");
> +MODULE_FIRMWARE(
+728,9 @@ module_exit(npe_cleanup_module);
MODULE_AUTHOR(Krzysztof Halasa);
MODULE_LICENSE(GPL v2);
+MODULE_FIRMWARE(NPE_A_FIRMWARE);
+MODULE_FIRMWARE(NPE_B_FIRMWARE);
+MODULE_FIRMWARE(NPE_C_FIRMWARE);
EXPORT_SYMBOL(npe_names);
EXPORT_SYMBOL(npe_running);
This looks like a good
t; module abusers more cautious.
Those not using _GPL exports?
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_GPL exports are really harmful - somebody
distributing a binary module may claim he/she doesn't violate the GPL
because the module uses only non-GPL exports. OTOH GPL symbols give
_us_ exactly nothing.
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Jan Engelhardt <[EMAIL PROTECTED]> writes:
> Now back to coding, oh and don't forget send a patch for CodingStyle
> since a mail without one is often taken even less seriously.
Someone with a patch to Emacs to use tabs for ident + spaces for
alignment maybe? :-)
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are really derivative works and it doesn't mean a
module not using any _GPL exports isn't a derivative.
I think introducing these _GPL symbols was a mistake in the first place.
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module not using any _GPL exports isn't a derivative.
I think introducing these _GPL symbols was a mistake in the first place.
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Jan Engelhardt [EMAIL PROTECTED] writes:
Now back to coding, oh and don't forget send a patch for CodingStyle
since a mail without one is often taken even less seriously.
Someone with a patch to Emacs to use tabs for ident + spaces for
alignment maybe? :-)
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are really harmful - somebody
distributing a binary module may claim he/she doesn't violate the GPL
because the module uses only non-GPL exports. OTOH GPL symbols give
_us_ exactly nothing.
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exports?
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ly possible now.
>> Unpacked sources will be much bigger with not tabs, sure.
>>
> Without no tabs at all, you mean?
With spaces in place of all tabs.
All tabs converted to spaces = 20% more?
"Alignment" tabs converted to spaces? How cares how much more would it
t
space? ;)
Unpacked sources will be much bigger with not tabs, sure.
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code checkers find the same hotspots.
I think you misunderstood. Of course I'm not against warnings in
general. I'm rather talking about _authority_ of human vs machine,
in this specific ("measuring" code complexity) case.
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the same hotspots.
I think you misunderstood. Of course I'm not against warnings in
general. I'm rather talking about _authority_ of human vs machine,
in this specific (measuring code complexity) case.
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with not tabs, sure.
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no tabs at all, you mean?
With spaces in place of all tabs.
All tabs converted to spaces = 20% more?
Alignment tabs converted to spaces? How cares how much more would it
take if it's the correct thing. Except that it's not very practical at
this point.
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Pavel Machek <[EMAIL PROTECTED]> writes:
>> Come on, are you doing Linux kernel development on PDA?
>
> I review patches on it, sometimes, yes.
I take it the "sometimes" is the key word :-)
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Pavel Machek [EMAIL PROTECTED] writes:
Come on, are you doing Linux kernel development on PDA?
I review patches on it, sometimes, yes.
I take it the sometimes is the key word :-)
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> nicely wrap at 78.
Sure - because email is not C code.
Actually you don't "read" C code, word by word, as you read books - do
you?
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Pavel Machek <[EMAIL PROTECTED]> writes:
> Zaurus is one example, second is small screen where you need big font
> to keep it readable (x60 on desk).
Come on, are you doing Linux kernel development on PDA?
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ould be free to ignore the advice. People upstream won't
be fooled by some cheap tab tricks I guess.
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n looking at the code is far better at
spotting such problems. Machine-generated warnings are great when the
machine is actually better than human.
Anyway, warnings are one thing and line limit is another. We may raise
the limit leaving the 80-chars warning in place. Unless there are too
many false positiv
such problems. Machine-generated warnings are great when the
machine is actually better than human.
Anyway, warnings are one thing and line limit is another. We may raise
the limit leaving the 80-chars warning in place. Unless there are too
many false positives, of course.
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Pavel Machek [EMAIL PROTECTED] writes:
Zaurus is one example, second is small screen where you need big font
to keep it readable (x60 on desk).
Come on, are you doing Linux kernel development on PDA?
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. People upstream won't
be fooled by some cheap tab tricks I guess.
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email is not C code.
Actually you don't read C code, word by word, as you read books - do
you?
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able).
So I think it just have to meet the author's and reviewers' taste. We
already depend on this.
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Raise the limit, terminal windows will follow.
I'm using 80-column windows, too.
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kernel
code. Obviously printk() _output_ etc. should stay at 80.
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printk() _output_ etc. should stay at 80.
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, terminal windows will follow.
I'm using 80-column windows, too.
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have to meet the author's and reviewers' taste. We
already depend on this.
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Please read
handshaking at all? Most (all?) UPSes I used
had only TxD and RxD (for RS-232).
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and RxD (for RS-232).
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"Kok, Auke" <[EMAIL PROTECTED]> writes:
>>> Don't work by default. "pci=nomsi" fixes the problem.
>
> actually does not fix anything - it just works around it by falling
> back to legacy interrupts.
Actually it does, fixes the problem by working arou
oration MCP51 Memory Controller 0 (rev a3)
00:10.0 PCI bridge: nVidia Corporation MCP51 PCI Bridge (rev a2)
Additional details on request.
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