On 2021-03-17 10:02, Quentin Perret wrote:
On Wednesday 17 Mar 2021 at 09:41:09 (+0100), Mate Toth-Pal wrote:
On 2021-03-16 18:46, Quentin Perret wrote:
On Tuesday 16 Mar 2021 at 16:16:18 (+0100), Mate Toth-Pal wrote:
On 2021-03-16 15:29, Quentin Perret wrote:
On Tuesday 16 Mar 2021 at 12:53
On 2021-03-16 18:46, Quentin Perret wrote:
On Tuesday 16 Mar 2021 at 16:16:18 (+0100), Mate Toth-Pal wrote:
On 2021-03-16 15:29, Quentin Perret wrote:
On Tuesday 16 Mar 2021 at 12:53:53 (+), Quentin Perret wrote:
On Tuesday 16 Mar 2021 at 13:28:42 (+0100), Mate Toth-Pal wrote:
Changing
On 2021-03-16 15:29, Quentin Perret wrote:
On Tuesday 16 Mar 2021 at 12:53:53 (+), Quentin Perret wrote:
On Tuesday 16 Mar 2021 at 13:28:42 (+0100), Mate Toth-Pal wrote:
Changing the value of MT_S2_FWB_NORMAL to 7 would change this behavior, and
the resulting memory type would be device
(_kvm.lock);
ret = kvm_pgtable_stage2_find_range(_kvm.pgt, addr, prot,
);
Best regards,
Mate Toth-Pal
mmu);
params->vtcr = host_kvm.arch.vtcr;
params->hcr_el2 |= HCR_VM;
+ if (cpus_have_const_cap(ARM64_HAS_STAGE2_FWB))
+ params->hcr_el2 |= HCR_FWB;
__flush_dcache_area(params, sizeof(*params));
}
Best regards,
Mate Toth-Pal
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