Added reads after writes to flush writes to device
Added set_desc ops to IMS msi domain ops
Tested the IMS infrastructure with the IDXD driver]
Reviewed-by: Tony Luck
Signed-off-by: Thomas Gleixner
Signed-off-by: Megha Dey
---
drivers/irqchip/Kconfig | 14
-by: Dave Jiang
Signed-off-by: Megha Dey
---
include/linux/msi.h | 2 ++
kernel/irq/msi.c| 44
2 files changed, 46 insertions(+)
diff --git a/include/linux/msi.h b/include/linux/msi.h
index 24abec0..d60a6ba 100644
--- a/include/linux/msi.h
+++ b
outside of the IOMMU subsystem, where it could be used with other known
means (CPUID, smbios) to sense whether Linux is running in a virtualized
environment. Add a capability bit so that it could be used there.
Cc: Joerg Roedel
Reviewed-by: Tony Luck
Signed-off-by: Lu Baolu
Signed-off-by: Megha Dey
-by: Megha Dey
---
drivers/iommu/intel/irq_remapping.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/iommu/intel/irq_remapping.c
b/drivers/iommu/intel/irq_remapping.c
index 611ef52..2a55e54 100644
--- a/drivers/iommu/intel/irq_remapping.c
+++ b/drivers/iommu/intel
@nanos.tec.linutronix.de/
Link: https://lore.kernel.org/linux-pci/877dqrnzr3@nanos.tec.linutronix.de/
Link: https://lore.kernel.org/linux-pci/877dqqmc2h@nanos.tec.linutronix.de/
Reviewed-by: Tony Luck
Signed-off-by: Lu Baolu
Signed-off-by: Megha Dey
---
arch/x86/pci/common.c | 72
(introduced
in a later patch) and that data are not typically present in MSI entry.
Reviewed-by: Tony Luck
Signed-off-by: Megha Dey
---
include/linux/interrupt.h | 2 ++
include/linux/irq.h | 4
kernel/irq/manage.c | 32
3 files changed, 38 insertions
From: Thomas Gleixner
MSI interrupts have some common flags which should be set not only for
PCI/MSI interrupts.
Move the PCI/MSI flag setting into a common function so it can be reused.
Reviewed-by: Tony Luck
Signed-off-by: Thomas Gleixner
Signed-off-by: Megha Dey
---
drivers/pci/msi.c
MSI on
platform MSI, the better variant is to reimplement platform MSI on top of
device MSI.
Reviewed-by: Tony Luck
Signed-off-by: Thomas Gleixner
Signed-off-by: Megha Dey
---
drivers/base/platform-msi.c | 131
include/linux/irqdomain.h | 1
separate callbacks which operate on struct device. The resulting
storage information has to be stored in struct msi_desc so the underlying
irq chip implementation can retrieve it for the relevant operations.
Reviewed-by: Tony Luck
Signed-off-by: Thomas Gleixner
Signed-off-by: Megha Dey
---
include
iommu: Add capability IOMMU_CAP_VIOMMU_HINT
platform-msi: Add platform check for subdevice irq domain
Megha Dey (3):
genirq: Set auxiliary data for an interrupt
iommu/vt-d: Add DEV-MSI support
irqchip: Add IMS (Interrupt Message Store) driver
Thomas Gleixner (7):
x86/irq: Add DEV_MSI allocation t
-by: Thomas Gleixner
Signed-off-by: Megha Dey
---
kernel/irq/manage.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/kernel/irq/manage.c b/kernel/irq/manage.c
index dec3f73..85ede4e 100644
--- a/kernel/irq/manage.c
+++ b/kernel/irq/manage.c
@@ -443,16 +443,16 @@ int
From: Thomas Gleixner
For the upcoming device MSI support a new allocation type is
required.
Reviewed-by: Tony Luck
Signed-off-by: Thomas Gleixner
Signed-off-by: Megha Dey
---
arch/x86/include/asm/hw_irq.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/include/asm/hw_irq.h b
.
One arch specific function for MSI support is truly enough.
Reviewed-by: Tony Luck
Signed-off-by: Thomas Gleixner
Signed-off-by: Megha Dey
---
arch/x86/include/asm/msi.h | 4 +++-
arch/x86/kernel/apic/msi.c | 27 ---
drivers/pci/controller/pci-hyperv.c
From: Thomas Gleixner
For the upcoming device MSI support it's required to have a default
irq_chip::ack implementation (irq_chip_ack_parent) so the drivers do not
need to care.
Reviewed-by: Tony Luck
Signed-off-by: Thomas Gleixner
Signed-off-by: Megha Dey
---
drivers/base/platform-msi.c | 2
@nanos.tec.linutronix.de/
Link: https://lore.kernel.org/linux-pci/877dqrnzr3@nanos.tec.linutronix.de/
Link: https://lore.kernel.org/linux-pci/877dqqmc2h@nanos.tec.linutronix.de/
Signed-off-by: Lu Baolu
Signed-off-by: Megha Dey
---
arch/x86/pci/common.c | 74
MSI on
platform MSI, the better variant is to reimplement platform MSI on top of
device MSI.
Signed-off-by: Thomas Gleixner
Signed-off-by: Megha Dey
---
drivers/base/platform-msi.c | 131
include/linux/irqdomain.h | 1 +
include/linux/msi.h
separate callbacks which operate on struct device. The resulting
storage information has to be stored in struct msi_desc so the underlying
irq chip implementation can retrieve it for the relevant operations.
Signed-off-by: Thomas Gleixner
Signed-off-by: Megha Dey
---
include/linux/msi.h | 8
From: Thomas Gleixner
MSI interrupts have some common flags which should be set not only for
PCI/MSI interrupts.
Move the PCI/MSI flag setting into a common function so it can be reused.
Signed-off-by: Thomas Gleixner
Signed-off-by: Megha Dey
---
drivers/pci/msi.c | 7 +--
include
(introduced
in a later patch) and that data are not typically present in MSI entry.
Reviewed-by: Tony Luck
Signed-off-by: Megha Dey
---
include/linux/interrupt.h | 2 ++
include/linux/irq.h | 4
kernel/irq/manage.c | 32
3 files changed, 38 insertions
Signed-off-by: Megha Dey
---
kernel/irq/manage.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/kernel/irq/manage.c b/kernel/irq/manage.c
index dec3f73..85ede4e 100644
--- a/kernel/irq/manage.c
+++ b/kernel/irq/manage.c
@@ -443,16 +443,16 @@ int irq_update_affinity_desc
outside of the IOMMU subsystem, where it could be used with other known
means (CPUID, smbios) to sense whether Linux is running in a virtualized
environment. Add a capability bit so that it could be used there.
Signed-off-by: Lu Baolu
Signed-off-by: Megha Dey
---
drivers/iommu/amd/iommu.c| 2
of IMS_VECTOR_CTRL
Added reads after writes to flush writes to device
Added set_desc ops to IMS msi domain ops
Tested the IMS infrastructure with the IDXD driver]
Reviewed-by: Tony Luck
Signed-off-by: Thomas Gleixner
Signed-off-by: Megha Dey
---
drivers/irqchip/Kconfig
-by: Megha Dey
---
drivers/iommu/intel/irq_remapping.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/iommu/intel/irq_remapping.c
b/drivers/iommu/intel/irq_remapping.c
index 685200a..18f1b53 100644
--- a/drivers/iommu/intel/irq_remapping.c
+++ b/drivers/iommu/intel
.
One arch specific function for MSI support is truly enough.
Signed-off-by: Thomas Gleixner
Signed-off-by: Megha Dey
---
arch/x86/include/asm/msi.h | 4 +++-
arch/x86/kernel/apic/msi.c | 27 ---
drivers/pci/controller/pci-hyperv.c | 2 +-
include/linux
From: Thomas Gleixner
For the upcoming device MSI support a new allocation type is
required.
Signed-off-by: Thomas Gleixner
Signed-off-by: Megha Dey
---
arch/x86/include/asm/hw_irq.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/include/asm/hw_irq.h b/arch/x86/include/asm
From: Thomas Gleixner
For the upcoming device MSI support it's required to have a default
irq_chip::ack implementation (irq_chip_ack_parent) so the drivers do not
need to care.
Signed-off-by: Thomas Gleixner
Signed-off-by: Megha Dey
---
drivers/base/platform-msi.c | 2 ++
1 file changed, 2
rnel.org/linux-pci/20210106022749.2769057-1-baolu...@linux.intel.com/
Lu Baolu (2):
iommu: Add capability IOMMU_CAP_VIOMMU_HINT
platform-msi: Add platform check for subdevice irq domain
Megha Dey (2):
genirq: Set auxiliary data for an interrupt
iommu/vt-d: Add DEV-MSI support
Thomas Gleixner (8):
x8
From: Kyung Min Park
Add speed test for optimized GHASH computations with vectorized
instructions. Introduce a new test suite to calculate the speed
for this algorithm.
Signed-off-by: Kyung Min Park
Signed-off-by: Megha Dey
---
crypto/tcrypt.c | 5 +
1 file changed, 5 insertions(+)
diff
rk
Co-developed-by: Megha Dey
Signed-off-by: Megha Dey
---
arch/x86/crypto/Makefile |1 +
arch/x86/crypto/avx512_vaes_common.S | 1211 ++
arch/x86/crypto/ghash-clmulni-intel_avx512.S | 68 ++
arch/x86/crypto/ghash-clmulni-intel_glue.c
er/crc/crc16_t10dif_by16_10.asm
Co-developed-by: Greg Tucker
Signed-off-by: Greg Tucker
Co-developed-by: Tomasz Kantecki
Signed-off-by: Tomasz Kantecki
Signed-off-by: Kyung Min Park
Signed-off-by: Megha Dey
---
arch/x86/crypto/Makefile | 1 +
arch/x86/crypto/crct10dif-avx512-asm_64.S
s inspired by the AES GCM mode optimization published in
Intel Optimized IPSEC Cryptographic library.
https://github.com/intel/intel-ipsec-mb/blob/master/lib/avx512/gcm_vaes_avx512.asm
Co-developed-by: Tomasz Kantecki
Signed-off-by: Tomasz Kantecki
Signed-off-by: Megha Dey
---
arch/x86/crypt
This is a preparatory patch to introduce the optimized crypto algorithms
using AVX512 instructions which would require VAES and VPLCMULQDQ support.
Check for VAES and VPCLMULQDQ assembler support using AVX512 registers.
Cc: x...@kernel.org
Signed-off-by: Megha Dey
---
arch/x86
The if else block in aesni_init does not follow required coding
conventions. If other conditionals are added to the block, it
becomes very difficult to parse. Use the correct coding style
instead.
Signed-off-by: Megha Dey
---
arch/x86/crypto/aesni-intel_glue.c | 3 +--
1 file changed, 1
---
This work was inspired by the AES CTR mode optimization published
in Intel Optimized IPSEC Cryptographic library.
https://github.com/intel/intel-ipsec-mb/blob/master/lib/avx512/cntr_vaes_avx512.asm
Co-developed-by: Tomasz Kantecki
Signed-off-by: Tomasz Ka
on
crypto: ghash - Optimized GHASH computations
crypto: tcrypt - Add speed test for optimized GHASH computations
Megha Dey (4):
x86: Probe assembler capabilities for VAES and VPLCMULQDQ support
crypto: aesni - AES CTR x86_64 "by16" AVX512 optimization
crypto: aesni - fix coding styl
and was wondering why IMS is x86 sepcific. Perhaps we can
use this thread to discuss further on this.
Megha Dey (7):
genirq/msi: Differentiate between various MSI based interrupts
drivers/base: Introduce callbacks for IMS interrupt domain
x86/ims: Add support for a new IMS irq domain
irq_remapping
irq_alloc_info *);
Cc: Jacob Pan
Signed-off-by: Sanjay Kumar
Signed-off-by: Megha Dey
---
arch/x86/include/asm/irq_remapping.h | 13 +
drivers/iommu/intel_irq_remapping.c | 30 ++
drivers/iommu/irq_remapping.c| 9 +
drivers/iommu/irq_remapping.h
This patch adds support for the creation of a new IMS irq domain. It
creates a new irq_chip associated with the IMS domain and adds the
necessary domain operations to it.
Cc: Jacob Pan
Signed-off-by: Sanjay Kumar
Signed-off-by: Megha Dey
---
arch/x86/include/asm/msi.h | 4 ++
arch/x86
-by: Sanjay Kumar
Signed-off-by: Megha Dey
---
arch/x86/include/asm/pci.h | 4
arch/x86/include/asm/x86_init.h | 10 ++
arch/x86/kernel/apic/ims.c | 18 ++
arch/x86/kernel/x86_init.c | 23 +++
drivers/base/ims-msi.c | 34
of the code is
similar to platform-msi.c.
TODO: Conclude if ims-msi.c and platform-msi.c can be merged.
Cc: Jacob Pan
Signed-off-by: Sanjay Kumar
Signed-off-by: Megha Dey
---
drivers/base/Kconfig | 7
drivers/base/Makefile | 1 +
drivers/base/ims-msi.c | 94
Add the set_desc callback to the ims domain ops.
The set_desc callback is used to find a unique hwirq number from a given
domain.
Each mdev can have a maximum of 2048 IMS interrupts.
Cc: Jacob Pan
Signed-off-by: Sanjay Kumar
Signed-off-by: Megha Dey
---
arch/x86/kernel/apic/ims.c | 7
Since a device can support both MSI-X and IMS interrupts simultaneously,
do away with is_msix and introduce a new enum msi_desc_tag to
differentiate between the various types of msi_descs.
Signed-off-by: Megha Dey
---
arch/mips/pci/msi-xlp.c| 2 +-
arch/s390/pci/pci_irq.c| 2 +-
arch
This patch introduces APIs to allocate and free IMS interrupts.
Cc: Jacob Pan
Signed-off-by: Sanjay Kumar
Signed-off-by: Megha Dey
---
drivers/base/ims-msi.c | 216 +
include/linux/msi.h| 2 +
2 files changed, 218 insertions(+)
diff --git
On Sun, 2019-08-11 at 09:18 +0200, Thomas Gleixner wrote:
> On Tue, 6 Aug 2019, Megha Dey wrote:
>
> >
> > On Sat, 2019-06-29 at 10:08 +0200, Thomas Gleixner wrote:
> > >
> > > Megha,
> > >
> > > On Fri, 21 Jun 2019, Megha Dey wrote:
&
On Sun, 2019-08-11 at 09:20 +0200, Thomas Gleixner wrote:
> On Wed, 7 Aug 2019, Marc Zyngier wrote:
> >
> > On 07/08/2019 14:56, Thomas Gleixner wrote:
> > >
> > > On Tue, 6 Aug 2019, Megha Dey wrote:
> > > >
> > > >
On Wed, 2019-08-07 at 15:18 +0100, Marc Zyngier wrote:
> On 07/08/2019 14:56, Thomas Gleixner wrote:
> >
> > Megha,
> >
> > On Tue, 6 Aug 2019, Megha Dey wrote:
> > >
> > > On Sat, 2019-06-29 at 09:59 +0200, Thomas Gleixner wrote:
> >
On Wed, 2019-08-07 at 15:56 +0200, Thomas Gleixner wrote:
> Megha,
>
> On Tue, 6 Aug 2019, Megha Dey wrote:
> >
> > On Sat, 2019-06-29 at 09:59 +0200, Thomas Gleixner wrote:
> > >
> > > On Fri, 21 Jun 2019, Megha Dey wrote:
> > Totally agreed. The
On Thu, 2019-08-01 at 19:24 -0500, Bjorn Helgaas wrote:
> Hi Megha,
>
> On Fri, Jun 21, 2019 at 05:19:32PM -0700, Megha Dey wrote:
> >
> > Currently, MSI-X vector enabling and allocation for a PCIe device
> > is
> > static i.e. a device driver gets only on
On Sat, 2019-06-29 at 10:08 +0200, Thomas Gleixner wrote:
> Megha,
>
> On Fri, 21 Jun 2019, Megha Dey wrote:
> >
> > +static int free_msi_irqs_grp(struct pci_dev *dev, int group_id)
> > +{
> >
> > +
> > + for_each_pci_msi_entry(entry, dev) {
&g
On Sat, 2019-06-29 at 10:01 +0200, Thomas Gleixner wrote:
> Megha,
>
> On Fri, 21 Jun 2019, Megha Dey wrote:
> >
> >
> > +void default_teardown_msi_irqs_grp(struct pci_dev *dev, int
> > group_id)
> > +{
> > + int i;
> > + struct msi_desc
On Sat, 2019-06-29 at 09:59 +0200, Thomas Gleixner wrote:
> Megha,
>
> On Fri, 21 Jun 2019, Megha Dey wrote:
>
> >
> > Currently, MSI-X vector enabling and allocation for a PCIe device
> > is
> > static i.e. a device driver gets only one chance to enabl
This is a preparatory patch to introduce the dynamic allocation of
MSI-X vectors. In this patch, we add new structure members and macros
which will be consumed by the API that will dynamically allocate
MSI-X vectors.
Cc: Jacob Pan
Cc: Ashok Raj
Signed-off-by: Megha Dey
---
include/linux
This is a preparatory patch to introduce disabling of MSI-X vectors
belonging to a particular group. In this patch, we introduce a x86
specific mechanism to teardown the IRQ vectors belonging to a
particular group.
Cc: Jacob Pan
Cc: Ashok Raj
Signed-off-by: Megha Dey
---
arch/x86/include/asm
-off-by: Megha Dey
---
drivers/pci/msi.c | 12 +++-
drivers/pci/probe.c | 1 +
include/linux/pci.h | 9 +
3 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
index fd7fa6e..e947243 100644
--- a/drivers/pci/msi.c
+++ b/drivers/pci
Add Documentation for the newly introduced dynamic allocation
and deallocation of MSI-X vectors.
Cc: Jacob Pan
Cc: Ashok Raj
Signed-off-by: Megha Dey
---
Documentation/PCI/MSI-HOWTO.txt | 38 ++
1 file changed, 38 insertions(+)
diff --git a/Documentation
group, which can be called even if the device is not
being shut down. The pci_free_irq_vectors_grp() function provides this
type of interface.
The existing pci_free_irq_vectors() can be called along side this API.
Cc: Jacob Pan
Cc: Ashok Raj
Signed-off-by: Megha Dey
---
drivers/pci/msi.c
number associated with any
vector in a group, a new API pci_irq_vector_group() has been introduced.
Cc: Jacob Pan
Cc: Ashok Raj
Signed-off-by: Megha Dey
---
drivers/pci/msi.c | 203 +---
drivers/pci/probe.c | 8 +++
include/linux/pci.h | 37
are based out of Linux 5.2-rc5.
Megha Dey (6):
PCI/MSI: New structures/macros for dynamic MSI-X allocation
PCI/MSI: Dynamic allocation of MSI-X vectors by group
x86: Introduce the dynamic teardown function
PCI/MSI: Introduce new structure to manage MSI-x entries
PCI/MSI: Free MSI-X resources
. Instead everything runs in a single thread of
execution. You had suggested that the SIMD wrapper will defer the job to
the Kthread context, but I am not sure that will be done.
Please let me know what you think.
Signed-off-by: Megha Dey <megha@linux.intel.com>
---
arch/x86/crypto/s
. Instead everything runs in a single thread of
execution. You had suggested that the SIMD wrapper will defer the job to
the Kthread context, but I am not sure that will be done.
Please let me know what you think.
Signed-off-by: Megha Dey
---
arch/x86/crypto/sha1-mb/sha1_mb.c | 312
On Wed, 2017-12-20 at 13:23 -0800, Megha Dey wrote:
> On Wed, 2017-12-13 at 08:21 +0100, Peter Zijlstra wrote:
> > On Tue, Dec 12, 2017 at 03:08:00PM -0800, Megha Dey wrote:
> > > >
> > > > There's work on the way to allow multiple HW PMUs. You'll either have
On Wed, 2017-12-20 at 13:23 -0800, Megha Dey wrote:
> On Wed, 2017-12-13 at 08:21 +0100, Peter Zijlstra wrote:
> > On Tue, Dec 12, 2017 at 03:08:00PM -0800, Megha Dey wrote:
> > > >
> > > > There's work on the way to allow multiple HW PMUs. You'll either have
On Thu, 2018-01-18 at 22:39 +1100, Herbert Xu wrote:
> On Tue, Jan 09, 2018 at 04:09:04PM -0800, Megha Dey wrote:
> >
> > +static void mcryptd_skcipher_encrypt(struct crypto_async_request *base,
> > + int err)
On Thu, 2018-01-18 at 22:39 +1100, Herbert Xu wrote:
> On Tue, Jan 09, 2018 at 04:09:04PM -0800, Megha Dey wrote:
> >
> > +static void mcryptd_skcipher_encrypt(struct crypto_async_request *base,
> > + int err)
multi-buffer encryption build
support.
For an introduction to the multi-buffer implementation, please see
http://www.intel.com/content/www/us/en/communications/communications-ia-multi-buffer-paper.html
Originally-by: Chandramouli Narayanan <mouli_7...@yahoo.com>
Signed-off-by: Megha Dey
multi-buffer encryption build
support.
For an introduction to the multi-buffer implementation, please see
http://www.intel.com/content/www/us/en/communications/communications-ia-multi-buffer-paper.html
Originally-by: Chandramouli Narayanan
Signed-off-by: Megha Dey
Acked-by: Tim Chen
---
crypto
This patch introduces the assembly routine to do a by8 AES CBC
encryption in support of the AES CBC multi-buffer implementation.
It encrypts 8 data streams of the same key size simultaneously.
Originally-by: Chandramouli Narayanan <mouli_7...@yahoo.com>
Signed-off-by: Megha Dey
completed state.
Originally-by: Chandramouli Narayanan <mouli_7...@yahoo.com>
Signed-off-by: Megha Dey <megha@linux.intel.com>
Acked-by: Tim Chen <tim.c.c...@linux.intel.com>
---
arch/x86/crypto/aes-cbc-mb/aes_mb_mgr_init.c | 146
arch/x86/crypto/aes-cbc-mb/m
-by: Chandramouli Narayanan <mouli_7...@yahoo.com>
Signed-off-by: Megha Dey <megha@linux.intel.com>
Acked-by: Tim Chen <tim.c.c...@linux.intel.com>
---
arch/x86/crypto/Makefile| 1 +
arch/x86/crypto/aes-cbc-mb/Makefile | 22 +
arch/x86/crypto/aes-cbc-mb/
This patch introduces the assembly routine to do a by8 AES CBC
encryption in support of the AES CBC multi-buffer implementation.
It encrypts 8 data streams of the same key size simultaneously.
Originally-by: Chandramouli Narayanan
Signed-off-by: Megha Dey
Acked-by: Tim Chen
---
arch/x86
completed state.
Originally-by: Chandramouli Narayanan
Signed-off-by: Megha Dey
Acked-by: Tim Chen
---
arch/x86/crypto/aes-cbc-mb/aes_mb_mgr_init.c | 146
arch/x86/crypto/aes-cbc-mb/mb_mgr_inorder_x8_asm.S | 223 +++
arch/x86/crypto/aes-cbc-mb/mb_mgr_ooo_x8_asm.S
-by: Chandramouli Narayanan
Signed-off-by: Megha Dey
Acked-by: Tim Chen
---
arch/x86/crypto/Makefile| 1 +
arch/x86/crypto/aes-cbc-mb/Makefile | 22 +
arch/x86/crypto/aes-cbc-mb/aes_cbc_mb.c | 698
3 files changed, 721 insertions(+)
create mode 100644
<mouli_7...@yahoo.com>
Signed-off-by: Megha Dey <megha@linux.intel.com>
Acked-by: Tim Chen <tim.c.c...@linux.intel.com>
---
arch/x86/crypto/aes-cbc-mb/aes_cbc_mb_ctx.h| 97 +
arch/x86/crypto/aes-cbc-mb/aes_cbc_mb_mgr.h| 132
arch/x86
Signed-off-by: Megha Dey
Acked-by: Tim Chen
---
arch/x86/crypto/aes-cbc-mb/aes_cbc_mb_ctx.h| 97 +
arch/x86/crypto/aes-cbc-mb/aes_cbc_mb_mgr.h| 132
arch/x86/crypto/aes-cbc-mb/mb_mgr_datastruct.S | 271 +
arch/x86/crypto/aes-cbc-mb/reg_sizes.S
ablkcipher_walk helpers to walk the scatter gather list
and eliminated needs to modify blkcipher_walk for multibuffer cipher
v2
1. Update cpu feature check to make sure SSE is supported
2. Fix up unloading of aes-cbc-mb module to properly free memory
Megha Dey (5):
crypto: Multi-buffer encryption
ablkcipher_walk helpers to walk the scatter gather list
and eliminated needs to modify blkcipher_walk for multibuffer cipher
v2
1. Update cpu feature check to make sure SSE is supported
2. Fix up unloading of aes-cbc-mb module to properly free memory
Megha Dey (5):
crypto: Multi-buffer encryption
On Thu, 2017-08-03 at 13:27 +0800, Herbert Xu wrote:
> On Tue, Jul 25, 2017 at 07:09:58PM -0700, Megha Dey wrote:
> >
> > +/* notify the caller of progress ; request still stays in queue */
> > +
> > +static void notify_callback(struct mcryptd
On Thu, 2017-08-03 at 13:27 +0800, Herbert Xu wrote:
> On Tue, Jul 25, 2017 at 07:09:58PM -0700, Megha Dey wrote:
> >
> > +/* notify the caller of progress ; request still stays in queue */
> > +
> > +static void notify_callback(struct mcryptd
set to 0xff00 instead of 0xff.
This patch fixes the pmu_format_max_value() function to return the
correct maximum value.
Acked-by: Jiri Olsa <jo...@kernel.org>
Signed-off-by: Megha Dey <megha@linux.intel.com>
---
tools/perf/util/pmu.c | 8 +---
1 file changed, 1 insertion(
set to 0xff00 instead of 0xff.
This patch fixes the pmu_format_max_value() function to return the
correct maximum value.
Acked-by: Jiri Olsa
Signed-off-by: Megha Dey
---
tools/perf/util/pmu.c | 8 +---
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/tools/perf/util/pmu.c b/to
!= 0x80004145)
+ if (attr.config1 != 0x8000a145)
break;
if (attr.config2 != 0x040020041d07)
break;
Signed-off-by: Megha Dey <megha@linux.intel.com>
---
tools/perf/util/pmu.c | 2 ++
1 file changed, 2 insertions(+)
diff -
!= 0x80004145)
+ if (attr.config1 != 0x8000a145)
break;
if (attr.config2 != 0x040020041d07)
break;
Signed-off-by: Megha Dey
---
tools/perf/util/pmu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/tools/perf/util/pmu.c b
On Wed, 2017-12-13 at 08:21 +0100, Peter Zijlstra wrote:
> On Tue, Dec 12, 2017 at 03:08:00PM -0800, Megha Dey wrote:
> > >
> > > There's work on the way to allow multiple HW PMUs. You'll either have to
> > > wait for that or help in making that happen. What you do
On Wed, 2017-12-13 at 08:21 +0100, Peter Zijlstra wrote:
> On Tue, Dec 12, 2017 at 03:08:00PM -0800, Megha Dey wrote:
> > >
> > > There's work on the way to allow multiple HW PMUs. You'll either have to
> > > wait for that or help in making that happen. What you do
On Tue, 2017-12-12 at 23:32 +0100, Peter Zijlstra wrote:
> On Tue, Dec 12, 2017 at 01:10:57PM -0800, Megha Dey wrote:
> > On Mon, 2017-11-20 at 12:57 +0100, Peter Zijlstra wrote:
> > > On Fri, Nov 17, 2017 at 05:54:05PM -0800, Megha Dey wrote:
> > > > +
On Tue, 2017-12-12 at 23:32 +0100, Peter Zijlstra wrote:
> On Tue, Dec 12, 2017 at 01:10:57PM -0800, Megha Dey wrote:
> > On Mon, 2017-11-20 at 12:57 +0100, Peter Zijlstra wrote:
> > > On Fri, Nov 17, 2017 at 05:54:05PM -0800, Megha Dey wrote:
> > > > +
On Mon, 2017-11-20 at 12:57 +0100, Peter Zijlstra wrote:
> On Fri, Nov 17, 2017 at 05:54:05PM -0800, Megha Dey wrote:
> > + mutex_lock(_counter_mutex);
> > + for (i = 0; i < BM_MAX_COUNTERS; i++) {
> > + if (bm_counter_owner[i] == NULL) {
> > +
On Mon, 2017-11-20 at 12:57 +0100, Peter Zijlstra wrote:
> On Fri, Nov 17, 2017 at 05:54:05PM -0800, Megha Dey wrote:
> > + mutex_lock(_counter_mutex);
> > + for (i = 0; i < BM_MAX_COUNTERS; i++) {
> > + if (bm_counter_owner[i] == NULL) {
> > +
On Mon, 2017-11-20 at 15:07 +0100, Jiri Olsa wrote:
> On Fri, Nov 17, 2017 at 05:54:06PM -0800, Megha Dey wrote:
>
> SNIP
>
> > +IV. User-configurable inputs
> > +
> > +
> > +Several sysfs entries are provided in /sys/devices/
On Mon, 2017-11-20 at 15:07 +0100, Jiri Olsa wrote:
> On Fri, Nov 17, 2017 at 05:54:06PM -0800, Megha Dey wrote:
>
> SNIP
>
> > +IV. User-configurable inputs
> > +
> > +
> > +Several sysfs entries are provided in /sys/devices/
On Mon, 2017-11-20 at 15:10 +0100, Jiri Olsa wrote:
> On Fri, Nov 17, 2017 at 05:54:05PM -0800, Megha Dey wrote:
>
> SNIP
>
> > +/* Branch Monitoring default and mask values */
> > +#define BM_MAX_WINDOW_SIZE 0x3ff
> > +#define BM_MAX_THRESHOLD 0
On Mon, 2017-11-20 at 15:10 +0100, Jiri Olsa wrote:
> On Fri, Nov 17, 2017 at 05:54:05PM -0800, Megha Dey wrote:
>
> SNIP
>
> > +/* Branch Monitoring default and mask values */
> > +#define BM_MAX_WINDOW_SIZE 0x3ff
> > +#define BM_MAX_THRESHOLD 0
This patch adds the Documentation/x86/intel_bm.txt file with some
information about Intel Branch monitoring.
Signed-off-by: Megha Dey <megha@linux.intel.com>
---
Documentation/x86/intel_bm.txt | 216 +
1 file changed, 216 insertions(+)
creat
branch monitoring interrupts occurred during
the execution of the user-space application.
Signed-off-by: Yu-Cheng Yu <yu-cheng...@intel.com>
Signed-off-by: Megha Dey <megha@linux.intel.com>
---
arch/x86/events/Kconfig | 10 +
arch/x86/events/intel/Makefile | 2 +
arch/x86
This patch adds the Documentation/x86/intel_bm.txt file with some
information about Intel Branch monitoring.
Signed-off-by: Megha Dey
---
Documentation/x86/intel_bm.txt | 216 +
1 file changed, 216 insertions(+)
create mode 100644 Documentation/x86
branch monitoring interrupts occurred during
the execution of the user-space application.
Signed-off-by: Yu-Cheng Yu
Signed-off-by: Megha Dey
---
arch/x86/events/Kconfig | 10 +
arch/x86/events/intel/Makefile | 2 +
arch/x86/events/intel/bm.c
Add CPUID of Cannonlake (CNL) processors to Intel family list.
Signed-off-by: Megha Dey <megha@linux.intel.com>
---
arch/x86/include/asm/intel-family.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86/include/asm/intel-family.h
b/arch/x86/include/asm/intel-family.h
Add CPUID of Cannonlake (CNL) processors to Intel family list.
Signed-off-by: Megha Dey
---
arch/x86/include/asm/intel-family.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86/include/asm/intel-family.h
b/arch/x86/include/asm/intel-family.h
index 35a6bc4..056bd41 100644
_event' function when used
9. Removed the setting of event->count to 0 in event_init. This is
redundant as this is its default value
10. Do not allow threshold to be set as 0
Megha Dey (3):
x86/cpu/intel: Add Cannonlake to Intel family
perf/x86/intel/bm.c: Add Intel Branch Monitoring supp
_event' function when used
9. Removed the setting of event->count to 0 in event_init. This is
redundant as this is its default value
10. Do not allow threshold to be set as 0
Megha Dey (3):
x86/cpu/intel: Add Cannonlake to Intel family
perf/x86/intel/bm.c: Add Intel Branch Monitoring supp
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