On 2021-04-19 20:08, Bjorn Andersson wrote:
On Fri 26 Feb 03:55 CST 2021, Sai Prakash Ranjan wrote:
Adreno(GPU) SMMU and APSS(Application Processor SubSystem) SMMU
both implement "arm,mmu-500" in some QTI SoCs and to run through
adreno smmu specific implementation such as enab
ver reached because the current sequence checks
for apps smmu compatible(qcom,sc7280-smmu-500) first and runs that
specific impl and we never reach adreno smmu specific implementation.
Suggested-by: Akhil P Oommen
Signed-off-by: Sai Prakash Ranjan
Reviewed-by: Bjorn Andersson
Acked-by: Jordan Cro
:
* Add a comment to make sure this order is not changed in future (Jordan)
Sai Prakash Ranjan (2):
iommu/arm-smmu-qcom: Add SC7280 SMMU compatible
iommu/arm-smmu-qcom: Move the adreno smmu specific impl earlier
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 14 +++---
1 file changed
Add compatible for SC7280 SMMU to use the Qualcomm Technologies, Inc.
specific implementation.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
b/drivers/iommu/arm
Hi Guenter,
On 2021-03-11 01:53, Guenter Roeck wrote:
On Thu, Mar 11, 2021 at 01:50:04AM +0530, Sai Prakash Ranjan wrote:
During suspend/resume usecases and tests, it is common to see issues
such as lockups either in suspend path or resume path because of the
bugs in the corresponding device
On 2021-04-05 14:12, Sai Prakash Ranjan wrote:
Hi Bjorn,
On 2021-03-25 20:35, Will Deacon wrote:
On Thu, Mar 25, 2021 at 01:10:12PM +0530, Sai Prakash Ranjan wrote:
...
I think there is consensus on this series. I can resend if required
but it
still applies cleanly, let me know if you
Hi Bjorn,
On 2021-03-25 20:35, Will Deacon wrote:
On Thu, Mar 25, 2021 at 01:10:12PM +0530, Sai Prakash Ranjan wrote:
...
I think there is consensus on this series. I can resend if required
but it
still applies cleanly, let me know if you have any comments?
Please resend
Hi Bjorn,
On 2021-03-16 00:05, Sai Prakash Ranjan wrote:
This series enables various hardware blocks such as LLCC, IPCC, AOSS
QMP
and Coresight on SC7280 SoC.
Changes in v2:
* Rename qmp to power-controller (Stephen)
* Drop the ipcc mailbox dt-binding from this series and send
On 2021-03-30 19:02, Greg Kroah-Hartman wrote:
On Tue, Mar 30, 2021 at 06:18:43PM +0530, Sai Prakash Ranjan wrote:
On 2021-03-30 16:46, Greg Kroah-Hartman wrote:
> On Tue, Mar 30, 2021 at 03:25:58PM +0530, Sai Prakash Ranjan wrote:
> > On 2021-03-30 14:37, Greg Kroah-Hartman wrote:
>
On 2021-03-30 16:46, Greg Kroah-Hartman wrote:
On Tue, Mar 30, 2021 at 03:25:58PM +0530, Sai Prakash Ranjan wrote:
On 2021-03-30 14:37, Greg Kroah-Hartman wrote:
> On Tue, Mar 30, 2021 at 02:12:04PM +0530, Sandeep Maheswaram wrote:
> >
> > On 3/26/2021 7:07 PM, Greg Kroa
You know that we can not add callbacks for no in-kernel user, so what
good is this patch for now?
What in-kernel user? Since when does shutdown callback need an in-kernel
user? When you reboot or shutdown a system, it gets called. The reason
why the shutdown callback is needed is provided in t
Hi Will,
On 2021-03-15 00:31, Sai Prakash Ranjan wrote:
On 2021-03-12 04:59, Bjorn Andersson wrote:
On Sat 27 Feb 07:53 CST 2021, Sai Prakash Ranjan wrote:
Hi Bjorn,
On 2021-02-27 00:44, Bjorn Andersson wrote:
> On Fri 26 Feb 12:23 CST 2021, Rob Clark wrote:
>
>
> The current
Add IPCC compatible for SC7280 SoC.
Cc: Manivannan Sadhasivam
Cc: Jassi Brar
Signed-off-by: Sai Prakash Ranjan
Reviewed-by: Manivannan Sadhasivam
Reviewed-by: Stephen Boyd
---
Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git
Add a DT node for the AOSS QMP on SC7280 SoC.
Signed-off-by: Sai Prakash Ranjan
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 6c6fa4fa1b0f
Add coresight components found on SC7280 SoC.
Cc: Mathieu Poirier
Cc: Suzuki K Poulose
Cc: Mike Leach
Cc: Leo Yan
Signed-off-by: Sai Prakash Ranjan
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 489 +++
1 file changed, 489 insertions(+)
diff --git a/arch/arm64/boot/dts
Add a DT node for Last level cache (aka. system cache)
controller which provides control over the last level
cache present on SC7280 SoC.
Signed-off-by: Sai Prakash Ranjan
Reviewed-by: Stephen Boyd
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff
Add the IPCC DT node which is used to send and receive IPC
signals with remoteprocs for SC7280 SoC.
Cc: Manivannan Sadhasivam
Cc: Jassi Brar
Signed-off-by: Sai Prakash Ranjan
Reviewed-by: Manivannan Sadhasivam
Reviewed-by: Stephen Boyd
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 10
This series enables various hardware blocks such as LLCC, IPCC, AOSS QMP
and Coresight on SC7280 SoC.
Changes in v2:
* Rename qmp to power-controller (Stephen)
* Drop the ipcc mailbox dt-binding from this series and send it separately
* Collect review tags
Sai Prakash Ranjan (4):
arm64: dts
On 2021-03-11 22:04, Bjorn Andersson wrote:
On Thu 11 Mar 04:06 CST 2021, schow...@codeaurora.org wrote:
On 2021-03-11 04:49, Bjorn Andersson wrote:
> On Wed 10 Mar 10:46 CST 2021, Souradeep Chowdhury wrote:
>
> > The DCC is a DMA Engine designed to capture and store data
> > during system
On 2021-03-12 04:44, Bjorn Andersson wrote:
On Thu 25 Feb 03:30 CST 2021, Sai Prakash Ranjan wrote:
This series enables various hardware blocks such as LLCC, IPCC, AOSS
QMP
and Coresight on SC7280 SoC.
This series is dependent on the base support added for SC7280 in [1].
I've picked some
On 2021-03-12 04:59, Bjorn Andersson wrote:
On Sat 27 Feb 07:53 CST 2021, Sai Prakash Ranjan wrote:
Hi Bjorn,
On 2021-02-27 00:44, Bjorn Andersson wrote:
> On Fri 26 Feb 12:23 CST 2021, Rob Clark wrote:
>
>
> The current logic picks one of:
> 1) is the compa
On 2021-03-11 22:01, Bjorn Andersson wrote:
> On Thu 11 Mar 00:19 CST 2021, Sai Prakash Ranjan wrote:
>
>> Hi Bjorn,
>>
>> On 2021-03-11 04:49, Bjorn Andersson wrote:
>> > On Wed 10 Mar 10:46 CST 2021, Souradeep Chowdhury wrote:
>> >
>> > >
Hi Bjorn,
On 2021-03-11 04:49, Bjorn Andersson wrote:
On Wed 10 Mar 10:46 CST 2021, Souradeep Chowdhury wrote:
The DCC is a DMA Engine designed to capture and store data
during system crash or software triggers. The DCC operates
based on link list entries which provides it with data and
happen, move the watchdog pm to
use late/early system pm callbacks which will ensure that the watchdog
is suspended late and resumed early so that it can catch such issues.
Signed-off-by: Sai Prakash Ranjan
---
drivers/watchdog/qcom-wdt.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff
Hi Andi,
On 2021-03-09 20:14, Andi Kleen wrote:
The disk encryption is just one example and there might be others
which
we might not be aware of yet and we are not suspecting there is
something
wrong with the crypto code that needs to be fixed.
Then you don't have any leaks relating to
Hi,
On 2021-02-05 17:38, Sai Prakash Ranjan wrote:
On 2021-02-04 03:16, Will Deacon wrote:
On Tue, Feb 02, 2021 at 11:56:27AM +0530, Sai Prakash Ranjan wrote:
On 2021-02-01 23:50, Jordan Crouse wrote:
> On Mon, Feb 01, 2021 at 08:20:44AM -0800, Rob Clark wrote:
> > On Mon, Feb 1, 202
Hi Andi,
On 2021-03-05 01:47, Andi Kleen wrote:
> Andi Kleen writes:
>>
>> Normally disk encryption is in specialized work queues. It's total
>> overkill to restrict all of the kernel if you just want to restrict
>> those work queues.
>>
>> I would suggest some more analysis where secrets are
Hi Thomas,
> On Wed, Oct 28, 2020 at 12:58:41PM +0100, Thomas Gleixner wrote:
>
...
> Something like the completly untested below should work independent of
> config options.
>
> Thanks,
>
> tglx
> ---
> include/linux/irqdesc.h |4 ++
> kernel/irq/manage.c |3 +
>
Use the generic DT node name "power-controller" for AOSS message ram
instead of the protocol name QMP(Qualcomm Messaging Protocol) since
it is used for power management requests.
Suggested-by: Stephen Boyd
Signed-off-by: Sai Prakash Ranjan
---
arch/arm64/boot/dts/qcom/sc7180.dtsi
This short series converts the qmp DT node name to generic "power-controller"
for AOSS message ram instead of the protocol name QMP(Qualcomm Messaging
Protocol)
since it is used for power management requests.
Sai Prakash Ranjan (4):
arm64: dts: qcom: sc7180: Rename the qmp nod
Use the generic DT node name "power-controller" for AOSS message ram
instead of the protocol name QMP(Qualcomm Messaging Protocol) since
it is used for power management requests.
Suggested-by: Stephen Boyd
Signed-off-by: Sai Prakash Ranjan
---
arch/arm64/boot/dts/qcom/sm8350.dtsi
Use the generic DT node name "power-controller" for AOSS message ram
instead of the protocol name QMP(Qualcomm Messaging Protocol) since
it is used for power management requests.
Suggested-by: Stephen Boyd
Signed-off-by: Sai Prakash Ranjan
---
arch/arm64/boot/dts/qcom/sdm845.dtsi
Use the generic DT node name "power-controller" for AOSS message ram
instead of the protocol name QMP(Qualcomm Messaging Protocol) since
it is used for power management requests.
Suggested-by: Stephen Boyd
Signed-off-by: Sai Prakash Ranjan
---
arch/arm64/boot/dts/qcom/sm8250.dtsi
On 2021-03-02 04:13, Doug Anderson wrote:
Hi,
On Mon, Mar 1, 2021 at 11:05 AM Sai Prakash Ranjan
wrote:
On production systems with ETMs enabled, it is preferred to exclude
kernel mode(NS EL1) tracing for security concerns and support only
userspace(NS EL0) tracing. Perf subsystem interface
Hi
On 2021-03-02 04:13, Doug Anderson wrote:
Hi,
On Mon, Mar 1, 2021 at 11:05 AM Sai Prakash Ranjan
wrote:
Add a warning message to check CONFIG_EXCLUDE_KERNEL_HW_ITRACE kernel
config which excludes kernel mode instruction tracing to help perf
tool
users identify the perf event open
On 2021-03-02 04:13, Doug Anderson wrote:
Hi,
On Mon, Mar 1, 2021 at 11:05 AM Sai Prakash Ranjan
wrote:
On production systems with ETMs enabled, it is preferred to exclude
kernel mode(NS EL1) tracing for security concerns and support only
userspace(NS EL0) tracing. Perf subsystem interface
Prakash Ranjan
---
tools/perf/util/evsel.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c
index 1bf76864c4f2..3f584128a590 100644
--- a/tools/perf/util/evsel.c
+++ b/tools/perf/util/evsel.c
@@ -2672,7 +2672,8 @@ int
ikitin
Link:
https://lore.kernel.org/lkml/20201015124522.1876-1-saiprakash.ran...@codeaurora.org/
Signed-off-by: Sai Prakash Ranjan
---
init/Kconfig | 11 +++
kernel/events/core.c | 3 +++
2 files changed, 14 insertions(+)
diff --git a/init/Kconfig b/init/Kconfig
index 22946fe5ded9..34d9b7587d
and
userspace tracing enabled by default.
Tested-by: Denis Nikitin
Signed-off-by: Sai Prakash Ranjan
---
drivers/hwtracing/coresight/coresight-etm4x-core.c | 6 +-
drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 6 ++
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git
generic
config.
[1] https://lwn.net/Articles/796866/
Changes in v2:
* Move from kernel mode instruction tracing to all kernel level PMU tracing
(Peter)
* Move the check and warning to the caller mode_store() (Doug)
Sai Prakash Ranjan (4):
perf/core: Add support to exclude kernel mode PMU
and
userspace tracing enabled by default.
Signed-off-by: Sai Prakash Ranjan
---
drivers/hwtracing/coresight/coresight-etm3x-core.c | 3 +++
drivers/hwtracing/coresight/coresight-etm3x-sysfs.c | 6 ++
2 files changed, 9 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c
On 2021-02-27 00:15, Stephen Boyd wrote:
Quoting Sai Prakash Ranjan (2021-02-26 00:04:27)
On 2021-02-26 01:07, Stephen Boyd wrote:
> Quoting Sai Prakash Ranjan (2021-02-25 01:30:19)
>> Add a DT node for Last level cache (aka. system cache)
>> controller which provides contro
On 2021-02-27 00:16, Stephen Boyd wrote:
Quoting Sai Prakash Ranjan (2021-02-25 23:51:00)
On 2021-02-26 01:11, Stephen Boyd wrote:
> Quoting Sai Prakash Ranjan (2021-02-25 01:30:24)
>> Add a DT node for the AOSS QMP on SC7280 SoC.
>>
>> Signed-off-by: Sai Prakash Ranjan
Hi Bjorn,
On 2021-02-27 00:44, Bjorn Andersson wrote:
> On Fri 26 Feb 12:23 CST 2021, Rob Clark wrote:
>
>
> The current logic picks one of:
> 1) is the compatible mentioned in qcom_smmu_impl_of_match[]
> 2) is the compatible an adreno
> 3) no quirks needed
>
> The change flips the order of
Add compatible for SC7280 SMMU to use the Qualcomm Technologies, Inc.
specific implementation.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
b/drivers/iommu/arm
ver reached because the current sequence checks
for apps smmu compatible(qcom,sc7280-smmu-500) first and runs that
specific impl and we never reach adreno smmu specific implementation.
Suggested-by: Akhil P Oommen
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm/arm-smmu/arm-smmu-qco
Patch 1 adds the sc7280 smmu compatible.
Patch 2 moves the adreno smmu check before apss smmu to enable
adreno smmu specific implementation.
Changes in v2:
* Add a comment to make sure this order is not changed in future (Jordan)
Sai Prakash Ranjan (2):
iommu/arm-smmu-qcom: Add SC7280 SMMU
On 2021-02-25 23:36, Jordan Crouse wrote:
On Thu, Feb 25, 2021 at 03:54:10PM +0530, Sai Prakash Ranjan wrote:
Adreno(GPU) SMMU and APSS(Application Processor SubSystem) SMMU
both implement "arm,mmu-500" in some QTI SoCs and to run through
adreno smmu specific implementation such a
On 2021-02-26 01:07, Stephen Boyd wrote:
Quoting Sai Prakash Ranjan (2021-02-25 01:30:19)
Add a DT node for Last level cache (aka. system cache)
controller which provides control over the last level
cache present on SC7280 SoC.
Signed-off-by: Sai Prakash Ranjan
---
Reviewed-by: Stephen Boyd
On 2021-02-26 01:11, Stephen Boyd wrote:
Quoting Sai Prakash Ranjan (2021-02-25 01:30:24)
Add a DT node for the AOSS QMP on SC7280 SoC.
Signed-off-by: Sai Prakash Ranjan
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64
ver reached because the current sequence checks
for apps smmu compatible(qcom,sc7280-smmu-500) first and runs that
specific impl and we never reach adreno smmu specific implementation.
Suggested-by: Akhil P Oommen
Signed-off-by: Sai Prakash Ranjan
---
Its either this or we add a new compatible
Add compatible for SC7280 SMMU to use the Qualcomm Technologies, Inc.
specific implementation.
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
b/drivers/iommu/arm
Patch 1 adds the sc7280 smmu compatible.
Patch 2 moves the adreno smmu check before apss smmu to enable
adreno smmu specific implementation.
Sai Prakash Ranjan (2):
iommu/arm-smmu-qcom: Add SC7280 SMMU compatible
iommu/arm-smmu-qcom: Move the adreno smmu specific impl earlier
drivers/iommu
Add coresight components found on SC7280 SoC.
Cc: Mathieu Poirier
Cc: Suzuki K Poulose
Cc: Mike Leach
Cc: Leo Yan
Signed-off-by: Sai Prakash Ranjan
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 489 +++
1 file changed, 489 insertions(+)
diff --git a/arch/arm64/boot/dts
Add AOSS QMP support for SC7280 SoC.
Signed-off-by: Sai Prakash Ranjan
---
drivers/soc/qcom/qcom_aoss.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/soc/qcom/qcom_aoss.c b/drivers/soc/qcom/qcom_aoss.c
index 53acb9423bd6..934fcc4d2b05 100644
--- a/drivers/soc/qcom/qcom_aoss.c
Add IPCC compatible for SC7280 SoC.
Cc: Manivannan Sadhasivam
Signed-off-by: Sai Prakash Ranjan
---
Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
b/Documentation/devicetree
Add SC7280 AOSS QMP compatible to the list of possible bindings.
Signed-off-by: Sai Prakash Ranjan
---
Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt
b/Documentation
Add the IPCC DT node which is used to send and receive IPC
signals with remoteprocs for SC7280 SoC.
Cc: Manivannan Sadhasivam
Signed-off-by: Sai Prakash Ranjan
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom
Add a DT node for the AOSS QMP on SC7280 SoC.
Signed-off-by: Sai Prakash Ranjan
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 65c1e0f2fb56
Add LLCC configuration data for SC7280 SoC.
Signed-off-by: Sai Prakash Ranjan
---
drivers/soc/qcom/llcc-qcom.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
index 8403a77b59fe..15a36dcab990 100644
Add LLCC compatible for SC7280 SoC.
Signed-off-by: Sai Prakash Ranjan
---
Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml
b/Documentation/devicetree/bindings/arm/msm/qcom
Add a DT node for Last level cache (aka. system cache)
controller which provides control over the last level
cache present on SC7280 SoC.
Signed-off-by: Sai Prakash Ranjan
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts
This series enables various hardware blocks such as LLCC, IPCC, AOSS QMP
and Coresight on SC7280 SoC.
This series is dependent on the base support added for SC7280 in [1].
[1] https://lore.kernel.org/patchwork/cover/1379842/
Sai Prakash Ranjan (9):
dt-bindings: arm: msm: Add LLCC for SC7280
Hi,
Thanks for taking a look, comments inline.
On 2021-02-23 01:44, Doug Anderson wrote:
Hi,
On Fri, Jan 29, 2021 at 11:08 AM Sai Prakash Ranjan
wrote:
@@ -1202,6 +1207,13 @@ void etm4_config_trace_mode(struct etmv4_config
*config)
/* excluding kernel AND user space doesn't make
timer interrupt to be EL2 physical
timer interrupt (10 in this case).
Fixes: 60378f1a171e ("arm64: dts: qcom: sm8250: Add sm8250 dts file")
Signed-off-by: Sai Prakash Ranjan
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/
As per interrupt documentation for SM8350 SoC, the polarity
for level triggered PMU interrupt is low, fix this.
Fixes: b7e8f433a673 ("arm64: dts: qcom: Add basic devicetree support for SM8350
SoC")
Signed-off-by: Sai Prakash Ranjan
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 2
As per interrupt documentation for SM8250 SoC, the polarity
for level triggered PMU interrupt is low, fix this.
Fixes: 60378f1a171e ("arm64: dts: qcom: sm8250: Add sm8250 dts file")
Signed-off-by: Sai Prakash Ranjan
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +-
1 file changed, 1
Fix PMU interrupt polarity for SM8250 and SM8350 SoCs and the timer
interrupt property for SM8250 SoC.
Sai Prakash Ranjan (3):
arm64: dts: qcom: sm8250: Fix level triggered PMU interrupt polarity
arm64: dts: qcom: sm8350: Fix level triggered PMU interrupt polarity
arm64: dts: qcom: sm8250
Add ETM PID for Cortex-A78 to the list of supported ETMs.
Signed-off-by: Sai Prakash Ranjan
---
Changes in v2:
* Rebased on top of coresight/next from kernel.org coresight repo.
---
drivers/hwtracing/coresight/coresight-etm4x-core.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers
to linaro coresight repo,
https://git.linaro.org/kernel/coresight.git, I have now updated
the remote to a proper kernel.org coresight repo and will post
the updated patchset.
Thanks,
Sai
On Fri, 12 Feb 2021 at 17:23, Sai Prakash Ranjan
wrote:
Add ETM PIDs for Cortex-A55 and Cortex-A78
Add ETM PIDs for Cortex-A55 and Cortex-A78 to the list of
supported ETMs.
Signed-off-by: Sai Prakash Ranjan
---
drivers/hwtracing/coresight/coresight-etm4x-core.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c
b/drivers/hwtracing
Hi Peter,
On 2021-02-02 11:41, Sai Prakash Ranjan wrote:
Hi Peter,
On 2021-02-01 19:11, Peter Zijlstra wrote:
On Mon, Feb 01, 2021 at 01:11:04PM +0530, Sai Prakash Ranjan wrote:
Ok I suppose you mean CONFIG_SECURITY_LOCKDOWN_LSM? But I don't see
how this new config has to depend
size=4096 unmapped_size=4096
After:
map: IOMMU: dev=1d84000.ufshc iova=0x000fffa88000
paddr=0x0001063db000 size=4096
unmap: IOMMU: dev=1d84000.ufshc iova=0x000fffa88000 size=4096
unmapped_size=4096
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/iommu.c| 8
On 2021-02-04 03:16, Will Deacon wrote:
On Tue, Feb 02, 2021 at 11:56:27AM +0530, Sai Prakash Ranjan wrote:
On 2021-02-01 23:50, Jordan Crouse wrote:
> On Mon, Feb 01, 2021 at 08:20:44AM -0800, Rob Clark wrote:
> > On Mon, Feb 1, 2021 at 3:16 AM Will Deacon wrote:
> > > On
On 2021-02-01 23:50, Jordan Crouse wrote:
On Mon, Feb 01, 2021 at 08:20:44AM -0800, Rob Clark wrote:
On Mon, Feb 1, 2021 at 3:16 AM Will Deacon wrote:
>
> On Fri, Jan 29, 2021 at 03:12:59PM +0530, Sai Prakash Ranjan wrote:
> > On 2021-01-29 14:35, Will Deacon wrote:
> > >
On 2021-02-01 23:50, Jordan Crouse wrote:
On Mon, Feb 01, 2021 at 08:20:44AM -0800, Rob Clark wrote:
On Mon, Feb 1, 2021 at 3:16 AM Will Deacon wrote:
>
> On Fri, Jan 29, 2021 at 03:12:59PM +0530, Sai Prakash Ranjan wrote:
> > On 2021-01-29 14:35, Will Deacon wrote:
> > >
Hi Peter,
On 2021-02-01 19:11, Peter Zijlstra wrote:
On Mon, Feb 01, 2021 at 01:11:04PM +0530, Sai Prakash Ranjan wrote:
Ok I suppose you mean CONFIG_SECURITY_LOCKDOWN_LSM? But I don't see
how this new config has to depend on that? This can work independently
whether complete lockdown
Hi Peter,
On 2021-01-30 01:00, Peter Zijlstra wrote:
On Sat, Jan 30, 2021 at 12:35:10AM +0530, Sai Prakash Ranjan wrote:
Here the idea is to protect such important information from all users
including root users since root privileges does not have to mean full
control over the kernel [1
On 2021-01-31 22:33, Jorge Ramirez-Ortiz, Foundries wrote:
On 28/01/21, Sai Prakash Ranjan wrote:
On 2021-01-28 13:49, Jorge Ramirez-Ortiz, Foundries wrote:
> On 26/01/21, Sai Prakash Ranjan wrote:
> > As per register documentation, QCOM_WDT_ENABLE_IRQ which is BIT(1)
> > of w
kernel and
userspace tracing enabled by default.
Signed-off-by: Sai Prakash Ranjan
---
drivers/hwtracing/coresight/coresight-etm3x-core.c | 11 +++
drivers/hwtracing/coresight/coresight-etm3x-sysfs.c | 3 ++-
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/hwtracing
kernel and
userspace tracing enabled by default.
Tested-by: Denis Nikitin
Signed-off-by: Sai Prakash Ranjan
---
drivers/hwtracing/coresight/coresight-etm4x-core.c | 14 +-
.../hwtracing/coresight/coresight-etm4x-sysfs.c| 3 ++-
2 files changed, 15 insertions(+), 2 deletions(-)
diff
ing kernel mode for
ARM Coresight ETM{4,3}XX sysfs mode using the newly introduced generic
config.
[1] https://lwn.net/Articles/796866/
Sai Prakash Ranjan (4):
perf/core: Add support to exclude kernel mode instruction tracing
perf evsel: Print warning for excluding kernel mode instruction
: Al Grant
Tested-by: Denis Nikitin
Link:
https://lore.kernel.org/lkml/20201015124522.1876-1-saiprakash.ran...@codeaurora.org/
Signed-off-by: Sai Prakash Ranjan
---
init/Kconfig | 12
kernel/events/core.c | 6 ++
2 files changed, 18 insertions(+)
diff --git a/init/Kcon
Prakash Ranjan
---
tools/perf/util/evsel.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c
index c26ea82220bd..09cc0349f883 100644
--- a/tools/perf/util/evsel.c
+++ b/tools/perf/util/evsel.c
@@ -2630,7 +2630,8 @@ int
On 2021-01-28 13:49, Jorge Ramirez-Ortiz, Foundries wrote:
On 26/01/21, Sai Prakash Ranjan wrote:
As per register documentation, QCOM_WDT_ENABLE_IRQ which is BIT(1)
of watchdog control register is wakeup interrupt enable bit and
not related to bark interrupt at all, BIT(0) is used for that.
So
On 2021-01-28 07:03, Stephen Boyd wrote:
Quoting Sai Prakash Ranjan (2021-01-26 07:02:41)
As per register documentation, QCOM_WDT_ENABLE_IRQ which is BIT(1)
of watchdog control register is wakeup interrupt enable bit and
not related to bark interrupt at all, BIT(0) is used for that.
So remove
Hi Vinod,
On 2021-01-27 21:03, Vinod Koul wrote:
Hi Sai,
On 27-01-21, 18:37, Sai Prakash Ranjan wrote:
Hi Vinod,
On 2021-01-27 18:00, Vinod Koul wrote:
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts =
Hi Vinod,
On 2021-01-27 18:00, Vinod Koul wrote:
Add basic devicetree support for Qualcomm Technologies, Inc SM8350 SoC.
This adds gcc, pinctrl, reserved memory, uart, cpu nodes for this SoC.
Signed-off-by: Vinod Koul
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 499 +++
On 2021-01-26 20:53, Guenter Roeck wrote:
On 1/26/21 7:02 AM, Sai Prakash Ranjan wrote:
As per register documentation, QCOM_WDT_ENABLE_IRQ which is BIT(1)
of watchdog control register is wakeup interrupt enable bit and
not related to bark interrupt at all, BIT(0) is used for that.
So remove
Specify bark interrupt for APSS watchdog to support pre-timeout
notification on SDM845 SoC.
Signed-off-by: Sai Prakash Ranjan
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
Specify bark interrupt for APSS watchdog to support pre-timeout
notification on SM8150 SoC.
Signed-off-by: Sai Prakash Ranjan
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi
b/arch/arm64/boot/dts/qcom/sm8150.dtsi
Specify bark interrupt for APSS watchdog to support pre-timeout
notification on SM8250 SoC.
Signed-off-by: Sai Prakash Ranjan
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi
b/arch/arm64/boot/dts/qcom/sm8250.dtsi
This series adds pre-timeout notification support via bark
interrupt for SC7180, SDM845, SM8150, SM8250 SoCs.
Note: This has a functional dependency on [1] without which
the watchdog functionality would be broken.
[1] https://lore.kernel.org/patchwork/patch/1371266/
Sai Prakash Ranjan (4
Specify bark interrupt for APSS watchdog to support pre-timeout
notification on SC7180 SoC.
Signed-off-by: Sai Prakash Ranjan
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts/qcom/sc7180.dtsi
with this bit set and bark
interrupt specified, pre-timeout notification and/or watchdog
reset/bite does not occur.
Fixes: 36375491a439 ("watchdog: qcom: support pre-timeout when the bark irq is
available")
Cc: sta...@vger.kernel.org
Signed-off-by: Sai Prakash Ranjan
---
Reading the con
Hi Angelo,
On 2021-01-20 16:34, AngeloGioacchino Del Regno wrote:
Il 11/01/21 13:04, Sai Prakash Ranjan ha scritto:
A6XX GPUs have support for last level cache(LLC) also known
as system cache and need to set the bus attributes to
use it. Currently we use a generic adreno iommu address space
On 2021-01-20 21:48, Rob Clark wrote:
On Mon, Jan 11, 2021 at 4:04 AM Sai Prakash Ranjan
wrote:
A6XX GPUs have support for last level cache(LLC) also known
as system cache and need to set the bus attributes to
use it. Currently we use a generic adreno iommu address space
implementation which
+0530, Sai Prakash Ranjan wrote:
> >> Hello Mathieu, Suzuki
> >>
> >> On 2020-10-15 21:32, Mathieu Poirier wrote:
> >> > On Thu, Oct 15, 2020 at 06:15:22PM +0530, Sai Prakash Ranjan wrote:
> >> > > On production systems with ETMs enabled, it is preferr
On 2021-01-11 19:45, Sai Prakash Ranjan wrote:
commit ecd7274fb4cd ("iommu: Remove unused IOMMU_SYS_CACHE_ONLY flag")
removed unused IOMMU_SYS_CACHE_ONLY prot flag and along with it went
the memory type setting required for the non-coherent masters to use
system cache. Now that sy
Hi Al,
On 2021-01-19 17:26, Al Grant wrote:
From: Suzuki K Poulose
On 1/19/21 9:51 AM, Sai Prakash Ranjan wrote:
> Hi Al,
>
> On 2021-01-19 14:06, Al Grant wrote:
>> Hi Sai,
>>
>>> From: saiprakash.ranjan=codeaurora@mg.codeaurora.org
>>> Hi Mathie
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