Add QCOM cpufreq firmware device bindings for Qualcomm Technology Inc's
SoCs. This is required for managing the cpu frequency transitions which are
controlled by the hardware engine.
Signed-off-by: Taniya Das
---
.../bindings/cpufreq/cpufreq-qcom-hw.txt | 172 +
1
Hello Stephen,
On 12/13/2018 1:58 PM, Stephen Boyd wrote:
Quoting Taniya Das (2018-12-12 23:49:53)
diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt
b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt
new file mode 100644
index 000..2b82965
--- /dev
Add QCOM cpufreq firmware device bindings for Qualcomm Technology Inc's
SoCs. This is required for managing the cpu frequency transitions which are
controlled by the hardware engine.
Signed-off-by: Taniya Das
---
.../bindings/cpufreq/cpufreq-qcom-hw.txt | 172 +
1
The CPUfreq HW present in some QCOM chipsets offloads the steps necessary
for changing the frequency of CPUs. The driver implements the cpufreq
driver interface for this hardware engine.
Signed-off-by: Saravana Kannan
Signed-off-by: Stephen Boyd
Signed-off-by: Taniya Das
---
drivers/cpufreq
o for "qcom_cpu_resources_init".
* Removed ret = 0 from qcom_get_related_cpus and added to check for
cpu_mask_empty to return -ENOENT.
* Fixes qcom_cpu_resources_init function
* Remove initialization of 'index'
* Check for valid 'c'
* Removed initialization of 'prev_cc' from 'qcom_read_l
Hello Viresh,
On 12/12/2018 10:17 AM, Viresh Kumar wrote:
On 11-12-18, 19:05, Taniya Das wrote:
The design here assumes that there would not be any per-cpu/per-cluster
based SW requirement for the HW during frequency transitions, which again
makes me think that we would require to re-introduce
Hi Viresh,
Sorry for the delayed response. Thanks for the patch.
On 12/5/2018 11:46 AM, Viresh Kumar wrote:
On 05-12-18, 09:07, Taniya Das wrote:
Hello Stephen, Viresh
Thanks for the code and suggestions.
Having a NR_DOMAINS '2' makes the driver not scalable for re-use.
Sure, I didn't
The GCC lpass clocks are updated as protected, so clean up the ifdefers.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/gcc-sdm845.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c
index c782e62..ba8ff99 100644
--- a/drivers
The GCC lpass clocks are updated as protected, so clean up the ifdefers.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/gcc-sdm845.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c
index c782e62..ba8ff99 100644
--- a/drivers
This adds the low pass audio clock controller node to sdm845 based on
the example in the bindings.
Signed-off-by: Taniya Das
---
arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 4 +++-
arch/arm64/boot/dts/qcom/sdm845.dtsi| 8
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git
This adds the low pass audio clock controller node to sdm845 based on
the example in the bindings.
Signed-off-by: Taniya Das
---
arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 4 +++-
arch/arm64/boot/dts/qcom/sdm845.dtsi| 8
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git
shape. Thanks for your efforts..
On 02-12-18, 09:25, Taniya Das wrote:
+++ b/drivers/cpufreq/qcom-cpufreq-hw.c
+struct cpufreq_qcom {
+ struct cpufreq_frequency_table *table;
+ void __iomem *perf_state_reg;
+ cpumask_t related_cpus;
+};
+
+static struct cpufreq_qcom
shape. Thanks for your efforts..
On 02-12-18, 09:25, Taniya Das wrote:
+++ b/drivers/cpufreq/qcom-cpufreq-hw.c
+struct cpufreq_qcom {
+ struct cpufreq_frequency_table *table;
+ void __iomem *perf_state_reg;
+ cpumask_t related_cpus;
+};
+
+static struct cpufreq_qcom
Hello Viresh,
On 12/4/2018 10:42 AM, Viresh Kumar wrote:
Hi Taniya,
Sorry that I haven't been reviewing it much from last few iterations as I was
letting others get this into a better shape. Thanks for your efforts..
On 02-12-18, 09:25, Taniya Das wrote:
+++ b/drivers/cpufreq/qcom-cpufreq
Hello Viresh,
On 12/4/2018 10:42 AM, Viresh Kumar wrote:
Hi Taniya,
Sorry that I haven't been reviewing it much from last few iterations as I was
letting others get this into a better shape. Thanks for your efforts..
On 02-12-18, 09:25, Taniya Das wrote:
+++ b/drivers/cpufreq/qcom-cpufreq
Add QCOM cpufreq firmware device bindings for Qualcomm Technology Inc's
SoCs. This is required for managing the cpu frequency transitions which are
controlled by the hardware engine.
Signed-off-by: Taniya Das
---
.../bindings/cpufreq/cpufreq-qcom-hw.txt | 172 +
1
The CPUfreq HW present in some QCOM chipsets offloads the steps necessary
for changing the frequency of CPUs. The driver implements the cpufreq
driver interface for this hardware engine.
Signed-off-by: Saravana Kannan
Signed-off-by: Stephen Boyd
Signed-off-by: Taniya Das
---
drivers/cpufreq
Add QCOM cpufreq firmware device bindings for Qualcomm Technology Inc's
SoCs. This is required for managing the cpu frequency transitions which are
controlled by the hardware engine.
Signed-off-by: Taniya Das
---
.../bindings/cpufreq/cpufreq-qcom-hw.txt | 172 +
1
The CPUfreq HW present in some QCOM chipsets offloads the steps necessary
for changing the frequency of CPUs. The driver implements the cpufreq
driver interface for this hardware engine.
Signed-off-by: Saravana Kannan
Signed-off-by: Stephen Boyd
Signed-off-by: Taniya Das
---
drivers/cpufreq
rom qcom_get_related_cpus and added to check for
cpu_mask_empty to return -ENOENT.
* Fixes qcom_cpu_resources_init function
* Remove initialization of 'index'
* Check for valid 'c'
* Removed initialization of 'prev_cc' from 'qcom_read_lut'.
Taniya Das (2):
dt-bindings: cpufreq: Intr
rom qcom_get_related_cpus and added to check for
cpu_mask_empty to return -ENOENT.
* Fixes qcom_cpu_resources_init function
* Remove initialization of 'index'
* Check for valid 'c'
* Removed initialization of 'prev_cc' from 'qcom_read_lut'.
Taniya Das (2):
dt-bindings: cpufreq: Intr
Hello Stephen,
Thanks for the patch, I have updated the latest series with the patch
and few comments from Matthias.
On 11/21/2018 11:53 PM, Stephen Boyd wrote:
Quoting Taniya Das (2018-11-21 02:42:47)
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index d5ee456..789b2e0
Hello Stephen,
Thanks for the patch, I have updated the latest series with the patch
and few comments from Matthias.
On 11/21/2018 11:53 PM, Stephen Boyd wrote:
Quoting Taniya Das (2018-11-21 02:42:47)
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index d5ee456..789b2e0
Hello Matthias,
On 11/22/2018 12:11 AM, Matthias Kaehlcke wrote:
Hi Taniya,
thanks for respinning, a few nits inline.
On Wed, Nov 21, 2018 at 04:12:47PM +0530, Taniya Das wrote:
The CPUfreq HW present in some QCOM chipsets offloads the steps necessary
for changing the frequency of CPUs
Hello Matthias,
On 11/22/2018 12:11 AM, Matthias Kaehlcke wrote:
Hi Taniya,
thanks for respinning, a few nits inline.
On Wed, Nov 21, 2018 at 04:12:47PM +0530, Taniya Das wrote:
The CPUfreq HW present in some QCOM chipsets offloads the steps necessary
for changing the frequency of CPUs
Hello Matthias,
On 11/21/2018 11:32 PM, Matthias Kaehlcke wrote:
On Wed, Nov 21, 2018 at 04:12:46PM +0530, Taniya Das wrote:
Add QCOM cpufreq firmware device bindings for Qualcomm Technology Inc's
SoCs. This is required for managing the cpu frequency transitions which are
controlled
Hello Matthias,
On 11/21/2018 11:32 PM, Matthias Kaehlcke wrote:
On Wed, Nov 21, 2018 at 04:12:46PM +0530, Taniya Das wrote:
Add QCOM cpufreq firmware device bindings for Qualcomm Technology Inc's
SoCs. This is required for managing the cpu frequency transitions which are
controlled
Hello Rob,
On 11/27/2018 12:28 AM, Rob Herring wrote:
On Wed, Nov 21, 2018 at 10:02:36AM -0800, Matthias Kaehlcke wrote:
On Wed, Nov 21, 2018 at 04:12:46PM +0530, Taniya Das wrote:
Add QCOM cpufreq firmware device bindings for Qualcomm Technology Inc's
SoCs. This is required for managing
Hello Rob,
On 11/27/2018 12:28 AM, Rob Herring wrote:
On Wed, Nov 21, 2018 at 10:02:36AM -0800, Matthias Kaehlcke wrote:
On Wed, Nov 21, 2018 at 04:12:46PM +0530, Taniya Das wrote:
Add QCOM cpufreq firmware device bindings for Qualcomm Technology Inc's
SoCs. This is required for managing
Add protected-clocks list which could used to specify the clocks to be
bypassed on certain devices.
Reviewed-by: Rob Herring
Signed-off-by: Taniya Das
---
Documentation/devicetree/bindings/clock/qcom,gcc.txt | 14 ++
1 file changed, 14 insertions(+)
diff --git a/Documentation
Add protected-clocks list which could used to specify the clocks to be
bypassed on certain devices.
Reviewed-by: Rob Herring
Signed-off-by: Taniya Das
---
Documentation/devicetree/bindings/clock/qcom,gcc.txt | 14 ++
1 file changed, 14 insertions(+)
diff --git a/Documentation
Add device tree bindings for Low Power Audio subsystem clock controller for
Qualcomm Technology Inc's SDM845 SoCs.
Reviewed-by: Rob Herring
Signed-off-by: Taniya Das
---
.../devicetree/bindings/clock/qcom,gcc.txt | 4 +++-
.../devicetree/bindings/clock/qcom,lpasscc.txt | 26
on the protected-clock flag. Also do not
gate these clocks if they are left unused, as the lpass clocks require
the global clock controller lpass clocks to be enabled before they are
accessed. Mark the GCC lpass clocks as CRITICAL, for the LPASS clock
access.
Signed-off-by: Taniya Das
---
drivers/clk/qcom
Add device tree bindings for Low Power Audio subsystem clock controller for
Qualcomm Technology Inc's SDM845 SoCs.
Reviewed-by: Rob Herring
Signed-off-by: Taniya Das
---
.../devicetree/bindings/clock/qcom,gcc.txt | 4 +++-
.../devicetree/bindings/clock/qcom,lpasscc.txt | 26
on the protected-clock flag. Also do not
gate these clocks if they are left unused, as the lpass clocks require
the global clock controller lpass clocks to be enabled before they are
accessed. Mark the GCC lpass clocks as CRITICAL, for the LPASS clock
access.
Signed-off-by: Taniya Das
---
drivers/clk/qcom
ious
domains of LPASS CC.
Add support for the lpass clock controller found on SDM845 based devices.
This would allow lpass peripheral loader drivers to control the clocks to
bring the subsystem out of reset.
Taniya Das (3):
dt-bindings: clock: Update GCC bindings for protected-clocks
dt-bind
ious
domains of LPASS CC.
Add support for the lpass clock controller found on SDM845 based devices.
This would allow lpass peripheral loader drivers to control the clocks to
bring the subsystem out of reset.
Taniya Das (3):
dt-bindings: clock: Update GCC bindings for protected-clocks
dt-bind
Hello Stephen,
On 11/29/2018 2:40 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-11-21 23:53:41)
diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c
index f133b7f..ba8ff99 100644
--- a/drivers/clk/qcom/gcc-sdm845.c
+++ b/drivers/clk/qcom/gcc-sdm845.c
@@ -3153,6
Hello Stephen,
On 11/29/2018 2:40 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-11-21 23:53:41)
diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c
index f133b7f..ba8ff99 100644
--- a/drivers/clk/qcom/gcc-sdm845.c
+++ b/drivers/clk/qcom/gcc-sdm845.c
@@ -3153,6
Hello Stephen,
On 11/27/2018 2:44 PM, Stephen Boyd wrote:
Quoting Taniya Das (2018-11-21 23:53:41)
+
+static struct clk_branch lpass_qdsp6ss_core_clk = {
+ .halt_reg = 0x20,
+ /* CLK_OFF would not toggle until LPASS is not out of reset */
Is this really "CLK_OFF won't t
Hello Stephen,
On 11/27/2018 2:44 PM, Stephen Boyd wrote:
Quoting Taniya Das (2018-11-21 23:53:41)
+
+static struct clk_branch lpass_qdsp6ss_core_clk = {
+ .halt_reg = 0x20,
+ /* CLK_OFF would not toggle until LPASS is not out of reset */
Is this really "CLK_OFF won't t
From: Amit Nischal
Add support for the graphics clock controller found on SDM845
based devices. This would allow graphics drivers to probe and
control their clocks.
Signed-off-by: Amit Nischal
Signed-off-by: Taniya Das
---
drivers/clk/qcom/Kconfig| 9 ++
drivers/clk/qcom/Makefile
From: Amit Nischal
Add support for the graphics clock controller found on SDM845
based devices. This would allow graphics drivers to probe and
control their clocks.
Signed-off-by: Amit Nischal
Signed-off-by: Taniya Das
---
drivers/clk/qcom/Kconfig| 9 ++
drivers/clk/qcom/Makefile
From: Amit Nischal
Add device tree bindings for graphics clock controller for
Qualcomm Technology Inc's SDM845 SoCs.
Signed-off-by: Amit Nischal
---
.../devicetree/bindings/clock/qcom,gpucc.txt | 18
include/dt-bindings/clock/qcom,gpucc-sdm845.h | 24
Changes in v4:
* Cleanup the GPUCC code to keep only the clocks which would be requested
from the GPU client SW.
* Clean up of code as well as header file clock IDs.
* Due to the above cleanup the patches to enable/disable clocks for GPU GDSC
requirement is not supported :
Changes in v4:
* Cleanup the GPUCC code to keep only the clocks which would be requested
from the GPU client SW.
* Clean up of code as well as header file clock IDs.
* Due to the above cleanup the patches to enable/disable clocks for GPU GDSC
requirement is not supported :
From: Amit Nischal
Add device tree bindings for graphics clock controller for
Qualcomm Technology Inc's SDM845 SoCs.
Signed-off-by: Amit Nischal
---
.../devicetree/bindings/clock/qcom,gpucc.txt | 18
include/dt-bindings/clock/qcom,gpucc-sdm845.h | 24
on the protected-clock flag. Also do not
gate these clocks if they are left unused, as the lpass clocks require
the global clock controller lpass clocks to be enabled before they are
accessed. Mark the GCC lpass clocks as CRITICAL, for the LPASS clock
access.
Signed-off-by: Taniya Das
---
drivers/clk/qcom
llow lpass peripheral loader drivers to control the clocks to
bring the subsystem out of reset.
Taniya Das (3):
dt-bindings: clock: Update GCC bindings for protected-clocks
dt-bindings: clock: Introduce QCOM LPASS clock bindings
clk: qcom: Add lpass clock controller driver for SDM845
.../device
Add protected-clocks list which could used to specify the clocks to be
bypassed on certain devices.
Signed-off-by: Taniya Das
---
Documentation/devicetree/bindings/clock/qcom,gcc.txt | 14 ++
1 file changed, 14 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom
llow lpass peripheral loader drivers to control the clocks to
bring the subsystem out of reset.
Taniya Das (3):
dt-bindings: clock: Update GCC bindings for protected-clocks
dt-bindings: clock: Introduce QCOM LPASS clock bindings
clk: qcom: Add lpass clock controller driver for SDM845
.../device
Add protected-clocks list which could used to specify the clocks to be
bypassed on certain devices.
Signed-off-by: Taniya Das
---
Documentation/devicetree/bindings/clock/qcom,gcc.txt | 14 ++
1 file changed, 14 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom
on the protected-clock flag. Also do not
gate these clocks if they are left unused, as the lpass clocks require
the global clock controller lpass clocks to be enabled before they are
accessed. Mark the GCC lpass clocks as CRITICAL, for the LPASS clock
access.
Signed-off-by: Taniya Das
---
drivers/clk/qcom
Add device tree bindings for Low Power Audio subsystem clock controller for
Qualcomm Technology Inc's SDM845 SoCs.
Signed-off-by: Taniya Das
---
.../devicetree/bindings/clock/qcom,gcc.txt | 4 +++-
.../devicetree/bindings/clock/qcom,lpasscc.txt | 26 ++
include
Add device tree bindings for Low Power Audio subsystem clock controller for
Qualcomm Technology Inc's SDM845 SoCs.
Signed-off-by: Taniya Das
---
.../devicetree/bindings/clock/qcom,gcc.txt | 4 +++-
.../devicetree/bindings/clock/qcom,lpasscc.txt | 26 ++
include
Hello Rob,
On 11/13/2018 5:49 AM, Rob Herring wrote:
On Sat, Nov 10, 2018 at 07:14:15AM +0530, Taniya Das wrote:
Add device tree bindings for Low Power Audio subsystem clock controller for
Qualcomm Technology Inc's SDM845 SoCs.
Signed-off-by: Taniya Das
---
.../devicetree/bindings/clock
Hello Rob,
On 11/13/2018 5:49 AM, Rob Herring wrote:
On Sat, Nov 10, 2018 at 07:14:15AM +0530, Taniya Das wrote:
Add device tree bindings for Low Power Audio subsystem clock controller for
Qualcomm Technology Inc's SDM845 SoCs.
Signed-off-by: Taniya Das
---
.../devicetree/bindings/clock
Hello Stephen,
On 11/22/2018 12:37 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-11-09 17:44:16)
diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c
index f133b7f..ba8ff99 100644
--- a/drivers/clk/qcom/gcc-sdm845.c
+++ b/drivers/clk/qcom/gcc-sdm845.c
@@ -3153,6
Hello Stephen,
On 11/22/2018 12:37 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-11-09 17:44:16)
diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c
index f133b7f..ba8ff99 100644
--- a/drivers/clk/qcom/gcc-sdm845.c
+++ b/drivers/clk/qcom/gcc-sdm845.c
@@ -3153,6
The CPUfreq HW present in some QCOM chipsets offloads the steps necessary
for changing the frequency of CPUs. The driver implements the cpufreq
driver interface for this hardware engine.
Signed-off-by: Saravana Kannan
Signed-off-by: Taniya Das
---
drivers/cpufreq/Kconfig.arm | 11
oved ret = 0 from qcom_get_related_cpus and added to check for
cpu_mask_empty to return -ENOENT.
* Fixes qcom_cpu_resources_init function
* Remove initialization of 'index'
* Check for valid 'c'
* Removed initialization of 'prev_cc' from 'qcom_read_lut'.
Taniya Das (2):
dt-b
Add QCOM cpufreq firmware device bindings for Qualcomm Technology Inc's
SoCs. This is required for managing the cpu frequency transitions which are
controlled by the hardware engine.
Signed-off-by: Taniya Das
---
.../bindings/cpufreq/cpufreq-qcom-hw.txt | 172 +
1
Add QCOM cpufreq firmware device bindings for Qualcomm Technology Inc's
SoCs. This is required for managing the cpu frequency transitions which are
controlled by the hardware engine.
Signed-off-by: Taniya Das
---
.../bindings/cpufreq/cpufreq-qcom-hw.txt | 172 +
1
The CPUfreq HW present in some QCOM chipsets offloads the steps necessary
for changing the frequency of CPUs. The driver implements the cpufreq
driver interface for this hardware engine.
Signed-off-by: Saravana Kannan
Signed-off-by: Taniya Das
---
drivers/cpufreq/Kconfig.arm | 11
oved ret = 0 from qcom_get_related_cpus and added to check for
cpu_mask_empty to return -ENOENT.
* Fixes qcom_cpu_resources_init function
* Remove initialization of 'index'
* Check for valid 'c'
* Removed initialization of 'prev_cc' from 'qcom_read_lut'.
Taniya Das (2):
dt-b
Hello Stephen,
On 11/5/2018 12:07 PM, Stephen Boyd wrote:
Quoting Amit Nischal (2018-08-12 23:33:07)
+
+static int gpu_cc_sdm845_probe(struct platform_device *pdev)
+{
+ struct regmap *regmap;
+ unsigned int value, mask;
+ int ret;
+
+ regmap = qcom_cc_map(pdev,
Hello Stephen,
On 11/5/2018 12:07 PM, Stephen Boyd wrote:
Quoting Amit Nischal (2018-08-12 23:33:07)
+
+static int gpu_cc_sdm845_probe(struct platform_device *pdev)
+{
+ struct regmap *regmap;
+ unsigned int value, mask;
+ int ret;
+
+ regmap = qcom_cc_map(pdev,
Hello Stephen,
On 11/5/2018 12:04 PM, Stephen Boyd wrote:
Quoting Amit Nischal (2018-08-12 23:33:04)
For some of the GDSCs, there is a requirement to enable/disable the
few clocks before turning on/off the gdsc power domain. Add support
for the same by specifying a list of clk_hw pointers per
Hello Stephen,
On 11/5/2018 12:04 PM, Stephen Boyd wrote:
Quoting Amit Nischal (2018-08-12 23:33:04)
For some of the GDSCs, there is a requirement to enable/disable the
few clocks before turning on/off the gdsc power domain. Add support
for the same by specifying a list of clk_hw pointers per
Hello Stephen,
Thanks for your comments.
On 11/4/2018 9:50 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-11-02 20:06:00)
Hello Stephen,
On 10/18/2018 5:02 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-10-11 04:36:01)
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
Hello Stephen,
Thanks for your comments.
On 11/4/2018 9:50 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-11-02 20:06:00)
Hello Stephen,
On 10/18/2018 5:02 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-10-11 04:36:01)
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
Hello Vinod,
On 11/9/2018 3:20 PM, Vinod Koul wrote:
Device tree node name are not supposed to have "_" in them so fix the
node name use of xo_board to xo-board
Fixes: 652f1813c113 ("clk: qcom: gcc: Add global clock controller driver for
QCS404")
Signed-off-by: Vinod Koul
---
Steve: RobH
Hello Vinod,
On 11/9/2018 3:20 PM, Vinod Koul wrote:
Device tree node name are not supposed to have "_" in them so fix the
node name use of xo_board to xo-board
Fixes: 652f1813c113 ("clk: qcom: gcc: Add global clock controller driver for
QCS404")
Signed-off-by: Vinod Koul
---
Steve: RobH
port for the lpass clock controller found on SDM845 based devices.
This would allow lpass peripheral loader drivers to control the clocks to
bring the subsystem out of reset.
Taniya Das (2):
dt-bindings: clock: Introduce QCOM LPASS clock bindings
clk: qcom: Add lpass clock controller driver for SD
Add device tree bindings for Low Power Audio subsystem clock controller for
Qualcomm Technology Inc's SDM845 SoCs.
Signed-off-by: Taniya Das
---
.../devicetree/bindings/clock/qcom,gcc.txt | 16 +
.../devicetree/bindings/clock/qcom,lpasscc.txt | 26
on the protected-clock flag. Also do not
gate these clocks if they are left unused, as the lpass clocks require
the global clock controller lpass clocks to be enabled before they are
accessed. Mark the GCC lpass clocks as CRITICAL, for the LPASS clock
access.
Signed-off-by: Taniya Das
---
drivers/clk/qcom
on the protected-clock flag. Also do not
gate these clocks if they are left unused, as the lpass clocks require
the global clock controller lpass clocks to be enabled before they are
accessed. Mark the GCC lpass clocks as CRITICAL, for the LPASS clock
access.
Signed-off-by: Taniya Das
---
drivers/clk/qcom
port for the lpass clock controller found on SDM845 based devices.
This would allow lpass peripheral loader drivers to control the clocks to
bring the subsystem out of reset.
Taniya Das (2):
dt-bindings: clock: Introduce QCOM LPASS clock bindings
clk: qcom: Add lpass clock controller driver for SD
Add device tree bindings for Low Power Audio subsystem clock controller for
Qualcomm Technology Inc's SDM845 SoCs.
Signed-off-by: Taniya Das
---
.../devicetree/bindings/clock/qcom,gcc.txt | 16 +
.../devicetree/bindings/clock/qcom,lpasscc.txt | 26
Thanks Stephen.
On 11/6/2018 10:46 PM, Stephen Boyd wrote:
Quoting Taniya Das (2018-11-02 20:16:20)
On 11/2/2018 10:08 PM, Stephen Boyd wrote:
Quoting Taniya Das (2018-10-28 00:35:40)
How about moving the QSPI clocks too under this qcom property? Later
could add the support?
Yes the plan
Thanks Stephen.
On 11/6/2018 10:46 PM, Stephen Boyd wrote:
Quoting Taniya Das (2018-11-02 20:16:20)
On 11/2/2018 10:08 PM, Stephen Boyd wrote:
Quoting Taniya Das (2018-10-28 00:35:40)
How about moving the QSPI clocks too under this qcom property? Later
could add the support?
Yes the plan
Thanks Stephen for adding Andy.
On 11/6/2018 4:51 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-11-05 02:35:17)
This adds the video clock controller node to sdm845 based on the examples
in the bindings.
Signed-off-by: Taniya Das
---
Did you mean to send "To:" Andy? Clk tree do
Thanks Stephen for adding Andy.
On 11/6/2018 4:51 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-11-05 02:35:17)
This adds the video clock controller node to sdm845 based on the examples
in the bindings.
Signed-off-by: Taniya Das
---
Did you mean to send "To:" Andy? Clk tree do
This adds the video clock controller node to sdm845 based on the examples
in the bindings.
Signed-off-by: Taniya Das
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
This adds the video clock controller node to sdm845 based on the examples
in the bindings.
Signed-off-by: Taniya Das
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
Hello Stephen,
On 11/2/2018 10:08 PM, Stephen Boyd wrote:
Quoting Taniya Das (2018-10-28 00:35:40)
Add support for the lpass clock controller found on SDM845 based devices.
This would allow lpass peripheral loader drivers to control the clocks to
bring the subsystem out of reset.
LPASS clocks
Hello Stephen,
On 11/2/2018 10:08 PM, Stephen Boyd wrote:
Quoting Taniya Das (2018-10-28 00:35:40)
Add support for the lpass clock controller found on SDM845 based devices.
This would allow lpass peripheral loader drivers to control the clocks to
bring the subsystem out of reset.
LPASS clocks
Hello Stephen,
On 10/18/2018 5:02 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-10-11 04:36:01)
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -121,6 +121,17 @@ config ARM_QCOM_CPUFREQ_KRYO
If in doubt, say N.
+config ARM_QCOM_CPUFREQ_HW
+ bool
Hello Stephen,
On 10/18/2018 5:02 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-10-11 04:36:01)
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -121,6 +121,17 @@ config ARM_QCOM_CPUFREQ_KRYO
If in doubt, say N.
+config ARM_QCOM_CPUFREQ_HW
+ bool
+ Chandan from Display Port team,
On 10/30/2018 10:03 PM, Stephen Boyd wrote:
Quoting Taniya Das (2018-10-29 23:01:44)
On 10/30/2018 12:13 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-10-28 03:34:55)
On 2018-10-19 16:04, Taniya Das wrote:
On 10/10/2018 2:04 AM, Stephen Boyd wrote
+ Chandan from Display Port team,
On 10/30/2018 10:03 PM, Stephen Boyd wrote:
Quoting Taniya Das (2018-10-29 23:01:44)
On 10/30/2018 12:13 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-10-28 03:34:55)
On 2018-10-19 16:04, Taniya Das wrote:
On 10/10/2018 2:04 AM, Stephen Boyd wrote
On 10/30/2018 12:13 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-10-28 03:34:55)
Hello Stephen,
On 2018-10-19 16:04, Taniya Das wrote:
Hello Stephen,
On 10/10/2018 2:04 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-10-09 06:57:47)
diff --git a/drivers/clk/qcom/dispcc-sdm845.c
b
On 10/30/2018 12:13 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-10-28 03:34:55)
Hello Stephen,
On 2018-10-19 16:04, Taniya Das wrote:
Hello Stephen,
On 10/10/2018 2:04 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-10-09 06:57:47)
diff --git a/drivers/clk/qcom/dispcc-sdm845.c
b
Hello Stephen,
On 2018-10-19 16:04, Taniya Das wrote:
Hello Stephen,
On 10/10/2018 2:04 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-10-09 06:57:47)
diff --git a/drivers/clk/qcom/dispcc-sdm845.c
b/drivers/clk/qcom/dispcc-sdm845.c
index 0cc4909..6d3136a 100644
--- a/drivers/clk/qcom
Hello Stephen,
On 2018-10-19 16:04, Taniya Das wrote:
Hello Stephen,
On 10/10/2018 2:04 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-10-09 06:57:47)
diff --git a/drivers/clk/qcom/dispcc-sdm845.c
b/drivers/clk/qcom/dispcc-sdm845.c
index 0cc4909..6d3136a 100644
--- a/drivers/clk/qcom
tree flag. Also do not gate
these clocks if they are left unused, as the lpass clocks require the
global clock controller lpass clocks to be enabled before they are
accessed. Mark the GCC lpass clocks as CRITICAL, for the LPASS clock
access.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/Kconfig
tree flag. Also do not gate
these clocks if they are left unused, as the lpass clocks require the
global clock controller lpass clocks to be enabled before they are
accessed. Mark the GCC lpass clocks as CRITICAL, for the LPASS clock
access.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/Kconfig
ames to differentiate various
domains of LPASS CC.
Add support for the lpass clock controller found on SDM845 based devices.
This would allow lpass peripheral loader drivers to control the clocks to
bring the subsystem out of reset.
*** BLURB HERE ***
Taniya Das (1):
clk: qcom: Add lpass clock contro
ames to differentiate various
domains of LPASS CC.
Add support for the lpass clock controller found on SDM845 based devices.
This would allow lpass peripheral loader drivers to control the clocks to
bring the subsystem out of reset.
*** BLURB HERE ***
Taniya Das (1):
clk: qcom: Add lpass clock contro
On 10/17/2018 7:50 PM, Stephen Boyd wrote:
Quoting Taniya Das (2018-10-17 05:04:10)
On 10/17/2018 5:07 PM, Taniya Das wrote:
Hello Stephen,
On 10/12/2018 11:05 PM, Stephen Boyd wrote:
Quoting Taniya Das (2018-10-09 23:12:27)
On 10/10/2018 2:22 AM, Stephen Boyd wrote:
Quoting Taniya
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