Hi Andy
On 3/10/2020 2:11 am, Andy Shevchenko wrote:
> On Fri, Oct 02, 2020 at 03:04:27PM +0800, Rahul Tanwar wrote:
>> PVT controller (MR75203) is used to configure & control
>> Moortec embedded analog IP which contains temprature
>> sensor(TS), voltage monitor(VM) & process detector(PD)
>>
Hi Guenter,
On 2/10/2020 2:26 am, Guenter Roeck wrote:
> On 9/29/20 1:59 AM, Rahul Tanwar wrote:
>> PVT controller (MR75203) is used to configure & control
>> Moortec embedded analog IP which contains temprature
>> sensor(TS), voltage monitor(VM) & process detector(PD)
>> modules. Add hardware
Hi Uwe,
Thanks for review & feedback.
On 24/9/2020 2:55 pm, Uwe Kleine-König wrote:
> Hello,
>
> (hhm Thierry already announced to have taken this patch, so my review is
> late.)
>
> On Tue, Sep 15, 2020 at 04:23:37PM +0800, Rahul Tanwar wrote:
>> Intel Lightning Mountain(LGM) SoC contains a
On 24/9/2020 3:12 pm, Thierry Reding wrote:
> On Thu, Sep 24, 2020 at 08:55:34AM +0200, Uwe Kleine-König wrote:
>> Hello,
>>
>> (hhm Thierry already announced to have taken this patch, so my review is
>> late.)
> There's also a build warning in linux-next caused by this patch, so I'm
> going to
On 10/9/2020 6:35 pm, Philipp Zabel wrote:
> On Wed, 2020-09-09 at 14:52 +0800, Rahul Tanwar wrote:
>> PVT controller (MR75203) is used to configure & control
>> Moortec embedded analog IP which contains temprature
>> sensor(TS), voltage monitor(VM) & process detector(PD)
>> modules. Add driver
On 10/9/2020 5:46 pm, Andy Shevchenko wrote:
> On Thu, Sep 10, 2020 at 03:27:11PM +0800, Tanwar, Rahul wrote:
>> On 9/9/2020 11:05 pm, Guenter Roeck wrote:
>>> On 9/8/20 11:52 PM, Rahul Tanwar wrote:
> ...
>
>>>> +static int pvt_get_regmap(struct p
Hi Andy,
Thanks for the review & feedback.
On 9/9/2020 6:33 pm, Andy Shevchenko wrote:
> On Wed, Sep 09, 2020 at 02:52:05PM +0800, Rahul Tanwar wrote:
>> PVT controller (MR75203) is used to configure & control
>> Moortec embedded analog IP which contains temprature
>> sensor(TS), voltage
Hi Andy,
On 24/8/2020 4:17 pm, Andy Shevchenko wrote:
> On Mon, Aug 24, 2020 at 11:36:37AM +0800, Rahul Tanwar wrote:
>> Intel Lightning Mountain(LGM) SoC contains a PWM fan controller.
>> This PWM controller does not have any other consumer, it is a
>> dedicated PWM controller for fan attached
Hi Andy,
On 21/8/2020 6:56 pm, Andy Shevchenko wrote:
> On Fri, Aug 21, 2020 at 05:32:11PM +0800, Rahul Tanwar wrote:
>> Intel Lightning Mountain(LGM) SoC contains a PWM fan controller.
>> This PWM controller does not have any other consumer, it is a
>> dedicated PWM controller for fan attached
On 20/8/2020 6:52 pm, Andy Shevchenko wrote:
> On Thu, Aug 20, 2020 at 12:50:46PM +0800, Rahul Tanwar wrote:
>> Intel Lightning Mountain(LGM) SoC contains a PWM fan controller.
>> This PWM controller does not have any other consumer, it is a
>> dedicated PWM controller for fan attached to the
Hi Andy,
On 20/8/2020 6:52 pm, Andy Shevchenko wrote:
> On Thu, Aug 20, 2020 at 12:50:46PM +0800, Rahul Tanwar wrote:
>> Intel Lightning Mountain(LGM) SoC contains a PWM fan controller.
>> This PWM controller does not have any other consumer, it is a
>> dedicated PWM controller for fan attached
Hi Andy,
On 19/8/2020 3:54 pm, Andy Shevchenko wrote:
> On Wed, Aug 19, 2020 at 7:18 AM Tanwar, Rahul
> wrote:
>>
>> Hi Andy,
>>
>> On 18/8/2020 4:38 pm, Andy Shevchenko wrote:
>>> On Tue, Aug 18, 2020 at 01:48:59PM +0800, Rahul Tanwar wrote:
>&g
Hi Andy,
On 18/8/2020 4:38 pm, Andy Shevchenko wrote:
> On Tue, Aug 18, 2020 at 01:48:59PM +0800, Rahul Tanwar wrote:
>> Patch 1 adds dt binding document in YAML format.
>> Patch 2 add PWM fan controller driver for LGM SoC.
>>
>> v7:
>> - Address code quality related review concerns.
>> -
Hi Rob,
On 1/8/2020 2:19 am, Rob Herring wrote:
> On Tue, Jul 28, 2020 at 04:52:12PM +0800, Rahul Tanwar wrote:
>> Intel's LGM(Lightning Mountain) SoC contains a PWM fan controller
>> which is only used to control the fan attached to the system. This
>> PWM controller does not have any other
Hi Uwe,
On 27/7/2020 3:01 pm, Uwe Kleine-König wrote:
> On Mon, Jul 27, 2020 at 02:04:56PM +0800, Tanwar, Rahul wrote:
>> Hi Uwe,
>>
>> On 24/7/2020 12:15 am, Uwe Kleine-König wrote:
>>> Hello,
>>>
>>> On Thu, Jul 23, 2020 at 03:44:18PM +0800, Ra
Hi Uwe,
On 24/7/2020 12:15 am, Uwe Kleine-König wrote:
> Hello,
>
> On Thu, Jul 23, 2020 at 03:44:18PM +0800, Rahul Tanwar wrote:
>> +static int lgm_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
>> + const struct pwm_state *state)
>> +{
>> +struct lgm_pwm_chip
Hi Uwe,
Thanks for the feedback.
On 14/7/2020 3:10 am, Uwe Kleine-König wrote:
> Hello,
>
> On Tue, Jun 30, 2020 at 03:55:32PM +0800, Rahul Tanwar wrote:
>> Intel Lightning Mountain(LGM) SoC contains a PWM fan controller.
>> This PWM controller does not have any other consumer, it is a
>>
Hi Uwe,
On 14/7/2020 3:10 am, Uwe Kleine-König wrote:
> Hello,
>
> On Tue, Jun 30, 2020 at 03:55:32PM +0800, Rahul Tanwar wrote:
>> Intel Lightning Mountain(LGM) SoC contains a PWM fan controller.
>> This PWM controller does not have any other consumer, it is a
>> dedicated PWM controller for
Hi Rob,
On 14/7/2020 12:46 am, Rob Herring wrote:
> On Tue, Jun 30, 2020 at 03:55:31PM +0800, Rahul Tanwar wrote:
>> Intel's LGM(Lightning Mountain) SoC contains a PWM fan controller
>> which is only used to control the fan attached to the system. This
>> PWM controller does not have any other
On 25/6/2020 1:58 pm, Uwe Kleine-König wrote:
> On Thu, Jun 25, 2020 at 12:23:54PM +0800, Tanwar, Rahul wrote:
>> Hi Philipp,
>>
>> On 18/6/2020 8:25 pm, Philipp Zabel wrote:
>>> Hi Rahul,
>>>
>>> On Thu, 2020-06-18 at 20:05 +0800, Rahul Tanw
Hi Uwe,
Thanks for your valuable feedback.
On 19/6/2020 2:02 pm, Uwe Kleine-König wrote:
> Hello Rahul,
>
> On Thu, Jun 18, 2020 at 08:05:13PM +0800, Rahul Tanwar wrote:
>> Intel Lightning Mountain(LGM) SoC contains a PWM fan controller.
>> This PWM controller does not have any other consumer,
Hi Philipp,
On 18/6/2020 8:25 pm, Philipp Zabel wrote:
> Hi Rahul,
>
> On Thu, 2020-06-18 at 20:05 +0800, Rahul Tanwar wrote:
>> Intel Lightning Mountain(LGM) SoC contains a PWM fan controller.
>> This PWM controller does not have any other consumer, it is a
>> dedicated PWM controller for fan
On 27/5/2020 5:15 pm, Andy Shevchenko wrote:
> On Wed, May 27, 2020 at 02:28:53PM +0800, Tanwar, Rahul wrote:
>> On 22/5/2020 4:56 pm, Uwe Kleine-König wrote:
>>> On Fri, May 22, 2020 at 03:41:59PM +0800, Rahul Tanwar wrote:
> ...
>
>>> I'm a unhappy to hav
Hi Uwe,
Thanks for review.
On 22/5/2020 4:56 pm, Uwe Kleine-König wrote:
> Hello,
>
> On Fri, May 22, 2020 at 03:41:59PM +0800, Rahul Tanwar wrote:
>> Add PWM controller driver for Intel's Lightning Mountain(LGM) SoC.
>>
>> Signed-off-by: Rahul Tanwar
>> ---
>> drivers/pwm/Kconfig |
Hi Stephen,
On 27/5/2020 10:10 am, Stephen Boyd wrote:
> Quoting Rahul Tanwar (2020-04-16 22:54:47)
>> diff --git a/drivers/clk/x86/clk-cgu.c b/drivers/clk/x86/clk-cgu.c
>> new file mode 100644
>> index ..802a7fa88535
>> --- /dev/null
>> +++ b/drivers/clk/x86/clk-cgu.c
>> @@ -0,0
On 6/5/2020 2:41 pm, Greg KH wrote:
> On Wed, May 06, 2020 at 12:49:57PM +0800, Tanwar, Rahul wrote:
>> On 5/5/2020 10:25 pm, Greg KH wrote:
>>> On Mon, May 04, 2020 at 04:03:52PM +0800, Rahul Tanwar wrote:
>>>> Lantiq serial driver/IP is reused for a x86
On 5/5/2020 10:25 pm, Greg KH wrote:
> On Mon, May 04, 2020 at 04:03:52PM +0800, Rahul Tanwar wrote:
>> Lantiq serial driver/IP is reused for a x86 based SoC as well.
>> Update the Kconfig accordingly.
>>
>> Signed-off-by: Rahul Tanwar
>> ---
>> drivers/tty/serial/Kconfig | 2 +-
>> 1 file
Hi Linus,
Thanks for taking time out to review.
On 5/10/2019 4:28 AM, Linus Walleij wrote:
>> +config PINCTRL_EQUILIBRIUM
>> + tristate "Generic pinctrl and GPIO driver for Intel Lightning
>> Mountain SoC"
>> + select PINMUX
>> + select PINCONF
>> + select GPIOLIB
>> +
Hi Mika,
On 13/9/2019 4:18 PM, Mika Westerberg wrote:
> On Thu, Sep 12, 2019 at 11:11:32AM +0100, Linus Walleij wrote:
>> Hi Rahul,
>>
>> thanks for your patches!
>>
>> On Thu, Sep 12, 2019 at 8:59 AM Rahul Tanwar
>> wrote:
>>
>>> This series is to add pinctrl & GPIO controller driver for a
Hi Andy,
Thanks for your comments. I agree & will address all your review concerns in
v2 except below mentioned points where i need more clarification.
On 12/9/2019 10:30 PM, Andy Shevchenko wrote:
>> +static const struct pin_config pin_cfg_type[] = {
>> +{"intel,pullup",
Hi Martin,
On 4/9/2019 2:53 AM, Martin Blumenstingl wrote:
My understanding is that if we do not use syscon, then there is no
point in using regmap because this driver uses simple 32 bit register
access. Can directly read/write registers using readl() & writel().
Would you agree ?
if there
Hi Martin,
On 3/9/2019 6:20 AM, Martin Blumenstingl wrote:
Hello,
I only noticed this patchset today and I don't have much time left.
Here's my initial impressions without going through the code in detail.
I'll continue my review in the next days (as time permits).
As with all other Intel
Hi Andy,
Thanks for your review comments.
On 28/8/2019 11:09 PM, Andy Shevchenko wrote:
On Wed, Aug 28, 2019 at 03:00:17PM +0800, Rahul Tanwar wrote:
From: rtanwar
Clock Generation Unit(CGU) is a new clock controller IP of a forthcoming
Intel network processor SoC. It provides programming
Hi Andy,
On 23/8/2019 8:56 PM, Andy Shevchenko wrote:
get_wallclock() and set_wallclock() are function pointers of platform_ops
which are initialized to mach_get_cmos_time() and mach_set_rtc_mmss()
at init time. Since adding a new platform to override these functions is
discouraged, so the
Hi Peter,
On 23/8/2019 5:03 PM, Peter Zijlstra wrote:
On Thu, Aug 22, 2019 at 01:35:44PM -0700, Luck, Tony wrote:
From: Tony Luck
One of the use cases for this processor is as a network
processor. So give it an "_NP" tag for now. Could be changed
later if it turns out to group with some
Hi Andy,
On 22/8/2019 9:04 PM, Andy Shevchenko wrote:
On Thu, Aug 22, 2019 at 05:26:33PM +0800, Tanwar, Rahul wrote:
On 22/8/2019 5:02 PM, Andy Shevchenko wrote:
On Thu, Aug 22, 2019 at 03:44:03PM +0800, Rahul Tanwar wrote:
Use a newly introduced optional "status" property of
On 22/8/2019 5:09 PM, Alexandre Belloni wrote:
On 22/08/2019 11:56:59+0300, Andy Shevchenko wrote:
On Thu, Aug 22, 2019 at 03:44:04PM +0800, Rahul Tanwar wrote:
Some products may not support MC146818 RTC CMOS device. Introduce a optional
'status' standard property for RTC-CMOS to indicate if
Hi Andy,
On 22/8/2019 5:02 PM, Andy Shevchenko wrote:
On Thu, Aug 22, 2019 at 03:44:03PM +0800, Rahul Tanwar wrote:
Use a newly introduced optional "status" property of "motorola,mc146818"
compatible DT node to determine if RTC is supported. Skip read/write from
RTC device only when this
Hi Thomas,
On 22/8/2019 12:47 AM, Andy Shevchenko wrote:
For DT we can actually avoid that completely. See below.
For ACPI not unfortunately as the stupid GSI mapping is hard coded.
The below works better for my case, so, if you are going with that
Tested-by: Andy Shevchenko
On 21/8/2019 4:34 PM, Thomas Gleixner wrote:
Secondly, this link is irrelevant. ioapic_dynirq_base has nothing to do
with virtual IRQ number 0. It's a boundary for the dynamic allocation of
virtual interrupt numbers so that the core allocator does not pick
interrupts out of the IOAPIC's fixed
On 20/8/2019 10:57 PM, Peter Zijlstra wrote:
On Tue, Aug 20, 2019 at 12:48:05PM +, Luck, Tony wrote:
+#define INTEL_FAM6_ATOM_AIRMONT_NP0x75 /* Lightning Mountain */
What's _NP ?
Network Processor. But that is too narrow a descriptor. This is going to be
used in
other areas besides
On 16/8/2019 2:43 PM, Borislav Petkov wrote:
Now to another question: you see how I put my reply to the previous mail
*below* the quoted text. Why is yours ontop? Why not put it after mine
since you're replying to it, like it is usually done on the mailing
lists and thus not confuse the
Hi Boris,
Well noted, will have Tony in loop from now on. Thanks.
Regards,
Rahul
On 15/8/2019 8:22 PM, Borislav Petkov wrote:
On Thu, Aug 15, 2019 at 05:46:46PM +0800, Rahul Tanwar wrote:
This patch adds a new variant of Intel Atom Airmont CPU model used in a
network processor SoC named
Hi Thomas,
Thanks for your comments.
On 15/8/2019 6:31 PM, Thomas Gleixner wrote:
Rahul,
On Thu, 15 Aug 2019, Rahul Tanwar wrote:
Please use the proper prefix for your patches. x86 uses
x86/subsystem: not x86: subsystem:
Well noted.
This patch replaces direct values usage with
44 matches
Mail list logo
