On Tue, 2018-11-13 at 08:00 -0800, Nicolas Boichat wrote:
> On Mon, Nov 5, 2018 at 10:42 PM Weiyi Lu wrote:
> >
> > From: Owen Chen
> >
> > On both MT8183 & MT6765, there add "set/clr" register for
> > each clkmux setting, and one update regis
On Tue, 2018-11-13 at 08:00 -0800, Nicolas Boichat wrote:
> On Mon, Nov 5, 2018 at 10:42 PM Weiyi Lu wrote:
> >
> > From: Owen Chen
> >
> > On both MT8183 & MT6765, there add "set/clr" register for
> > each clkmux setting, and one update regis
On Tue, 2018-11-13 at 08:18 -0800, Nicolas Boichat wrote:
> On Mon, Nov 5, 2018 at 10:43 PM Weiyi Lu wrote:
> >
> > From: Owen Chen
> >
> > 1. pcwibits: The integer bits of pcw for plls is extend to 8 bits,
> >add a variable to indicate this change and
> &
On Tue, 2018-11-13 at 08:18 -0800, Nicolas Boichat wrote:
> On Mon, Nov 5, 2018 at 10:43 PM Weiyi Lu wrote:
> >
> > From: Owen Chen
> >
> > 1. pcwibits: The integer bits of pcw for plls is extend to 8 bits,
> >add a variable to indicate this change and
> &
On Tue, 2018-11-13 at 11:31 -0800, Nicolas Boichat wrote:
> (not a complete review...)
>
> On Mon, Nov 5, 2018 at 10:42 PM Weiyi Lu wrote:
> >
> > From: Owen Chen
> >
> > Both MT8183 & MT6765 add more bus protect node than previous project,
> > there
On Tue, 2018-11-13 at 11:31 -0800, Nicolas Boichat wrote:
> (not a complete review...)
>
> On Mon, Nov 5, 2018 at 10:42 PM Weiyi Lu wrote:
> >
> > From: Owen Chen
> >
> > Both MT8183 & MT6765 add more bus protect node than previous project,
> > there
On Tue, 2018-11-13 at 22:25 -0800, Nicolas Boichat wrote:
> On Mon, Nov 5, 2018 at 10:42 PM Weiyi Lu wrote:
> >
> > Add MT8183 clock support, include topckgen, apmixedsys,
> > infracfg, mcucfg and subsystem clocks.
> >
> > Signed-off-by: Weiyi Lu
> >
On Tue, 2018-11-13 at 22:25 -0800, Nicolas Boichat wrote:
> On Mon, Nov 5, 2018 at 10:42 PM Weiyi Lu wrote:
> >
> > Add MT8183 clock support, include topckgen, apmixedsys,
> > infracfg, mcucfg and subsystem clocks.
> >
> > Signed-off-by: Weiyi Lu
> >
On Tue, 2018-11-13 at 11:35 -0800, Nicolas Boichat wrote:
> On Mon, Nov 5, 2018 at 10:43 PM Weiyi Lu wrote:
> >
> > Add scpsys driver for MT8183
> >
> > Signed-off-by: Weiyi Lu
> > ---
> > drivers/soc/mediatek/mtk-scpsys.c | 226 +++
On Tue, 2018-11-13 at 11:35 -0800, Nicolas Boichat wrote:
> On Mon, Nov 5, 2018 at 10:43 PM Weiyi Lu wrote:
> >
> > Add scpsys driver for MT8183
> >
> > Signed-off-by: Weiyi Lu
> > ---
> > drivers/soc/mediatek/mtk-scpsys.c | 226 +++
From: Owen Chen
1. pcwibits: The integer bits of pcw for plls is extend to 8 bits,
add a variable to indicate this change and
backward-compatible.
2. fmin: The pll freqency lower-bound is vary from 1GMhz to
1.5Ghz, add a variable to indicate platform-dependent.
Signed-off-by: Owen Chen
From: Owen Chen
PLLs with tuner_en bit, such as APLL1, need to disable
tuner_en before apply new frequency settings, or the new frequency
settings (pcw) will not be applied.
The tuner_en bit will be disabled during changing PLL rate
and be restored after new settings applied.
Signed-off-by:
From: Owen Chen
1. pcwibits: The integer bits of pcw for plls is extend to 8 bits,
add a variable to indicate this change and
backward-compatible.
2. fmin: The pll freqency lower-bound is vary from 1GMhz to
1.5Ghz, add a variable to indicate platform-dependent.
Signed-off-by: Owen Chen
From: Owen Chen
PLLs with tuner_en bit, such as APLL1, need to disable
tuner_en before apply new frequency settings, or the new frequency
settings (pcw) will not be applied.
The tuner_en bit will be disabled during changing PLL rate
and be restored after new settings applied.
Signed-off-by:
On some Mediatek platforms, there are critical clocks of
clock gate type.
To register clock gate with flags CLK_IS_CRITICAL,
we need to add the flags field in mtk_gate data and register APIs.
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/clk-gate.c | 5 +++--
drivers/clk/mediatek/clk-gate.h
On some Mediatek platforms, there are critical clocks of
clock gate type.
To register clock gate with flags CLK_IS_CRITICAL,
we need to add the flags field in mtk_gate data and register APIs.
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/clk-gate.c | 5 +++--
drivers/clk/mediatek/clk-gate.h
lk_mux/mtk_mux struct in new file "clk-mux.c", "clk-mux.h".
Signed-off-by: Owen Chen
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/Makefile | 2 +-
drivers/clk/mediatek/clk-mux.c | 252 +
drivers/clk/mediatek/clk-mux.h | 101
Add scpsys driver for MT8183
Signed-off-by: Weiyi Lu
---
drivers/soc/mediatek/mtk-scpsys.c | 226 ++
1 file changed, 226 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c
b/drivers/soc/mediatek/mtk-scpsys.c
index 80be2e05e4e0..57b9f04a69de 100644
Add scpsys driver for MT8183
Signed-off-by: Weiyi Lu
---
drivers/soc/mediatek/mtk-scpsys.c | 226 ++
1 file changed, 226 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c
b/drivers/soc/mediatek/mtk-scpsys.c
index 80be2e05e4e0..57b9f04a69de 100644
lk_mux/mtk_mux struct in new file "clk-mux.c", "clk-mux.h".
Signed-off-by: Owen Chen
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/Makefile | 2 +-
drivers/clk/mediatek/clk-mux.c | 252 +
drivers/clk/mediatek/clk-mux.h | 101
Add MT8183 clock support, include topckgen, apmixedsys,
infracfg, mcucfg and subsystem clocks.
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/Kconfig | 75 ++
drivers/clk/mediatek/Makefile | 12 +
drivers/clk/mediatek/clk-mt8183-audio.c| 112 ++
drivers/clk
Add MT8183 clock support, include topckgen, apmixedsys,
infracfg, mcucfg and subsystem clocks.
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/Kconfig | 75 ++
drivers/clk/mediatek/Makefile | 12 +
drivers/clk/mediatek/clk-mt8183-audio.c| 112 ++
drivers/clk
fix incorrect IC name that will affect the MT8183 power dt-bindings
Signed-off-by: Weiyi Lu
---
include/dt-bindings/power/mt8173-power.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/dt-bindings/power/mt8173-power.h
b/include/dt-bindings/power/mt8173-power.h
Add MT8183 clock dt-bindings, include topckgen, apmixedsys,
infracfg, mcucfg and subsystem clocks.
Signed-off-by: Weiyi Lu
Reviewed-by: Rob Herring
---
include/dt-bindings/clock/mt8183-clk.h | 421 +
1 file changed, 421 insertions(+)
create mode 100644 include/dt
This patch adds the binding documentation for apmixedsys, audiosys,
camsys, imgsys, infracfg, mcucfg, mfgcfg, mmsys, topckgen, vdecsys,
vencsys and ipu for Mediatek MT8183.
Signed-off-by: Weiyi Lu
Reviewed-by: Rob Herring
---
.../arm/mediatek/mediatek,apmixedsys.txt | 1 +
.../bindings
This series is based on v4.20-rc1 and most of changes are
extracted from series below
(clock/scpsys common changes for both MT8183 & MT6765)
https://patchwork.kernel.org/patch/10528495/
(clock support of MT8183)
https://patchwork.kernel.org/patch/10549891/
The whole series is composed of
clock
mtk_pll_data
clk: mediatek: Disable tuner_en before change PLL rate
soc: mediatek: add new flow for mtcmos power.
Weiyi Lu (7):
dt-bindings: ARM: Mediatek: Document bindings for MT8183
clk: mediatek: Add dt-bindings for MT8183 clocks
clk: mediatek: Add flags support for mtk_gate data
c
do clock and internal isolation while power on/off sram.
We add a flag "sram_iso_ctrl" in scp_domain_data to judge if we need to
do the extra sram isolation control or not.
Signed-off-by: Owen Chen
Signed-off-by: Mars Cheng
Signed-off-by: Weiyi Lu
---
drivers/soc/mediatek/Makefi
fix incorrect IC name that will affect the MT8183 power dt-bindings
Signed-off-by: Weiyi Lu
---
include/dt-bindings/power/mt8173-power.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/dt-bindings/power/mt8173-power.h
b/include/dt-bindings/power/mt8173-power.h
Add MT8183 clock dt-bindings, include topckgen, apmixedsys,
infracfg, mcucfg and subsystem clocks.
Signed-off-by: Weiyi Lu
Reviewed-by: Rob Herring
---
include/dt-bindings/clock/mt8183-clk.h | 421 +
1 file changed, 421 insertions(+)
create mode 100644 include/dt
This patch adds the binding documentation for apmixedsys, audiosys,
camsys, imgsys, infracfg, mcucfg, mfgcfg, mmsys, topckgen, vdecsys,
vencsys and ipu for Mediatek MT8183.
Signed-off-by: Weiyi Lu
Reviewed-by: Rob Herring
---
.../arm/mediatek/mediatek,apmixedsys.txt | 1 +
.../bindings
This series is based on v4.20-rc1 and most of changes are
extracted from series below
(clock/scpsys common changes for both MT8183 & MT6765)
https://patchwork.kernel.org/patch/10528495/
(clock support of MT8183)
https://patchwork.kernel.org/patch/10549891/
The whole series is composed of
clock
mtk_pll_data
clk: mediatek: Disable tuner_en before change PLL rate
soc: mediatek: add new flow for mtcmos power.
Weiyi Lu (7):
dt-bindings: ARM: Mediatek: Document bindings for MT8183
clk: mediatek: Add dt-bindings for MT8183 clocks
clk: mediatek: Add flags support for mtk_gate data
c
do clock and internal isolation while power on/off sram.
We add a flag "sram_iso_ctrl" in scp_domain_data to judge if we need to
do the extra sram isolation control or not.
Signed-off-by: Owen Chen
Signed-off-by: Mars Cheng
Signed-off-by: Weiyi Lu
---
drivers/soc/mediatek/Makefi
Add power dt-bindings for MT8183.
Signed-off-by: Weiyi Lu
---
.../bindings/soc/mediatek/scpsys.txt | 14 ++
include/dt-bindings/power/mt8183-power.h | 26 +++
2 files changed, 40 insertions(+)
create mode 100644 include/dt-bindings/power/mt8183-power.h
Add power dt-bindings for MT8183.
Signed-off-by: Weiyi Lu
---
.../bindings/soc/mediatek/scpsys.txt | 14 ++
include/dt-bindings/power/mt8183-power.h | 26 +++
2 files changed, 40 insertions(+)
create mode 100644 include/dt-bindings/power/mt8183-power.h
According to 3rd ECO design change,
1. Add new fixed factor clock of audio.
2. Add the parent clocks for audio clock mux.
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/clk-mt2712.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt2712.c
According to 3rd ECO design change,
1. Add new fixed factor clock of audio.
2. Add the parent clocks for audio clock mux.
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/clk-mt2712.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt2712.c
This series is based on v4.19-rc1.
Basically, it's for the 3rd ECO design change of MT2712.
And also add support for switching pll reference source
for some MT2712 projects.
*** BLURB HERE ***
Weiyi Lu (3):
dt-bindings: clock: add clock for MT2712
clk: mediatek: update clock driver of MT2712
Add new clock according to 3rd ECO design change.
It's the parent clock of audio clock mux.
Signed-off-by: Weiyi Lu
---
include/dt-bindings/clock/mt2712-clk.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/dt-bindings/clock/mt2712-clk.h
b/include/dt-bindings
This series is based on v4.19-rc1.
Basically, it's for the 3rd ECO design change of MT2712.
And also add support for switching pll reference source
for some MT2712 projects.
*** BLURB HERE ***
Weiyi Lu (3):
dt-bindings: clock: add clock for MT2712
clk: mediatek: update clock driver of MT2712
Add new clock according to 3rd ECO design change.
It's the parent clock of audio clock mux.
Signed-off-by: Weiyi Lu
---
include/dt-bindings/clock/mt2712-clk.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/dt-bindings/clock/mt2712-clk.h
b/include/dt-bindings
of all PLL with
property "mediatek,refclk" instead of the default source "clk26m".
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/clk-mt2712.c | 87 ++-
1 file changed, 68 insertions(+), 19 deletions(-)
diff --git a/drivers/clk/mediat
of all PLL with
property "mediatek,refclk" instead of the default source "clk26m".
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/clk-mt2712.c | 87 ++-
1 file changed, 68 insertions(+), 19 deletions(-)
diff --git a/drivers/clk/mediat
This series is based on v4.19-rc1.
Basically, it's for the 3rd ECO design change of MT2712.
And also add support for switching pll reference source
for some MT2712 projects.
This series is based on v4.19-rc1.
Basically, it's for the 3rd ECO design change of MT2712.
And also add support for switching pll reference source
for some MT2712 projects.
On Mon, 2018-03-12 at 15:03 +0800, Weiyi Lu wrote:
> This series is based on v4.16-rc1 and composed of scpsys control (PATCH 1-2)
> and clock control (PATCH 3-5).
> Basically, all changes are for the ECO design change of MT2712.
>
> changes since v1:
> - Avoid renumbering
On Mon, 2018-03-12 at 15:03 +0800, Weiyi Lu wrote:
> This series is based on v4.16-rc1 and composed of scpsys control (PATCH 1-2)
> and clock control (PATCH 3-5).
> Basically, all changes are for the ECO design change of MT2712.
>
> changes since v1:
> - Avoid renumbering
add new clocks according to ECO design change
Signed-off-by: Weiyi Lu <weiyi...@mediatek.com>
---
include/dt-bindings/clock/mt2712-clk.h | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/include/dt-bindings/clock/mt2712-clk.h
b/include/dt-bindings/clock/
add new clocks according to ECO design change
Signed-off-by: Weiyi Lu
---
include/dt-bindings/clock/mt2712-clk.h | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/include/dt-bindings/clock/mt2712-clk.h
b/include/dt-bindings/clock/mt2712-clk.h
index 48a8e797a617
1. split MFG power domain into MFG/MFG_SC1/MFG_SC2/MFG_SC3
according to MT2712 ECO design change
2. add subdomain support for MT2712
Signed-off-by: Weiyi Lu <weiyi...@mediatek.com>
---
drivers/soc/mediatek/mtk-scpsys.c | 42 +--
1 file changed, 40 inse
add new clocks according to ECO design change
Signed-off-by: Weiyi Lu <weiyi...@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 28
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
b/arch/arm64/boot/dts/me
1. split MFG power domain into MFG/MFG_SC1/MFG_SC2/MFG_SC3
according to MT2712 ECO design change
2. add subdomain support for MT2712
Signed-off-by: Weiyi Lu
---
drivers/soc/mediatek/mtk-scpsys.c | 42 +--
1 file changed, 40 insertions(+), 2 deletions(-)
diff
add new clocks according to ECO design change
Signed-off-by: Weiyi Lu
---
arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 28
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index
Add new power domains(MFG_SC1/MFG_SC2/MFG_SC3)
for MT2712 according to ECO design change.
Signed-off-by: Weiyi Lu <weiyi...@mediatek.com>
Reviewed-by: Rob Herring <r...@kernel.org>
---
include/dt-bindings/power/mt2712-power.h | 3 +++
1 file changed, 3 insertions(+)
diff --git
Add new power domains(MFG_SC1/MFG_SC2/MFG_SC3)
for MT2712 according to ECO design change.
Signed-off-by: Weiyi Lu
Reviewed-by: Rob Herring
---
include/dt-bindings/power/mt2712-power.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/dt-bindings/power/mt2712-power.h
b/include/dt
According to ECO design change,
1. add new clock mux data and change some
2. add new clock gate data and clock factor data
3. change status register offset of infra subsystem
Signed-off-by: Weiyi Lu <weiyi...@mediatek.com>
---
drivers/clk/mediatek/clk-mt2712.
According to ECO design change,
1. add new clock mux data and change some
2. add new clock gate data and clock factor data
3. change status register offset of infra subsystem
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/clk-mt2712.c | 69 +++
1 file
This series is based on v4.16-rc1 and composed of scpsys control (PATCH 1-2)
and clock control (PATCH 3-5).
Basically, all changes are for the ECO design change of MT2712.
changes since v1:
- Avoid renumbering clocks. Append new clocks at the bottom of each own
subsystem.
Weiyi Lu (5):
dt
This series is based on v4.16-rc1 and composed of scpsys control (PATCH 1-2)
and clock control (PATCH 3-5).
Basically, all changes are for the ECO design change of MT2712.
changes since v1:
- Avoid renumbering clocks. Append new clocks at the bottom of each own
subsystem.
Weiyi Lu (5):
dt
This series is based on v4.16-rc1 and composed of scpsys control (PATCH 1-2)
and clock control (PATCH 3-5).
Basically, all changes are for the ECO design change of MT2712.
changes since v1:
- Avoid renumbering clocks. Append new clocks at the bottom of each own
subsystem.
Weiyi Lu (5):
dt
This series is based on v4.16-rc1 and composed of scpsys control (PATCH 1-2)
and clock control (PATCH 3-5).
Basically, all changes are for the ECO design change of MT2712.
changes since v1:
- Avoid renumbering clocks. Append new clocks at the bottom of each own
subsystem.
Weiyi Lu (5):
dt
On Thu, 2018-03-01 at 16:45 -0600, Rob Herring wrote:
> On Thu, Feb 22, 2018 at 01:48:49PM +0800, Weiyi Lu wrote:
> > add new clocks according to ECO design change
> >
> > Signed-off-by: Weiyi Lu <weiyi...@mediatek.com>
> > ---
> > inclu
On Thu, 2018-03-01 at 16:45 -0600, Rob Herring wrote:
> On Thu, Feb 22, 2018 at 01:48:49PM +0800, Weiyi Lu wrote:
> > add new clocks according to ECO design change
> >
> > Signed-off-by: Weiyi Lu
> > ---
> > include/dt-
Add new power domains(MFG_SC1/MFG_SC2/MFG_SC3)
for MT2712 according to ECO design change.
Signed-off-by: Weiyi Lu <weiyi...@mediatek.com>
---
include/dt-bindings/power/mt2712-power.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/dt-bindings/power/mt2712-power.h
b/incl
Add new power domains(MFG_SC1/MFG_SC2/MFG_SC3)
for MT2712 according to ECO design change.
Signed-off-by: Weiyi Lu
---
include/dt-bindings/power/mt2712-power.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/dt-bindings/power/mt2712-power.h
b/include/dt-bindings/power/mt2712
add new clocks according to ECO design change
Signed-off-by: Weiyi Lu <weiyi...@mediatek.com>
---
include/dt-bindings/clock/mt2712-clk.h | 294 +
1 file changed, 151 insertions(+), 143 deletions(-)
diff --git a/include/dt-bindings/clock/mt2712-clk.h
b/incl
add new clocks according to ECO design change
Signed-off-by: Weiyi Lu
---
include/dt-bindings/clock/mt2712-clk.h | 294 +
1 file changed, 151 insertions(+), 143 deletions(-)
diff --git a/include/dt-bindings/clock/mt2712-clk.h
b/include/dt-bindings/clock/mt2712
add new clocks according to ECO design change
Signed-off-by: Weiyi Lu <weiyi...@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 28
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
b/arch/arm64/boot/dts/me
add new clocks according to ECO design change
Signed-off-by: Weiyi Lu
---
arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 28
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index
This series is based on v4.16-rc1 and composed of scpsys control (PATCH 1-2)
and clock control (PATCH 3-5).
Basically, all changes are for the ECO design change of MT2712.
Weiyi Lu (5):
dt-bindings: soc: update MT2712 power dt-bindings
soc: mediatek: update power domain data of MT2712
dt
1. split MFG power domain into MFG/MFG_SC1/MFG_SC2/MFG_SC3
according to MT2712 ECO design change
2. add subdomain support for MT2712
Signed-off-by: Weiyi Lu <weiyi...@mediatek.com>
---
drivers/soc/mediatek/mtk-scpsys.c | 42 +--
1 file changed, 40 inse
This series is based on v4.16-rc1 and composed of scpsys control (PATCH 1-2)
and clock control (PATCH 3-5).
Basically, all changes are for the ECO design change of MT2712.
Weiyi Lu (5):
dt-bindings: soc: update MT2712 power dt-bindings
soc: mediatek: update power domain data of MT2712
dt
1. split MFG power domain into MFG/MFG_SC1/MFG_SC2/MFG_SC3
according to MT2712 ECO design change
2. add subdomain support for MT2712
Signed-off-by: Weiyi Lu
---
drivers/soc/mediatek/mtk-scpsys.c | 42 +--
1 file changed, 40 insertions(+), 2 deletions(-)
diff
This series is based on v4.16-rc1 and composed of scpsys control (PATCH 1-2)
and clock control (PATCH 3-5).
Basically, all changes are for the ECO design change of MT2712.
Weiyi Lu (5):
dt-bindings: soc: update MT2712 power dt-bindings
soc: mediatek: update power domain data of MT2712
dt
This series is based on v4.16-rc1 and composed of scpsys control (PATCH 1-2)
and clock control (PATCH 3-5).
Basically, all changes are for the ECO design change of MT2712.
Weiyi Lu (5):
dt-bindings: soc: update MT2712 power dt-bindings
soc: mediatek: update power domain data of MT2712
dt
According to ECO design change,
1. add new clock mux data and change some
2. add new clock gate data and clock factor data
3. change status register offset of infra subsystem
Signed-off-by: Weiyi Lu <weiyi...@mediatek.com>
---
drivers/clk/mediatek/clk-mt2712.
According to ECO design change,
1. add new clock mux data and change some
2. add new clock gate data and clock factor data
3. change status register offset of infra subsystem
Signed-off-by: Weiyi Lu
---
drivers/clk/mediatek/clk-mt2712.c | 69 +++
1 file
On Tue, 2017-11-28 at 15:28 +0800, Weiyi Lu wrote:
Hi Matthias,
Just gentle ping. Many thanks.
> This series is based on v4.15-rc1 and composed of
> scpsys control (PATCH 1-4) and device tree (PATCH 5-6)
>
> changes since v6:
> - Rebase to v4.15-rc1.
>
> changes sin
On Tue, 2017-11-28 at 15:28 +0800, Weiyi Lu wrote:
Hi Matthias,
Just gentle ping. Many thanks.
> This series is based on v4.15-rc1 and composed of
> scpsys control (PATCH 1-4) and device tree (PATCH 5-6)
>
> changes since v6:
> - Rebase to v4.15-rc1.
>
> changes sin
the frequency of clk32k/clkrtc_ext/clkrtc_int
changes since v1:
- Rebase to v4.13-next-soc.
- Refine scpsys and infracfg for bus protection.
*** BLURB HERE ***
Weiyi Lu (6):
dt-bindings: soc: add MT2712 power dt-bindings
soc: mediatek: extend bus protection API
soc: mediatek: add dependent clock
the frequency of clk32k/clkrtc_ext/clkrtc_int
changes since v1:
- Rebase to v4.13-next-soc.
- Refine scpsys and infracfg for bus protection.
*** BLURB HERE ***
Weiyi Lu (6):
dt-bindings: soc: add MT2712 power dt-bindings
soc: mediatek: extend bus protection API
soc: mediatek: add dependent clock
Add power dt-bindings for MT2712.
Acked-by: Rob Herring <r...@kernel.org>
Signed-off-by: Weiyi Lu <weiyi...@mediatek.com>
---
.../devicetree/bindings/soc/mediatek/scpsys.txt| 3 +++
include/dt-bindings/power/mt2712-power.h | 26 ++
2 files
Add power dt-bindings for MT2712.
Acked-by: Rob Herring
Signed-off-by: Weiyi Lu
---
.../devicetree/bindings/soc/mediatek/scpsys.txt| 3 +++
include/dt-bindings/power/mt2712-power.h | 26 ++
2 files changed, 29 insertions(+)
create mode 100644 include/dt
s "true" to use the legacy update method.
By improving the mtk-infracfg bus protection implementation to
support set/clear bus protection control method by IC configuration.
Signed-off-by: Weiyi Lu <weiyi...@mediatek.com>
---
drivers/soc/mediatek/mtk-infracfg.c | 26 ++
Add clock controller nodes for MT2712, include topckgen, infracfg,
pericfg, mcucfg and apmixedsys. This patch also add six oscillators that
provide clocks for MT2712.
Signed-off-by: Weiyi Lu <weiyi...@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt2712e.dtsi
s "true" to use the legacy update method.
By improving the mtk-infracfg bus protection implementation to
support set/clear bus protection control method by IC configuration.
Signed-off-by: Weiyi Lu
---
drivers/soc/mediatek/mtk-infracfg.c | 26
Add clock controller nodes for MT2712, include topckgen, infracfg,
pericfg, mcucfg and apmixedsys. This patch also add six oscillators that
provide clocks for MT2712.
Signed-off-by: Weiyi Lu
---
arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 115 ++
1 file changed, 115
add scpsys driver for MT2712
Signed-off-by: Weiyi Lu <weiyi...@mediatek.com>
---
drivers/soc/mediatek/mtk-scpsys.c | 106 +++---
1 file changed, 100 insertions(+), 6 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c
b/drivers/soc/mediatek/mtk-sc
This series is based on v4.15-rc1 and composed of
scpsys control (PATCH 1-4) and device tree (PATCH 5-6)
changes since v6:
- Rebase to v4.15-rc1.
changes since v5:
- Refine bus protection with proper variable name
and better implementation for the if statement.
changes since v4:
- Refine
This series is based on v4.15-rc1 and composed of
scpsys control (PATCH 1-4) and device tree (PATCH 5-6)
changes since v6:
- Rebase to v4.15-rc1.
changes since v5:
- Refine bus protection with proper variable name
and better implementation for the if statement.
changes since v4:
- Refine
add scpsys driver for MT2712
Signed-off-by: Weiyi Lu
---
drivers/soc/mediatek/mtk-scpsys.c | 106 +++---
1 file changed, 100 insertions(+), 6 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c
b/drivers/soc/mediatek/mtk-scpsys.c
index c0f3219..435ce5e
add power controller node for MT2712
Signed-off-by: Weiyi Lu <weiyi...@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
add power controller node for MT2712
Signed-off-by: Weiyi Lu
---
arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index 5703793..61dd763 100644
There are dependent clock jpgdec/audio in scpsys on MT2712,
and will exist three dependent clocks on MT2712 VDEC.
Signed-off-by: Weiyi Lu <weiyi...@mediatek.com>
---
drivers/soc/mediatek/mtk-scpsys.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/me
There are dependent clock jpgdec/audio in scpsys on MT2712,
and will exist three dependent clocks on MT2712 VDEC.
Signed-off-by: Weiyi Lu
---
drivers/soc/mediatek/mtk-scpsys.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c
b/drivers
Add clock controller nodes for MT2712, include topckgen, infracfg,
pericfg, mcucfg and apmixedsys. This patch also add six oscillators that
provide clocks for MT2712.
Signed-off-by: Weiyi Lu <weiyi...@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt2712e.dtsi
Add clock controller nodes for MT2712, include topckgen, infracfg,
pericfg, mcucfg and apmixedsys. This patch also add six oscillators that
provide clocks for MT2712.
Signed-off-by: Weiyi Lu
---
arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 115 ++
1 file changed, 115
There are dependent clock jpgdec/audio in scpsys on MT2712,
and will exist three dependent clocks on MT2712 VDEC.
Signed-off-by: Weiyi Lu <weiyi...@mediatek.com>
---
drivers/soc/mediatek/mtk-scpsys.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/me
s "true" to use the legacy update method.
By improving the mtk-infracfg bus protection implementation to
support set/clear bus protection control method by IC configuration.
Signed-off-by: Weiyi Lu <weiyi...@mediatek.com>
---
drivers/soc/mediatek/mtk-infracfg.c | 26 ++
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