> -Original Message-
> From: Bin Meng
> Sent: 16 December 2020 11:36
> To: Yash Shah
> Cc: linux-...@vger.kernel.org; linux-ser...@vger.kernel.org; linux-
> p...@vger.kernel.org; linux-...@vger.kernel.org; linux-kernel ker...@vger.kernel.org>; linux-riscv ;
> dev
> -Original Message-
> From: Bin Meng
> Sent: 10 December 2020 19:05
> To: Yash Shah
> Cc: linux-...@vger.kernel.org; linux-ser...@vger.kernel.org; linux-
> p...@vger.kernel.org; linux-...@vger.kernel.org; linux-kernel ker...@vger.kernel.org>; linux-riscv ;
> dev
SiFive FU740 has 4 ECC interrupt sources as compared to 3 in FU540.
Update the L2 cache controller driver to support this additional
interrupt in case of FU740-C000 chip.
Signed-off-by: Yash Shah
---
drivers/soc/sifive/sifive_l2_cache.c | 27 ---
1 file changed, 24
The L2 cache controller in SiFive FU740 has 4 ECC interrupt sources as
compared to 3 in FU540. Update the DT documentation accordingly with
"compatible" and "interrupt" property changes.
Signed-off-by: Yash Shah
---
.../devicetree/bindings/riscv/sifiv
Add support for additional interrupt present in SiFive FU740 chip.
Changes:
v3:
- Rename the subject line of dt-binding patch
- Add the additional interrupt "DirFail" as the last entry so as to keep
the order of all previous index same.
v2:
- Changes as per Rob Herring's request o
Any updates on this patch?
- Yash
> -Original Message-
> From: Yash Shah
> Sent: 12 November 2020 17:31
> To: robh...@kernel.org; Paul Walmsley ( Sifive)
> ; pal...@dabbelt.com; b...@alien8.de;
> mche...@kernel.org; tony.l...@intel.com; james.mo...@arm.com;
>
> -Original Message-
> From: Rob Herring
> Sent: 09 December 2020 04:52
> To: Yash Shah
> Cc: linux-kernel@vger.kernel.org; linux-ri...@lists.infradead.org;
> devicet...@vger.kernel.org; b...@suse.de; a...@brainfault.org;
> jonathan.came...@huawei.com; w...@kernel.o
Add initial board data for the SiFive HiFive Unmatched A00.
This patch is dependent on Zong's Patchset[0].
[0]:
https://lore.kernel.org/linux-riscv/20201130082330.77268-4-zong...@sifive.com/T/#u
Signed-off-by: Yash Shah
---
arch/riscv/boot/dts/sifive/Makefile| 3
Add initial support for the SiFive FU540-C000 SoC. FU740-C000 is built
around the SiFIve U7 Core Complex and a TileLink interconnect.
This file is expected to grow as more device drivers are added to the
kernel.
Signed-off-by: Yash Shah
---
arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 293
Add new compatible strings to the YAML DT binding document to support
SiFive's HiFive Unmatched board
Signed-off-by: Yash Shah
---
Documentation/devicetree/bindings/riscv/sifive.yaml | 17 -
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree
Add new compatible strings to the DT binding documents to support SiFive
FU740-C000.
Signed-off-by: Yash Shah
---
Documentation/devicetree/bindings/pwm/pwm-sifive.yaml | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/pwm/pwm
Add new compatible strings to the DT binding documents to support SiFive
FU740-C000.
Signed-off-by: Yash Shah
---
Documentation/devicetree/bindings/i2c/i2c-ocores.txt | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/i2c/i2c-ocores.txt
Add new compatible strings to the DT binding documents to support SiFive
FU740-C000.
Signed-off-by: Yash Shah
---
Documentation/devicetree/bindings/gpio/sifive,gpio.yaml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/gpio/sifive
Add new compatible strings to the DT binding documents to support SiFive
FU740-C000.
Signed-off-by: Yash Shah
---
Documentation/devicetree/bindings/serial/sifive-serial.yaml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/serial/sifive
Add new compatible strings in cpus.yaml to support the E71 and U74 CPU
cores ("harts") that are present on FU740-C000 SoC.
Signed-off-by: Yash Shah
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetre
Add new compatible strings to the DT binding documents to support SiFive
FU740-C000.
Signed-off-by: Yash Shah
---
Documentation/devicetree/bindings/spi/spi-sifive.yaml | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/spi/spi
-send-email-yash.s...@sifive.com/T/#t
[2]:
https://lore.kernel.org/linux-riscv/20201126030043.67390-1-zong...@sifive.com/T/#u
Changes in v2:
- The dt bindings patch is split into several individual patches.
- Expand the full list for compatible strings in i2c-ocores.txt
Yash Shah (9):
dt
> -Original Message-
> From: Andrew Lunn
> Sent: 02 December 2020 20:28
> To: Yash Shah
> Cc: linux-...@vger.kernel.org; linux-ser...@vger.kernel.org; linux-
> p...@vger.kernel.org; linux-...@vger.kernel.org; linux-
> ker...@vger.kernel.org; linux-ri...@lists.inf
Add initial board data for the SiFive HiFive Unmatched A00
Signed-off-by: Yash Shah
---
arch/riscv/boot/dts/sifive/Makefile| 3 +-
.../riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 253 +
2 files changed, 255 insertions(+), 1 deletion(-)
create mode
Add new compatible strings to the DT binding documents to support SiFive
FU740-C000. Also, add new compatible strings in cpus.yaml to support the
E71 and U74 CPU cores ("harts") that are present on FU740-C000 SoC.
Signed-off-by: Yash Shah
---
Documentation/devicetree/bindings/g
Add new compatible strings to the YAML DT binding document to support
SiFive's HiFive Unmatched board
Signed-off-by: Yash Shah
---
Documentation/devicetree/bindings/riscv/sifive.yaml | 17 -
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree
Add initial support for the SiFive FU540-C000 SoC. FU740-C000 is built
around the SiFIve U7 Core Complex and a TileLink interconnect.
This file is expected to grow as more device drivers are added to the
kernel.
Signed-off-by: Yash Shah
---
arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 293
-send-email-yash.s...@sifive.com/T/#t
[2]:
https://lore.kernel.org/linux-riscv/20201126030043.67390-1-zong...@sifive.com/T/#u
Yash Shah (4):
dt-bindings: riscv: Update DT binding docs to support SiFive FU740 SoC
riscv: dts: add initial support for the SiFive FU740-C000 SoC
dt-bindings: riscv
SiFive FU740 has 4 ECC interrupt sources as compared to 3 in FU540.
Update the L2 cache controller driver to support this additional
interrupt in case of FU740-C000 chip.
Signed-off-by: Yash Shah
---
drivers/soc/sifive/sifive_l2_cache.c | 49 +++-
1 file changed
The L2 cache controller in SiFive FU740 has 4 ECC interrupt sources as
compared to 3 in FU540. Update the DT documentation accordingly with
"compatible" and "interrupt" property changes.
Signed-off-by: Yash Shah
---
Changes in v2:
- Changes as per Rob Herring's request on v1
> -Original Message-
> From: Rob Herring
> Sent: 21 November 2020 18:25
> To: Yash Shah
> Cc: Paul Walmsley ( Sifive) ;
> pal...@dabbelt.com; a...@eecs.berkeley.edu;
> jonathan.came...@huawei.com; w...@kernel.org; s...@ravnborg.org;
> Sagar Kadam ; a...@brainf
Add DT json-schema for SiFive Bus Error unit present in FU740-C000 chip
Signed-off-by: Yash Shah
---
.../devicetree/bindings/riscv/sifive-beu.yaml | 47 ++
1 file changed, 47 insertions(+)
create mode 100644 Documentation/devicetree/bindings/riscv/sifive-beu.yaml
diff
Add driver support for Bus Error Unit present in SiFive's FU740 chip.
Currently the driver reports erroneous events only using Platform-level
interrupts. The support for reporting events using hart-local interrupts
can be added in future.
Signed-off-by: Yash Shah
---
drivers/soc/sifive/Kconfig
Register for ECC error events from SiFive BEU in SiFive platform EDAC
driver.
Signed-off-by: Yash Shah
---
drivers/edac/Kconfig | 2 +-
drivers/edac/sifive_edac.c | 13 +++--
2 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/edac/Kconfig b/drivers/edac
The L2 cache controller in SiFive FU740 has 4 ECC interrupt sources as
compared to 3 in FU540. Update the DT documentation accordingly with
"compatible" and "interrupt" property changes.
Signed-off-by: Yash Shah
---
.../devicetree/bindings/riscv/sifiv
SiFive FU740 has 4 ECC interrupt sources as compared to 3 in FU540.
Update the L2 cache controller driver to support this additional
interrupt in case of FU740-C000 chip.
Signed-off-by: Yash Shah
---
drivers/soc/sifive/sifive_l2_cache.c | 49 +++-
1 file changed
> -Original Message-
> From: Palmer Dabbelt
> Sent: 09 September 2020 08:42
> To: Christoph Hellwig ; dkang...@cadence.com
> Cc: Yash Shah ; robh...@kernel.org; Paul
> Walmsley ( Sifive) ; b...@alien8.de;
> mche...@kernel.org; tony.l...@intel.com; devic
Add device tree bindings for SiFive FU540 DDR controller driver
Signed-off-by: Yash Shah
Reviewed-by: Palmer Dabbelt
Acked-by: Palmer Dabbelt
---
.../devicetree/bindings/riscv/sifive-ddr.yaml | 41 ++
1 file changed, 41 insertions(+)
create mode 100644 Documentation
Changes in v2:
Incorporate below changes in EDAC patch as suggested by Borislav Petkov
- Replace all ifdeffery with if(IS_ENABLED(CONFIG_...))
- A few textual changes in patch description and code
Yash Shah (3):
dt-bindings: riscv: Add DT documentation for DDR Controller in SiFive
SoCs
soc
Add Memory controller EDAC support to the SiFive platform EDAC driver.
It registers for ECC notifier events from the memory controller.
Signed-off-by: Yash Shah
Reviewed-by: Palmer Dabbelt
Acked-by: Palmer Dabbelt
---
drivers/edac/Kconfig | 2 +-
drivers/edac/sifive_edac.c | 119
Add a driver to manage the Cadence DDR controller present on SiFive SoCs
At present the driver manages the EDAC feature of the DDR controller.
Additional features may be added to the driver in future to control
other aspects of the DDR controller.
Signed-off-by: Yash Shah
Reviewed-by: Palmer
> -Original Message-
> From: Borislav Petkov
> Sent: 31 August 2020 14:22
> To: Yash Shah
> Cc: robh...@kernel.org; pal...@dabbelt.com; Paul Walmsley ( Sifive)
> ; mche...@kernel.org; tony.l...@intel.com;
> a...@eecs.berkeley.edu; james.mo...@arm.com; rrich...@m
Add Memory controller EDAC support in exisiting SiFive platform EDAC
driver. It registers for notifier events from the SiFive DDR controller
driver for DDR ECC events.
Signed-off-by: Yash Shah
---
drivers/edac/Kconfig | 2 +-
drivers/edac/sifive_edac.c | 117
Add device tree bindings for SiFive FU540 DDR controller driver
Signed-off-by: Yash Shah
---
.../devicetree/bindings/riscv/sifive-ddr.yaml | 41 ++
1 file changed, 41 insertions(+)
create mode 100644 Documentation/devicetree/bindings/riscv/sifive-ddr.yaml
diff --git
Add a driver to manage the Cadence DDR controller present on SiFive SoCs
At present the driver manages the EDAC feature of the DDR controller.
Additional features may be added to the driver in future to control
other aspects of the DDR controller.
Signed-off-by: Yash Shah
---
drivers/soc/sifive
Yash Shah (3):
dt-bindings: riscv: Add DT documentation for DDR Controller in SiFive
SoCs
soc: sifive: Add SiFive specific Cadence DDR controller driver
edac: sifive: Add EDAC support for Memory Controller in SiFive SoCs
.../devicetree/bindings/riscv/sifive-ddr.yaml | 41
Hi Andreas,
> -Original Message-
> From: Andreas Schwab
> Sent: 01 July 2020 16:11
> To: Yash Shah
> Cc: Paul Walmsley ( Sifive) ;
> pal...@dabbelt.com; robh...@kernel.org; linux-ri...@lists.infradead.org;
> linux-kernel@vger.kernel.org; devicet...@vger.ker
> -Original Message-
> From: David Abdurachmanov
> Sent: 01 July 2020 17:34
> To: Andreas Schwab
> Cc: Yash Shah ; devicet...@vger.kernel.org; Albert
> Ou ; Atish Patra ; Anup
> Patel ; lolliv...@baylibre.com; linux-
> ker...@vger.kernel.org List ; Green Wan
&
v kernel, the
mmap call should fail for this particular combination of permission bits
since it's not valid.
[0]: https://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-161.pdf
Signed-off-by: Yash Shah
Reported-by: David Abdurachmanov
---
arch/riscv/kernel/sys_riscv.c | 6 ++
1 file
.
Signed-off-by: Yash Shah
---
arch/riscv/Kconfig | 8
arch/riscv/configs/defconfig | 5 +
2 files changed, 13 insertions(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index a31e1a4..1c8443e 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -381,6 +381,14
Declare that each hart defined in the FU540 DT data is clocked by the
COREPLL. This is in preparation for enabling CPUFreq for the
FU540-C000 SoC on the HiFive Unleashed board.
Signed-off-by: Yash Shah
---
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 5 +
1 file changed, 5 insertions
The patch series adds the support for dynamic CPU frequency switching
for FU540-C000 SoC on the HiFive Unleashed board. All the patches are
based on Paul Walmsley's work.
This series is based on Linux v5.7 and tested on HiFive unleashed board.
Yash Shah (3):
riscv: defconfig, Kconfig: enable
, the 1GHz rate is present solely because the default HiFive
Unleashed bootloaders set the CPU to run at 1GHz before starting the
kernel.
Signed-off-by: Yash Shah
---
.../riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 38 ++
1 file changed, 38 insertions(+)
diff --git a/arch
00-pwm". I
will add it along with "sifive,pwm0" and repost as version 2.
Thanks for your comment.
- Yash
>
> >
> > - Yash
> >
> > On Wed, Aug 21, 2019 at 2:53 PM Yash Shah wrote:
> >>
> >> Add the PWM DT node in SiFive F
Hi,
Any comments on this patch?
- Yash
On Wed, Aug 21, 2019 at 2:53 PM Yash Shah wrote:
>
> Add the PWM DT node in SiFive FU540 soc-specific DT file.
> Enable the PWM nodes in HiFive Unleashed board-specific DT file.
>
> Signed-off-by: Yash Shah
> ---
> arch/riscv/boot/
On Thu, Aug 29, 2019 at 2:36 AM David Miller wrote:
>
> From: Yash Shah
> Date: Tue, 27 Aug 2019 10:36:02 +0530
>
> > This patch series renames the compatible property to a more appropriate
> > string. The patchset is based on Linux-5.3-rc6 and tested on SiFive
> >
Update the compatibility string for SiFive FU540-C000 as per the new
string updated in the binding doc.
Reference:
https://lore.kernel.org/netdev/caj2_jofevzqat0yprg4hem4jrrqkb72fkseqj4p8p5ka-+r...@mail.gmail.com/
Signed-off-by: Yash Shah
Acked-by: Nicolas Ferre
Reviewed-by: Paul Walmsley
As per the discussion with Nicolas Ferre[0], rename the compatible property
to a more appropriate and specific string.
[0]
https://lore.kernel.org/netdev/caj2_jofevzqat0yprg4hem4jrrqkb72fkseqj4p8p5ka-+r...@mail.gmail.com/
Signed-off-by: Yash Shah
Acked-by: Nicolas Ferre
Reviewed-by: Paul
to a
'lore.kernel.org' link instead of 'lkml.org'
Yash Shah (2):
macb: bindings doc: update sifive fu540-c000 binding
macb: Update compatibility string for SiFive FU540-C000
Documentation/devicetree/bindings/net/macb.txt | 4 ++--
drivers/net/ethernet/cadence/macb_main.c | 2 +-
2 files
Add the PWM DT node in SiFive FU540 soc-specific DT file.
Enable the PWM nodes in HiFive Unleashed board-specific DT file.
Signed-off-by: Yash Shah
---
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 19 +++
arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 8
On Mon, Aug 19, 2019 at 11:56 AM Christoph Hellwig wrote:
>
> On Mon, Aug 19, 2019 at 08:09:04AM +0200, Borislav Petkov wrote:
> > On Sun, Aug 18, 2019 at 10:29:35AM +0200, Christoph Hellwig wrote:
> > > The sifive_l2_cache.c is in no way related to RISC-V architecture
> > > memory management.
On Fri, Jul 19, 2019 at 5:36 PM wrote:
>
> On 19/07/2019 at 13:10, Yash Shah wrote:
> > Update the compatibility string for SiFive FU540-C000 as per the new
> > string updated in the binding doc.
> > Reference: https://lkml.org/lkml/2019/7/17/200
>
> Maybe referrin
Update the compatibility string for SiFive FU540-C000 as per the new
string updated in the binding doc.
Reference: https://lkml.org/lkml/2019/7/17/200
Signed-off-by: Yash Shah
---
drivers/net/ethernet/cadence/macb_main.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
DT node for SiFive FU540-C000 GEMGXL Ethernet controller driver added
Signed-off-by: Yash Shah
---
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 15 +++
arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 9 +
2 files changed, 24 insertions(+)
diff --git a/arch
As per the discussion with Nicolas Ferre, rename the compatible property
to a more appropriate and specific string.
LINK: https://lkml.org/lkml/2019/7/17/200
Signed-off-by: Yash Shah
---
Documentation/devicetree/bindings/net/macb.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions
On Mon, Jun 24, 2019 at 9:08 PM wrote:
>
> On 23/05/2019 at 22:50, Rob Herring wrote:
> > On Thu, May 23, 2019 at 6:46 AM Yash Shah wrote:
> >>
> >> Add the compatibility string documentation for SiFive FU540-C
> >> interface.
> >> On the
Reading the count register clears the interrupt signal. Currently, the
count registers are read into 'regval' variable but the variable is
never used. Therefore remove it. V2 of this patch add comments to
justify the readl calls without checking the return value.
Signed-off-by: Yash Shah
On Thu, Jun 27, 2019 at 9:43 PM Paul Walmsley wrote:
>
> On Thu, 27 Jun 2019, Yash Shah wrote:
>
> > Reading the count register clears the interrupt signal. Currently, the
> > count registers are read into 'regval' variable but the variable is
> > never used. Therefor
Reading the count register clears the interrupt signal. Currently, the
count registers are read into 'regval' variable but the variable is
never used. Therefore remove it.
Signed-off-by: Yash Shah
---
arch/riscv/mm/sifive_l2_cache.c | 8
1 file changed, 4 insertions(+), 4 deletions
As per the convention for any SOC device with external connection,
define only device DT node in SOC DTSi file with status = "disabled"
and enable device in Board DTS file with status = "okay"
Reported-by: Anup Patel
Signed-off-by: Yash Shah
---
arch/riscv/boot/dts/si
On Tue, Jun 25, 2019 at 2:53 AM Paul Walmsley wrote:
>
> On Mon, 24 Jun 2019, Yash Shah wrote:
>
> > As per the General convention, define only device DT node in SOC DTSi
> > file with status = "disabled" and enable device in Board DTS file with
> > status = &
As per the General convention, define only device DT node in SOC DTSi
file with status = "disabled" and enable device in Board DTS file with
status = "okay"
Reported-by: Anup Patel
Signed-off-by: Yash Shah
---
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 3 +++
DT node for SiFive FU540-C000 GEMGXL Ethernet controller driver added
Signed-off-by: Yash Shah
---
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 16
arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 9 +
2 files changed, 25 insertions(+)
diff --git a/arch
Change history:
v2:
- Set "status = disabled" in DTSI file and enable it in Board DTS file
- Move PHY related nodes into board DTS file
Yash Shah (1):
riscv: dts: Add DT node for SiFive FU540 Ethernet controller driver
arch/riscv/boot/dts/sifive/fu540-c000.dtsi
On Fri, Jun 21, 2019 at 2:31 PM Anup Patel wrote:
>
> On Fri, Jun 21, 2019 at 11:40 AM Yash Shah wrote:
> >
> > DT node for SiFive FU540-C000 GEMGXL Ethernet controller driver added
> >
> > Signed-off-by: Yash Shah
> > ---
> > arch/
Yash Shah (1):
riscv: dts: Add DT node for SiFive FU540 Ethernet controller driver
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 20
1 file changed, 20 insertions(+)
--
1.9.1
DT node for SiFive FU540-C000 GEMGXL Ethernet controller driver added
Signed-off-by: Yash Shah
---
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 20
1 file changed, 20 insertions(+)
diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
b/arch/riscv/boot/dts/sifive/fu540
.
Signed-off-by: Yash Shah
---
drivers/net/ethernet/cadence/macb_main.c | 123 +++
1 file changed, 123 insertions(+)
diff --git a/drivers/net/ethernet/cadence/macb_main.c
b/drivers/net/ethernet/cadence/macb_main.c
index c049410..15d0737 100644
--- a/drivers/net
register.
- Fix the issue of probe fail on reloading the module reported by:
Andreas Schwab
Yash Shah (2):
macb: bindings doc: add sifive fu540-c000 binding
macb: Add support for SiFive FU540-C000
Documentation/devicetree/bindings/net/macb.txt | 3 +
drivers/net/ethernet/cadence/macb_main.c
additional range to "reg" property for SiFive GEMGXL
management IP registers.
Signed-off-by: Yash Shah
Reviewed-by: Paul Walmsley
---
Documentation/devicetree/bindings/net/macb.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/m
On Mon, Jun 17, 2019 at 9:28 PM Andrew Lunn wrote:
>
> On Mon, Jun 17, 2019 at 09:49:27AM +0530, Yash Shah wrote:
...
> > static const struct macb_config at91sam9260_config = {
> > .caps = MACB_CAPS_USRIO_HAS_CLKEN |
> > MACB_CAPS_USRIO_DEFAULT_IS_MII_G
On Mon, Jun 17, 2019 at 3:58 PM Paul Walmsley wrote:
>
> On Mon, 17 Jun 2019, Yash Shah wrote:
>
> > On Mon, Jun 17, 2019 at 3:28 PM Paul Walmsley
> > wrote:
> >
> > > On Mon, 17 Jun 2019, Andreas Schwab wrote:
> > >
> > > >
On Mon, Jun 17, 2019 at 3:28 PM Paul Walmsley wrote:
>
> Hi Yash,
>
> On Mon, 17 Jun 2019, Andreas Schwab wrote:
>
> > On Jun 17 2019, Yash Shah wrote:
> >
> > > - Add "MACB_SIFIVE_FU540" in Kconfig to support SiFive FU540 in macb
> > > d
On Mon, Jun 17, 2019 at 9:49 AM Yash Shah wrote:
>
> On FU540, the management IP block is tightly coupled with the Cadence
> MACB IP block. It manages many of the boundary signals from the MACB IP
> This patchset controls the tx_clk input signal to the MACB IP. It
> switches betwe
.
Signed-off-by: Yash Shah
---
drivers/net/ethernet/cadence/Kconfig | 6 ++
drivers/net/ethernet/cadence/macb_main.c | 129 +++
2 files changed, 135 insertions(+)
diff --git a/drivers/net/ethernet/cadence/Kconfig
b/drivers/net/ethernet/cadence/Kconfig
index
additional range to "reg" property for SiFive GEMGXL
management IP registers.
Signed-off-by: Yash Shah
---
Documentation/devicetree/bindings/net/macb.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/macb.txt
b/Documentation/devicetree/bi
SiFive FU540 in macb
driver. This is needed because on FU540, the macb driver depends on
SiFive GPIO driver.
- Avoid writing the result of a comparison to a register.
- Fix the issue of probe fail on reloading the module reported by:
Andreas Schwab
Yash Shah (2):
macb: bindings doc: add sifive fu540-c0
Adds a PWM driver for PWM chip present in SiFive's HiFive Unleashed SoC.
Signed-off-by: Wesley W. Terpstra
[Atish: Various fixes and code cleanup]
Signed-off-by: Atish Patra
Signed-off-by: Yash Shah
---
drivers/pwm/Kconfig | 11 ++
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm
DT documentation for PWM controller added.
Signed-off-by: Wesley W. Terpstra
[Atish: Compatible string update]
Signed-off-by: Atish Patra
Signed-off-by: Yash Shah
Reviewed-by: Rob Herring
---
.../devicetree/bindings/pwm/pwm-sifive.txt | 33 ++
1 file changed, 33
in driver name
- Remove use of of_match_ptr macro
- Update the DT compatible strings and Add reference to a common
versioning document
Yash Shah (2):
pwm: sifive: Add DT documentation for SiFive PWM Controller
pwm: sifive: Add a driver for SiFive SoC PWM
.../devicetree/bindings/pwm/pwm-sifive.txt
On Mon, May 27, 2019 at 1:34 PM Andreas Schwab wrote:
>
> On Mai 24 2019, Yash Shah wrote:
>
> > Hi Andreas,
> >
> > On Thu, May 23, 2019 at 6:19 PM Andreas Schwab wrote:
> >>
> >> On Mai 23 2019, Yash Shah wrote:
> >>
>
On Fri, May 24, 2019 at 2:20 AM Rob Herring wrote:
>
> On Thu, May 23, 2019 at 6:46 AM Yash Shah wrote:
> >
> > Add the compatibility string documentation for SiFive FU540-C
> > interface.
> > On the FU540, this driver also needs to read and write register
On Thu, May 23, 2019 at 9:58 PM David Miller wrote:
>
>
> Please be consistent in your subsystem prefixes used in your Subject lines.
> You use "net: macb:" then "net/macb:" Really, plain "macb: " is sufficient.
Sure, Will take care of this in the next revision of this patch.
Thanks for your
On Thu, May 23, 2019 at 8:24 PM Andrew Lunn wrote:
>
> > +static int fu540_macb_tx_set_rate(struct clk_hw *hw, unsigned long rate,
> > + unsigned long parent_rate)
> > +{
> > + rate = fu540_macb_tx_round_rate(hw, rate, _rate);
> > + iowrite32(rate !=
Hi Andreas,
On Thu, May 23, 2019 at 6:19 PM Andreas Schwab wrote:
>
> On Mai 23 2019, Yash Shah wrote:
>
> > On FU540, the management IP block is tightly coupled with the Cadence
> > MACB IP block. It manages many of the boundary signals from the MACB IP
> > This p
.
Signed-off-by: Yash Shah
---
drivers/net/ethernet/cadence/macb_main.c | 118 +++
1 file changed, 118 insertions(+)
diff --git a/drivers/net/ethernet/cadence/macb_main.c
b/drivers/net/ethernet/cadence/macb_main.c
index c049410..a9e5227 100644
--- a/drivers/net
additional range to "reg" property for SiFive GEMGXL
management IP registers.
Signed-off-by: Yash Shah
---
Documentation/devicetree/bindings/net/macb.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/macb.txt
b/Documentation/devicetree/bi
patches needed for testing can be
found at dev/yashs/ethernet branch of:
https://github.com/yashshah7/riscv-linux.git
Yash Shah (2):
net/macb: bindings doc: add sifive fu540-c000 binding
net: macb: Add support for SiFive FU540-C000
Documentation/devicetree/bindings/net/macb.txt | 3 +
drivers
On Mon, May 6, 2019 at 4:57 PM Yash Shah wrote:
>
> The initial ver of EDAC driver supports:
> - ECC event monitoring and reporting through the EDAC framework for SiFive
> L2 cache controller.
>
> The EDAC driver registers for notifier events from the L2 cache controller
>
Adds a PWM driver for PWM chip present in SiFive's HiFive Unleashed SoC.
Signed-off-by: Wesley W. Terpstra
[Atish: Various fixes and code cleanup]
Signed-off-by: Atish Patra
Signed-off-by: Yash Shah
---
drivers/pwm/Kconfig | 11 ++
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm
DT documentation for PWM controller added.
Signed-off-by: Wesley W. Terpstra
[Atish: Compatible string update]
Signed-off-by: Atish Patra
Signed-off-by: Yash Shah
Reviewed-by: Rob Herring
---
.../devicetree/bindings/pwm/pwm-sifive.txt | 33 ++
1 file changed, 33
versioning document
Yash Shah (2):
pwm: sifive: Add DT documentation for SiFive PWM Controller
pwm: sifive: Add a driver for SiFive SoC PWM
.../devicetree/bindings/pwm/pwm-sifive.txt | 33 ++
drivers/pwm/Kconfig| 11 +
drivers/pwm/Makefile
On Tue, May 7, 2019 at 7:15 PM Andrew F. Davis wrote:
>
> On 5/7/19 2:48 AM, Yash Shah wrote:
> > On Mon, May 6, 2019 at 5:48 PM Andrew F. Davis wrote:
> >>
> >> On 5/6/19 6:48 AM, Yash Shah wrote:
> >>> The driver currently supports only SiFive FU
Hi Andreas,
On Tue, May 7, 2019 at 3:09 PM Andreas Schwab wrote:
>
> On Mai 02 2019, Yash Shah wrote:
>
> > The PWM default output state is high (When duty cycle is 0), So I
> > guess leds will remain on by default.
>
> So that's the bug that needs to be fixed.
Sorr
On Mon, May 6, 2019 at 5:48 PM Andrew F. Davis wrote:
>
> On 5/6/19 6:48 AM, Yash Shah wrote:
> > The driver currently supports only SiFive FU540-C000 platform.
> >
> > The initial version of L2 cache controller driver includes:
> > - Initial configuration repor
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