On Sat, 2021-04-17 at 10:52 +0200, Hans de Goede wrote:
> Hi David,
>
> On 4/17/21 5:12 AM, David E. Box wrote:
> > From: Gayatri Kammela
> >
> > Platforms that support low power modes (LPM) such as Tiger Lake
> > maintain
> > requirements for each sub-state that a readable in the PMC.
> >
On Sat, 2021-04-17 at 11:00 +0200, Hans de Goede wrote:
> Hi,
>
> On 4/17/21 5:12 AM, David E. Box wrote:
> > From: Gayatri Kammela
> >
> > Platforms that support low power modes (LPM) such as Tiger Lake
> > maintain
> > requirements for each sub-state that a readable in the PMC.
> > However,
Hi,
On 4/17/21 5:12 AM, David E. Box wrote:
> From: Gayatri Kammela
>
> Platforms that support low power modes (LPM) such as Tiger Lake maintain
> requirements for each sub-state that a readable in the PMC. However, unlike
> LPM status registers, requirement registers are not memory mapped but
Hi David,
On 4/17/21 5:12 AM, David E. Box wrote:
> From: Gayatri Kammela
>
> Platforms that support low power modes (LPM) such as Tiger Lake maintain
> requirements for each sub-state that a readable in the PMC. However, unlike
> LPM status registers, requirement registers are not memory
Hi "David,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on 823b31517ad3196324322804ee365d5fcff704d6]
url:
https://github.com/0day-ci/linux/commits/David-E-Box/intel_pmc_core-Add-sub-state-requirements-and-mode/20210417-111530
base:
Hi "David,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on 823b31517ad3196324322804ee365d5fcff704d6]
url:
https://github.com/0day-ci/linux/commits/David-E-Box/intel_pmc_core-Add-sub-state-requirements-and-mode/20210417-111530
base:
From: Gayatri Kammela
Platforms that support low power modes (LPM) such as Tiger Lake maintain
requirements for each sub-state that a readable in the PMC. However, unlike
LPM status registers, requirement registers are not memory mapped but are
available from an ACPI _DSM. Collect the
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