Re: [PATCH v11 3/6] clk: ralink: add clock driver for mt7621 SoC

Hi, On Fri, Apr 9, 2021 at 8:14 PM Stephen Boyd wrote: > > Quoting Sergio Paracuellos (2021-03-08 21:22:23) > > diff --git a/drivers/clk/ralink/Kconfig b/drivers/clk/ralink/Kconfig > > new file mode 100644 > > index ..3e3f5cb9ad88 > > --- /dev/null > > +++

Re: [PATCH v11 3/6] clk: ralink: add clock driver for mt7621 SoC

Quoting Sergio Paracuellos (2021-03-08 21:22:23) > diff --git a/drivers/clk/ralink/Kconfig b/drivers/clk/ralink/Kconfig > new file mode 100644 > index ..3e3f5cb9ad88 > --- /dev/null > +++ b/drivers/clk/ralink/Kconfig > @@ -0,0 +1,15 @@ > +# SPDX-License-Identifier: GPL-2.0-only > +# >

[PATCH v11 3/6] clk: ralink: add clock driver for mt7621 SoC

The documentation for this SOC only talks about two registers regarding to the clocks: * SYSC_REG_CPLL_CLKCFG0 - provides some information about boostrapped refclock. PLL and dividers used for CPU and some sort of BUS. * SYSC_REG_CPLL_CLKCFG1 - a banch of gates to enable/disable clocks for all or