Hi Dilip,
On Tue, Sep 3, 2019 at 12:20 PM Dilip Kota wrote:
>
> Hi Martin,
>
> On 8/29/2019 10:54 AM, Chuan Hua, Lei wrote:
>
>
> On 8/29/2019 3:36 AM, Martin Blumenstingl wrote:
>
> On Wed, Aug 28, 2019 at 5:35 AM Chuan Hua, Lei
> wrote:
> [...]
>
> +static int intel_pcie_ep_rst_init(struct
Hi Kishon,
On Thu, Aug 29, 2019 at 7:10 AM Kishon Vijay Abraham I wrote:
[...]
> The PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION defines the Power
> Sequencing and Reset Signal Timings in Table 2-4. Please also refer Figure
> 2-10: Power Up of the CEM.
>
>
Hi Martin,
On 28/08/19 2:08 AM, Martin Blumenstingl wrote:
> Hello,
>
> On Tue, Aug 27, 2019 at 5:09 AM Chuan Hua, Lei
> wrote:
>>
>> Hi Martin,
>>
>> Thanks for your feedback. Please check the comments below.
>>
>> On 8/27/2019 5:15 AM, Martin Blumenstingl wrote:
>>> Hello,
>>>
>>> On Mon, Aug
On 8/29/2019 3:36 AM, Martin Blumenstingl wrote:
On Wed, Aug 28, 2019 at 5:35 AM Chuan Hua, Lei
wrote:
[...]
+static int intel_pcie_ep_rst_init(struct intel_pcie_port *lpp)
+{
+struct device *dev = lpp->pci->dev;
+int ret = 0;
+
+lpp->reset_gpio = devm_gpiod_get(dev, "reset",
On Wed, Aug 28, 2019 at 5:35 AM Chuan Hua, Lei
wrote:
[...]
> >> +static int intel_pcie_ep_rst_init(struct intel_pcie_port *lpp)
> >> +{
> >> +struct device *dev = lpp->pci->dev;
> >> +int ret = 0;
> >> +
> >> +lpp->reset_gpio = devm_gpiod_get(dev, "reset",
Hi Martin,
Thanks for your comment.
On 8/28/2019 4:38 AM, Martin Blumenstingl wrote:
Hello,
On Tue, Aug 27, 2019 at 5:09 AM Chuan Hua, Lei
wrote:
Hi Martin,
Thanks for your feedback. Please check the comments below.
On 8/27/2019 5:15 AM, Martin Blumenstingl wrote:
Hello,
On Mon, Aug 26,
Hi Dilip,
On Tue, Aug 27, 2019 at 10:47 AM Dilip Kota wrote:
[...]
> >
> >
> >> now I am wondering:
> >> - if we don't have to disable the interrupt line (once it is enabled),
> >> why can't we enable all of these interrupts at initialization time
> >> (instead of doing it on-demand)?
> > Good
Hello,
On Tue, Aug 27, 2019 at 5:09 AM Chuan Hua, Lei
wrote:
>
> Hi Martin,
>
> Thanks for your feedback. Please check the comments below.
>
> On 8/27/2019 5:15 AM, Martin Blumenstingl wrote:
> > Hello,
> >
> > On Mon, Aug 26, 2019 at 5:31 AM Chuan Hua, Lei
> > wrote:
> >> Hi Martin,
> >>
> >>
On Mon, Aug 26, 2019 at 11:15:48PM +0200, Martin Blumenstingl wrote:
> On Mon, Aug 26, 2019 at 5:31 AM Chuan Hua, Lei
> wrote:
> > As I mentioned, VRX200 was a very old PCIe Gen1.1 product. In our latest
> > SoC Lightning
> >
> > Mountain, we are using synopsys controller 5.20/5.50a. We support
On 8/27/2019 4:14 AM, Martin Blumenstingl wrote:
second example: pcie-tegra194 (only in -next, will be part of v5.4)
struct tegra_pcie_dw {
...
struct dw_pcie pci;
...
};
so some drivers store a pointer pointer to the dw_pcie struct vs.
embedding the dw_pcie struct
Hi Martin,
On 8/27/2019 11:09 AM, Chuan Hua, Lei wrote:
[...]
now I am wondering:
- if we don't have to disable the interrupt line (once it is enabled),
why can't we enable all of these interrupts at initialization time
(instead of doing it on-demand)?
Good point! we even can remote map_irq
Hi Martin,
Thanks for your feedback. Please check the comments below.
On 8/27/2019 5:15 AM, Martin Blumenstingl wrote:
Hello,
On Mon, Aug 26, 2019 at 5:31 AM Chuan Hua, Lei
wrote:
Hi Martin,
Thanks for your valuable comments. I reply some of them as below.
you're welcome
[...]
+config
Hello,
On Mon, Aug 26, 2019 at 5:31 AM Chuan Hua, Lei
wrote:
>
> Hi Martin,
>
> Thanks for your valuable comments. I reply some of them as below.
you're welcome
[...]
> >> +config PCIE_INTEL_AXI
> >> +bool "Intel AHB/AXI PCIe host controller support"
> > I believe that this is mostly
Hi Dilip,
On Mon, Aug 26, 2019 at 8:42 AM Dilip Kota wrote:
[...]
> intel_pcie_port structure is having "struct dw_pcie" as mentioned below:
>
> struct intel_pcie_port {
> struct dw_pcie *pci;
> unsigned intid; /* Physical RC Index */
> void __iomem
[Got delivery failure mail , so re-sending the mail]
Hi Martin,
Thanks for review comments, please find my response inline.
On 8/26/2019 11:30 AM, Chuan Hua, Lei wrote:
Hi Martin,
Thanks for your valuable comments. I reply some of them as below.
Regards,
Chuanhua
On 8/25/2019 5:03 AM,
Hi Martin,
Thanks for your valuable comments. I reply some of them as below.
Regards,
Chuanhua
On 8/25/2019 5:03 AM, Martin Blumenstingl wrote:
Hi Dilip,
first of all: thank you for submitting this upstream!
I hope that we can use this driver to replace the out-of-tree PCIe
driver that's
Hi Dilip,
first of all: thank you for submitting this upstream!
I hope that we can use this driver to replace the out-of-tree PCIe
driver that's used in OpenWrt for the Lantiq VRX200 SoCs.
a small disclaimer: I don't have access to any Lantiq, Intel or
DesignWare datasheets. so everything I
Add support to PCIe RC controller on Intel Universal
Gateway SoC. PCIe controller is based of Synopsys
Designware pci core.
Signed-off-by: Dilip Kota
---
drivers/pci/controller/dwc/Kconfig | 13 +
drivers/pci/controller/dwc/Makefile | 1 +
18 matches
Mail list logo
