Re: [PATCH v4 3/6] clk: ralink: add clock driver for mt7621 SoC

On Thu, Dec 17, 2020 at 11:12 AM Stephen Boyd wrote: > > Quoting Sergio Paracuellos (2020-12-17 01:54:18) > > > > On Thu, Dec 17, 2020 at 10:09 AM Stephen Boyd wrote: > > > > > > Quoting Sergio Paracuellos (2020-11-22 01:55:53) > > > > diff --git a/drivers/clk/ralink/Makefile

Re: [PATCH v4 3/6] clk: ralink: add clock driver for mt7621 SoC

Hi Stephen, Thanks for the review. On Thu, Dec 17, 2020 at 10:09 AM Stephen Boyd wrote: > > Quoting Sergio Paracuellos (2020-11-22 01:55:53) > > The documentation for this SOC only talks about two > > registers regarding to the clocks: > > * SYSC_REG_CPLL_CLKCFG0 - provides some information

Re: [PATCH v4 3/6] clk: ralink: add clock driver for mt7621 SoC

Quoting Sergio Paracuellos (2020-11-22 01:55:53) > The documentation for this SOC only talks about two > registers regarding to the clocks: > * SYSC_REG_CPLL_CLKCFG0 - provides some information about > boostrapped refclock. PLL and dividers used for CPU and some > sort of BUS. > *

[PATCH v4 3/6] clk: ralink: add clock driver for mt7621 SoC

The documentation for this SOC only talks about two registers regarding to the clocks: * SYSC_REG_CPLL_CLKCFG0 - provides some information about boostrapped refclock. PLL and dividers used for CPU and some sort of BUS. * SYSC_REG_CPLL_CLKCFG1 - a banch of gates to enable/disable clocks for all or